[f40a309] | 1 | /*
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| 2 | =============================================================================
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| 3 | patch.h -- MIDAS-VII Patch facility definitions
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| 4 | Version 22 -- 1988-12-02 -- D.N. Lynx Crowe
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| 5 | =============================================================================
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| 6 | */
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| 7 |
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[f7428b1] | 8 | #pragma once
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[5fa506d] | 9 |
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[f7428b1] | 10 | #include "stdint.h"
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| 11 |
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[f40a309] | 12 | #define MAXPATCH 256 /* patch table size */
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| 13 | #define RAWDEFS 256 /* def table size */
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| 14 |
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| 15 | #define NSLINES 1000 /* sequence table size */
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| 16 | #define NSEQW 7 /* number of words in a seqent */
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| 17 |
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| 18 | #define SEQTIME 10 /* milliseconds per tick */
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| 19 |
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| 20 | #define DATAROW 9 /* data entry row */
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| 21 |
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| 22 | #define NDEFSTMS 5120 /* number of stms/defs */
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| 23 | #define NPTEQELS 256 /* number of trigger fifo entries */
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| 24 |
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[f7428b1] | 25 | #define NPTEQLO (NPTEQELS >> 2) /* trigger fifo lo water */
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| 26 | #define NPTEQHI (NPTEQELS - NPTEQLO)
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| 27 | /* trigger fifo hi water */
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[f40a309] | 28 |
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| 29 | #define NULL_DEF 0x1200 /* blank definer code */
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| 30 |
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| 31 | #define ADR_MASK 0x00FF /* patch / defent table index mask */
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| 32 | #define TRG_MASK 0x1FFF /* trigger mask */
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| 33 | #define PE_SPEC 0x00FF /* destination mask */
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| 34 | #define PE_TBIT 0x8000 /* DEF triggered bit */
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| 35 |
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| 36 | /* Patch structure definitions */
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| 37 |
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| 38 | struct patch { /* patch table entry (16 bytes per entry) */
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| 39 |
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[f537c48] | 40 | int16_t nextstm; /* index of next entry in stm chain */
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| 41 | int16_t prevstm; /* index of previous entry in stm chain */
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[7258c6a] | 42 | uint16_t defnum; /* definer */
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| 43 | uint16_t stmnum; /* stimulus */
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| 44 | uint16_t paspec; /* destination type and flags */
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| 45 | uint16_t pasuba; /* sub-address */
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| 46 | uint16_t padat1; /* data word 1 */
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| 47 | uint16_t padat2; /* data word 2 */
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[f40a309] | 48 | };
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| 49 |
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| 50 | struct defent { /* definition table entry -- 10 bytes per entry */
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| 51 |
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[f537c48] | 52 | int16_t nextdef; /* index of next in def chain */
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[7258c6a] | 53 | uint16_t stm; /* stimulus */
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| 54 | uint16_t adspec; /* destination type */
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| 55 | uint16_t adsuba; /* sub-address */
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| 56 | uint16_t addat1; /* data word 1 */
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[f40a309] | 57 | };
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| 58 |
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| 59 |
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| 60 | /* Sequence structure definitions */
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| 61 |
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| 62 | struct seqent { /* sequence table entry -- 14 bytes per entry */
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| 63 |
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[7258c6a] | 64 | uint16_t seqtime; /* time */
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| 65 | uint16_t seqact1; /* action 1 */
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| 66 | uint16_t seqdat1; /* action 1 data */
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| 67 | uint16_t seqact2; /* action 2 */
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| 68 | uint16_t seqdat2; /* action 2 data */
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| 69 | uint16_t seqact3; /* action 3 */
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| 70 | uint16_t seqdat3; /* action 3 data */
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[f40a309] | 71 | };
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| 72 |
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| 73 | /* Patch destination types */
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| 74 |
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| 75 | #define PA_KEY 1
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| 76 | #define PA_TRG 2
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| 77 | #define PA_PLS 3
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| 78 | #define PA_LED 4
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| 79 | #define PA_SLIN 5
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| 80 | #define PA_SCTL 6
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| 81 | #define PA_TUNE 7
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| 82 | #define PA_RSET 8
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| 83 | #define PA_RADD 9
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| 84 | #define PA_INST 10
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| 85 | #define PA_OSC 11
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| 86 | #define PA_WAVA 12
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| 87 | #define PA_WAVB 13
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| 88 | #define PA_CNFG 14
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| 89 | #define PA_LEVL 15
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| 90 | #define PA_INDX 16
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| 91 | #define PA_FREQ 17
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| 92 | #define PA_FILT 18
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| 93 | #define PA_FILQ 19
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| 94 | #define PA_LOCN 20
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| 95 | #define PA_DYNM 21
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| 96 | #define PA_AUX 22
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| 97 | #define PA_RATE 23
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| 98 | #define PA_INTN 24
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| 99 | #define PA_DPTH 25
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| 100 | #define PA_VOUT 26
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| 101 |
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| 102 | /* Patch sub-address types */
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| 103 |
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| 104 | #define PSA_SRC 0
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| 105 | #define PSA_MLT 1
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| 106 | #define PSA_TIM 2
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| 107 | #define PSA_VAL 3
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| 108 | #define PSA_FNC 4
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| 109 |
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| 110 | /* Patch oscillator data types */
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| 111 |
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| 112 | #define PSO_INT 0
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| 113 | #define PSO_RAT 1
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| 114 | #define PSO_FRQ 2
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| 115 | #define PSO_PCH 3
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| 116 |
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| 117 | /* Sequence control flags */
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| 118 |
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| 119 | #define SQF_RUN 0x8000 /* RUN state */
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| 120 | #define SQF_CLK 0x4000 /* CLK state */
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| 121 |
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| 122 | /* Sequence action word masks */
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| 123 |
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| 124 | #define SQ_MACT 0x00FF /* ACT -- action mask */
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| 125 | #define SQ_MOBJ 0xFF00 /* ACT -- object mask */
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| 126 |
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| 127 | /* Sequence action types */
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| 128 |
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| 129 | #define SQ_NULL 0x0000 /* NULL action */
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| 130 |
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| 131 | #define SQ_CKEY 0x0001 /* Key closure */
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| 132 | #define SQ_RKEY 0x0002 /* Key release */
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| 133 | #define SQ_TKEY 0x0003 /* Key transient */
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| 134 | #define SQ_IKEY 0x0004 /* If key active */
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| 135 |
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| 136 | #define SQ_STRG 0x0005 /* Trigger on */
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| 137 | #define SQ_CTRG 0x0006 /* Trigger off */
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| 138 | #define SQ_TTRG 0x0007 /* Trigger toggle */
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| 139 | #define SQ_ITRG 0x0008 /* If trigger active */
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| 140 |
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| 141 | #define SQ_SREG 0x0009 /* Set register */
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| 142 | #define SQ_IREQ 0x000A /* If register = */
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| 143 | #define SQ_IRLT 0x000B /* If register < */
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| 144 | #define SQ_IRGT 0x000C /* If register > */
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| 145 |
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| 146 | #define SQ_ISTM 0x000D /* If stimulus active */
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| 147 | #define SQ_JUMP 0x000E /* Jump to sequence line */
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| 148 | #define SQ_STOP 0x000F /* Stop sequence */
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| 149 |
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| 150 | #define SQ_AREG 0x0010 /* Increment register */
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| 151 |
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| 152 | /* Sequence data word masks */
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| 153 |
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| 154 | #define SQ_MFLG 0xF000 /* DAT -- flag mask */
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| 155 | #define SQ_MTYP 0x0F00 /* DAT -- data type mask */
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| 156 | #define SQ_MVAL 0x00FF /* DAT -- data value mask */
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| 157 |
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| 158 | /* Sequence data types */
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| 159 |
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| 160 | #define SQ_REG 0x0000 /* register */
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| 161 | #define SQ_VAL 0x0100 /* value */
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| 162 | #define SQ_VLT 0x0200 /* voltage */
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| 163 | #define SQ_RND 0x0300 /* random */
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