source: buchla-68k/include/patch.h@ d1ecb94

Last change on this file since d1ecb94 was f537c48, checked in by Thomas Lopatic <thomas@…>, 7 years ago

Cleanup.
  • Property mode set to 100644
File size: 4.2 KB
Line 
1/*
2 =============================================================================
3 patch.h -- MIDAS-VII Patch facility definitions
4 Version 22 -- 1988-12-02 -- D.N. Lynx Crowe
5 =============================================================================
6*/
7
8#pragma once
9
10#include "stdint.h"
11
12#define MAXPATCH 256 /* patch table size */
13#define RAWDEFS 256 /* def table size */
14
15#define NSLINES 1000 /* sequence table size */
16#define NSEQW 7 /* number of words in a seqent */
17
18#define SEQTIME 10 /* milliseconds per tick */
19
20#define DATAROW 9 /* data entry row */
21
22#define NDEFSTMS 5120 /* number of stms/defs */
23#define NPTEQELS 256 /* number of trigger fifo entries */
24
25#define NPTEQLO (NPTEQELS >> 2) /* trigger fifo lo water */
26#define NPTEQHI (NPTEQELS - NPTEQLO)
27 /* trigger fifo hi water */
28
29#define NULL_DEF 0x1200 /* blank definer code */
30
31#define ADR_MASK 0x00FF /* patch / defent table index mask */
32#define TRG_MASK 0x1FFF /* trigger mask */
33#define PE_SPEC 0x00FF /* destination mask */
34#define PE_TBIT 0x8000 /* DEF triggered bit */
35
36/* Patch structure definitions */
37
38struct patch { /* patch table entry (16 bytes per entry) */
39
40 int16_t nextstm; /* index of next entry in stm chain */
41 int16_t prevstm; /* index of previous entry in stm chain */
42 uint16_t defnum; /* definer */
43 uint16_t stmnum; /* stimulus */
44 uint16_t paspec; /* destination type and flags */
45 uint16_t pasuba; /* sub-address */
46 uint16_t padat1; /* data word 1 */
47 uint16_t padat2; /* data word 2 */
48};
49
50struct defent { /* definition table entry -- 10 bytes per entry */
51
52 int16_t nextdef; /* index of next in def chain */
53 uint16_t stm; /* stimulus */
54 uint16_t adspec; /* destination type */
55 uint16_t adsuba; /* sub-address */
56 uint16_t addat1; /* data word 1 */
57};
58
59
60/* Sequence structure definitions */
61
62struct seqent { /* sequence table entry -- 14 bytes per entry */
63
64 uint16_t seqtime; /* time */
65 uint16_t seqact1; /* action 1 */
66 uint16_t seqdat1; /* action 1 data */
67 uint16_t seqact2; /* action 2 */
68 uint16_t seqdat2; /* action 2 data */
69 uint16_t seqact3; /* action 3 */
70 uint16_t seqdat3; /* action 3 data */
71};
72
73/* Patch destination types */
74
75#define PA_KEY 1
76#define PA_TRG 2
77#define PA_PLS 3
78#define PA_LED 4
79#define PA_SLIN 5
80#define PA_SCTL 6
81#define PA_TUNE 7
82#define PA_RSET 8
83#define PA_RADD 9
84#define PA_INST 10
85#define PA_OSC 11
86#define PA_WAVA 12
87#define PA_WAVB 13
88#define PA_CNFG 14
89#define PA_LEVL 15
90#define PA_INDX 16
91#define PA_FREQ 17
92#define PA_FILT 18
93#define PA_FILQ 19
94#define PA_LOCN 20
95#define PA_DYNM 21
96#define PA_AUX 22
97#define PA_RATE 23
98#define PA_INTN 24
99#define PA_DPTH 25
100#define PA_VOUT 26
101
102/* Patch sub-address types */
103
104#define PSA_SRC 0
105#define PSA_MLT 1
106#define PSA_TIM 2
107#define PSA_VAL 3
108#define PSA_FNC 4
109
110/* Patch oscillator data types */
111
112#define PSO_INT 0
113#define PSO_RAT 1
114#define PSO_FRQ 2
115#define PSO_PCH 3
116
117/* Sequence control flags */
118
119#define SQF_RUN 0x8000 /* RUN state */
120#define SQF_CLK 0x4000 /* CLK state */
121
122/* Sequence action word masks */
123
124#define SQ_MACT 0x00FF /* ACT -- action mask */
125#define SQ_MOBJ 0xFF00 /* ACT -- object mask */
126
127/* Sequence action types */
128
129#define SQ_NULL 0x0000 /* NULL action */
130
131#define SQ_CKEY 0x0001 /* Key closure */
132#define SQ_RKEY 0x0002 /* Key release */
133#define SQ_TKEY 0x0003 /* Key transient */
134#define SQ_IKEY 0x0004 /* If key active */
135
136#define SQ_STRG 0x0005 /* Trigger on */
137#define SQ_CTRG 0x0006 /* Trigger off */
138#define SQ_TTRG 0x0007 /* Trigger toggle */
139#define SQ_ITRG 0x0008 /* If trigger active */
140
141#define SQ_SREG 0x0009 /* Set register */
142#define SQ_IREQ 0x000A /* If register = */
143#define SQ_IRLT 0x000B /* If register < */
144#define SQ_IRGT 0x000C /* If register > */
145
146#define SQ_ISTM 0x000D /* If stimulus active */
147#define SQ_JUMP 0x000E /* Jump to sequence line */
148#define SQ_STOP 0x000F /* Stop sequence */
149
150#define SQ_AREG 0x0010 /* Increment register */
151
152/* Sequence data word masks */
153
154#define SQ_MFLG 0xF000 /* DAT -- flag mask */
155#define SQ_MTYP 0x0F00 /* DAT -- data type mask */
156#define SQ_MVAL 0x00FF /* DAT -- data value mask */
157
158/* Sequence data types */
159
160#define SQ_REG 0x0000 /* register */
161#define SQ_VAL 0x0100 /* value */
162#define SQ_VLT 0x0200 /* voltage */
163#define SQ_RND 0x0300 /* random */
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