source: buchla-68k/orig/DOC/VSDD.TXT@ ee49131

Last change on this file since ee49131 was 3ae31e9, checked in by Thomas Lopatic <thomas@…>, 8 years ago

Imported original source code.
  • Property mode set to 100755
File size: 1.2 KB
Line 
182716 VSDD Timing Calculations
2------------------------------
3
4 with HRS = 1 and PSA = 0
5
6Clock values
7------------
8
9VCK = 12800000 Hz Master clock
10PIXCLK = 12800000 Hz Pixel clock
11VPH = 6400000 Hz Internal clock
12GCLK = 800000 Hz General clock (1250 nanoseconds)
13
14Horizontal values Vertical values
15----------------- ---------------
16
17HC0 = 4 GCLKs VC0 = 9 lines sync
18HC1 = 6 GCLKs VC1 = 11 lines start
19HC2 = 38 GCLKs VC2 = 361 lines stop
20HC3 = 41 GCLKs VC3 = 363 lines sweep
21
22AHP = 32 GCLKs AVL = 350 lines active
23IHP = 9 GCLKs IVL = 13 lines inactive
24
25HSYNC = 5000 nanoseconds VSYNC = 461250 nanoseconds
26HSWEEP = 51250 nanoseconds VSWEEP = 18603750 nanoseconds
27AHZ = 40000 nanoseconds AVZ = 17937500 nanoseconds
28
29Miscellaneous values
30--------------------
31
32GPIX = 16 pixels / GCLK HPIX = 512 pixels displayed
33HRATE = 19512 Hz VRATE = 53 Hz
34
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