source: buchla-68k/orig/IOLIB/VHINIT.C@ 0580615

Last change on this file since 0580615 was 3ae31e9, checked in by Thomas Lopatic <thomas@…>, 7 years ago

Imported original source code.

  • Property mode set to 100755
File size: 2.8 KB
Line 
1/*
2 =============================================================================
3 vhinit.c -- initialize VSDD hardware
4 Version 17 -- 1988-03-20 -- D.N. Lynx Crowe
5 (c) Copyright 1987, 1988 -- D.N. Lynx Crowe
6
7 VHinit()
8
9 Setup VSDD registers, clear access table, clear object table,
10 load character generator, set color lookup table defaults.
11 Defines major video system variables, since the linker isn't
12 smart enough to let me put them in a separate file.
13 =============================================================================
14*/
15
16#define FASTCHIP 1 /* non-zero if it's the fast VSDD chip */
17
18#include "hwdefs.h"
19#include "vsdd.h"
20#include "memory.h"
21
22#define VREG(h,v) ((h<<10)|v)
23
24extern int cgtable[];
25extern int cg_rows;
26
27struct octent v_obtab[16]; /* object control table */
28
29struct octent *v_curob; /* current v_obtab pointer */
30
31int v_nobj; /* current object number */
32int v_obpri; /* current object priority */
33
34/*
35 */
36
37/* initialized variables */
38
39int vr_data[] = {
40
41 0x825B, /* R0 -- Mode word 0 */
42 0xC474, /* R1 -- Mode word 1 */
43 0x0006, /* R2 -- Register window base, Control flags */
44 0x0100, /* R3 -- Data window base, X limit (0x200000) */
45 0x0000, /* R4 -- Data length mask (128K) */
46 0x0000, /* R5 -- Data segment base (0x000000) */
47 0x0001, /* R6 -- Priority access count (1) */
48 0x0040, /* R7 -- Object Descriptor Table base (0x200080) */
49 0x0080, /* R8 -- Access Table base (0x200100) */
50 0x0010, /* R9 -- Color Lookup Table base (0x200020) */
51 0x00FF, /* R10 -- Character Generator bases (0x21E000) */
52 0x0000, /* R11 -- Access Table address counter */
53
54#if FASTCHIP
55 VREG( 3, 8), /* R12 -- HC0 (HSYNC width) VC0 (VSYNC width) */
56 VREG( 5, 10), /* R13 -- HC1 (AHZ start) VC1 (AVZ start) */
57 VREG(37, 360), /* R14 -- HC2 (AHZ stop) VC2 (AVZ stop) */
58 VREG(40, 362) /* R15 -- HC3 (HOR sweep) VC3 (VRT sweep) */
59#else
60 VREG( 3, 8), /* R12 -- HC0 (HSYNC width) VC0 (VSYNC width) */
61 VREG( 6, 10), /* R13 -- HC1 (AHZ start) VC1 (AVZ start) */
62 VREG(38, 360), /* R14 -- HC2 (AHZ stop) VC2 (AVZ stop) */
63 VREG(43, 361) /* R15 -- HC3 (HOR sweep) VC3 (VRT sweep) */
64#endif
65};
66
67/*
68 */
69
70/*
71 =============================================================================
72 VHinit() -- initialize the VSDD
73 =============================================================================
74*/
75
76VHinit()
77{
78
79 /* select VSDD RAM bank 0 so we can access the control tables */
80
81 vbank(0);
82
83 /* set the video register values */
84
85 memcpyw(v_regs, vr_data, 16);
86
87 /* clear the access table to turn off all objects */
88
89 memsetw(v_actab, 0xFFFF, 350);
90
91 /* clear the object table */
92
93 memsetw(v_odtab, 0, 64);
94
95 /* move the character generator table to VSDD RAM */
96
97 memsetw(v_cgtab, 0, 4096);
98 memcpyw(v_cgtab, cgtable, 256 * cg_rows);
99}
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