source: buchla-68k/orig/MT/MTINT2.S@ bbb6a97

Last change on this file since bbb6a97 was 3ae31e9, checked in by Thomas Lopatic <thomas@…>, 7 years ago

Imported original source code.
  • Property mode set to 100755
File size: 1.9 KB
Line 
1* ------------------------------------------------------------------------------
2* mtfpu.s -- Multi-Tasker null FPU second level interrupt handler
3* Version 3 -- 1988-04-13 -- D.N. Lynx Crowe
4* Initially, resvec3 points at nullfpu. MIDAS can change it with a BIOS trap.
5* ------------------------------------------------------------------------------
6*
7 .text
8*
9 .xdef __MTInt2 * FPU Second Level Interrupt Handler
10 .xdef nullfpu * FPU null Third Level Interrupt Handler
11*
12 .xref SM_Wait * Sempahore wait function
13*
14 .xref MT_ISEM2 * FPU interrupt semaphore
15 .xref resvec3 * FPU interrupt vector
16*
17FPUBASE .equ $180000 * FPU base address
18*
19* FPU address offsets and misc. values
20*
21FPU_CTL .equ $4000 * FPU control offset
22*
23FPU_IN .equ $4000 * FPU input address
24FPU_CLR .equ $6000 * FPU interrupt reset address
25*
26FPU_RST .equ $0015 * FPU reset value
27*
28 .page
29*
30* __MTInt2 -- FPU Second Level Interrupt Handler
31* -------- ----------------------------------
32__MTInt2: move.l #MT_ISEM2,-(a7) * Wait on interrupt semaphore
33 jsr SM_Wait * ...
34 tst.l (a7)+ *
35 movea.l resvec3,a0 * (*resvec3)()
36 jsr (a0) * ...
37 bra __MTInt2 * do it again
38*
39* ------------------------------------------------------------------------------
40*
41* nullfpu -- FPU null Third Level Interrupt Handler
42* ------- --------------------------------------
43nullfpu: movem.l d0-d0/a0-a0,-(a7) * Save registers
44 movea.l #FPUBASE,a0 * Setup FPU base address in a0
45 move.w FPU_IN(a0),d0 * Read FPU interrupt port
46 andi.l #$000000FF,d0 * Mask for voice & parameter
47 lsl.l #5,d0 * Shift for word offset
48 addi.l #FPU_CTL,d0 * Add FPU control offset
49 move.w #FPU_RST,0(a0,d0.L) * Reset the function
50 clr.w FPU_CLR(a0) * Clear the interrupt
51 movem.l (a7)+,d0-d0/a0-a0 * Restore registers
52 rts * Return to interrupted code
53*
54 .end
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