source: buchla-68k/ram/etiosc.c@ 3fcb810

Last change on this file since 3fcb810 was f537c48, checked in by Thomas Lopatic <thomas@…>, 7 years ago

Cleanup.
  • Property mode set to 100644
File size: 13.5 KB
RevLine 
[f40a309]1/*
2 =============================================================================
3 etiosc.c -- MIDAS instrument editor -- oscillator field handlers
4 Version 31 -- 1988-10-27 -- D.N. Lynx Crowe
5 =============================================================================
6*/
7
[b28a12e]8#include "ram.h"
[f40a309]9
10/* initialized variables */
11
12/* C C# D D# E F F# G G# A A# B */
[8cc57e6]13int8_t notes[] = {2, 2, 3, 3, 4, 5, 5, 6, 6, 0, 0, 1};
[f40a309]14
15/* A B C D E F G */
[7258c6a]16int16_t pitches[] = { 900, 1100, 0, 200, 400, 500, 700};
[f40a309]17
18#include "ratio.h" /* short ratio[]; */
19
20/* C C# D D# E F F# G G# A A# B */
[8cc57e6]21int8_t sharps[] = {7, 9, 7, 9, 7, 7, 9, 7, 9, 7, 9, 7};
[f40a309]22
[7258c6a]23int16_t shrpflt[] = { 0, -100, 100};
[f40a309]24
[7258c6a]25int8_t sfdsp[] = {' ', D_FLAT, D_SHARP};
[f40a309]26
[7258c6a]27static int8_t intstr[] = "+0000";
28static int8_t ratstr[] = "1/1";
29static int8_t frqstr[] = "00.0";
30static int8_t pchstr[] = "0C 00";
[f40a309]31
[7258c6a]32int16_t ndvals[10] = {0, 0, 1200, 1902, 2400, 2786, 3102, 3369, 3600, 3804};
[f40a309]33
34/*
35 =============================================================================
36 int2rat() -- convert interval to ratio
37 =============================================================================
38*/
39
[7258c6a]40void int2rat(int16_t rat)
[f40a309]41{
[7258c6a]42 register int16_t den, inum, num;
[f40a309]43
44 ebuf[0] = '1';
45 ebuf[1] = '/';
46 ebuf[2] = '1';
47 ebuf[3] = '\0';
48
49 for (num = 1; num < 10; num++) {
50
51 inum = 10 * num;
52
53 for (den = 1; den < 10; den++) {
54
55 if (rat EQ ratio[inum + den]) {
56
[8cc57e6]57 ebuf[0] = (int8_t)(num + '0');
58 ebuf[2] = (int8_t)(den + '0');
[f40a309]59 return;
60 }
61 }
62 }
63}
64
65/*
66 =============================================================================
67 cnvc2p() -- convert cents to pitch
68 =============================================================================
69*/
70
[7258c6a]71void cnvc2p(int8_t *buf, int16_t cv)
[f40a309]72{
[7258c6a]73 int16_t rem, tmp;
[f40a309]74
75 cv -= 160;
[8cc57e6]76 buf[0] = (int8_t)(cv / 1200);
[f537c48]77 rem = cv - (buf[0] * 1200);
[f40a309]78 tmp = rem / 100;
79 rem -= (tmp * 100);
80 buf[1] = notes[tmp];
81 buf[2] = sharps[tmp];
[8cc57e6]82 buf[3] = (int8_t)(rem / 10);
83 buf[4] = (int8_t)(rem - (buf[3] * 10));
[f40a309]84}
85
86/*
87 =============================================================================
88 cnvp2c() -- convert pitch to cents
89
90 input in edit buffer:
91
92 ebuf[0] = octave 0..9
93 ebuf[1] = note A..G (0..6)
94 ebuf[2] = type natural, flat, sharp (7..9)
95 ebuf[3] = ms byte of offset 0..9
96 ebuf[4] = ls byte of offset 0..9
97
98 output in cents
99 =============================================================================
100*/
101
[7258c6a]102int16_t cnvp2c(void)
[f40a309]103{
104 if (ebuf[0] EQ 9) /* high limit is C9 00 */
105 if (ebuf[1] GT 2)
106 return(FAILURE);
107 else if (ebuf[1] EQ 2)
108 if (ebuf[2] NE 7)
109 return(FAILURE);
110 else if (ebuf[3] OR ebuf[4])
111 return(FAILURE);
112
113 cents = (ebuf[0] * 1200) + pitches[ebuf[1]] + shrpflt[ebuf[2] - 7]
114 + (ebuf[3] * 10) + ebuf[4] + 160;
115
116 return(SUCCESS);
117}
118
119/*
120 =============================================================================
121 et_iosc() -- load the edit buffer
122 =============================================================================
123*/
124
[7258c6a]125int16_t et_iosc(int16_t nn)
[f40a309]126{
127 register struct instdef *ip;
[7258c6a]128 register int16_t val, ctl, fh, fl, v;
[f40a309]129
130 v = (nn >> 8) & 0x03;
131 ip = &vbufs[curvce];
132
133 switch (v) {
134
135 case 0:
136
137 val = ip->idhos1v;
138 ctl = ip->idhos1c;
139 break;
140
141 case 1:
142
143 val = ip->idhos2v;
144 ctl = ip->idhos2c;
145 break;
146
147 case 2:
148
149 val = ip->idhos3v;
150 ctl = ip->idhos3c;
151 break;
152
153 case 3:
154
155 val = ip->idhos4v;
156 ctl = ip->idhos4c;
157 break;
158 }
[fa38804]159
[f40a309]160 bform = ctl & OC_MOD;
161
162 switch (bform) {
163
164 case OC_INT: /* interval */
165
166 sprintf(ebuf, "%04d%c", ((val < 0 ? -val : val) >> 1),
167 (val < 0 ? '-' : '+'));
168
169 ebflag = TRUE;
170 return(SUCCESS);
171
172 case OC_RAT: /* ratio */
173
174 int2rat(val >> 1);
175 ebflag = TRUE;
176 return(SUCCESS);
177
178 case OC_FRQ: /* frequency */
179
180 fh = (val >> 1) / 10;
181 fl = (val >> 1) - (fh * 10);
182
183 sprintf(ebuf, "%02d.%d", fh, fl);
184 ebflag = TRUE;
185 return(SUCCESS);
186
187 case OC_PCH:
188
189 cnvc2p(ebuf, (val >> 1));
190 ebflag = TRUE;
191 return(SUCCESS);
192 }
[599d89b]193
194 return(FAILURE);
[f40a309]195}
196
197/*
198 =============================================================================
199 setoval() -- set oscillator mode and pitch/ratio variables
200 =============================================================================
201*/
202
[7258c6a]203void setoval(struct instdef *ip, int16_t v, int16_t val)
[f40a309]204{
205 switch (v) {
206
207 case 0:
208
209 ip->idhos1v = val << 1;
[8cc57e6]210 ip->idhos1c = (int8_t)((ip->idhos1c & ~OC_MOD) | bform);
[f40a309]211 break;
212
213 case 1:
214
215 ip->idhos2v = val << 1;
[8cc57e6]216 ip->idhos2c = (int8_t)((ip->idhos2c & ~OC_MOD) | bform);
[f40a309]217 break;
218
219 case 2:
220
221 ip->idhos3v = val << 1;
[8cc57e6]222 ip->idhos3c = (int8_t)((ip->idhos3c & ~OC_MOD) | bform);
[f40a309]223 break;
224
225 case 3:
226
227 ip->idhos4v = val << 1;
[8cc57e6]228 ip->idhos4c = (int8_t)((ip->idhos4c & ~OC_MOD) | bform);
[f40a309]229 break;
230 }
231
[8cc57e6]232 ip->idhfnc[v].idftmd = (int8_t)((ip->idhfnc[v].idftmd & ~I_NRATIO)
233 | ((bform & 2) ? I_NRATIO : 0));
[f40a309]234}
235
236/*
237 =============================================================================
238 ef_iosc() -- unload (parse) edit buffer
239 =============================================================================
240*/
241
[7258c6a]242int16_t ef_iosc(int16_t nn)
[f40a309]243{
244 register struct instdef *ip;
[7258c6a]245 register int16_t v, i, tmp;
[f40a309]246
247 v = (nn >> 8) & 3;
248 ip = &vbufs[curvce];
249 ebflag = FALSE;
250
251 switch (bform) {
252
253 case OC_INT: /* interval */
254
255 tmp = 0;
256
257 for (i = 0; i < 4; i++)
258 tmp = (tmp * 10) + (ebuf[i] - '0');
259
260 if (ebuf[4] EQ '-')
261 tmp = -tmp;
262
263 setoval(ip, v, tmp);
264 modinst();
265 return(SUCCESS);
266
267 case OC_RAT: /* ratio */
268
269 tmp = ndvals[ebuf[0] - '0'] - ndvals[ebuf[2] - '0'];
270
271 setoval(ip, v, tmp);
272 modinst();
273 return(SUCCESS);
[fa38804]274
[f40a309]275 case OC_FRQ: /* frequency */
276
277 tmp = 0;
278
279 for (i = 0; i < 2; i++)
280 tmp = (tmp * 10) + ebuf[i] - '0';
281
282 tmp = (tmp * 10) + ebuf[3] - '0';
283
284 if (tmp GT 159)
285 return(FAILURE);
286
287 setoval(ip, v, tmp);
288 modinst();
289 return(SUCCESS);
290
291 case OC_PCH: /* pitch */
292
293 if (cnvp2c() EQ FAILURE)
294 return(FAILURE);
295
296 setoval(ip, v, cents);
297 modinst();
298 return(SUCCESS);
299 }
[599d89b]300
301 return(FAILURE);
[f40a309]302}
303
304/*
305 =============================================================================
306 rd_iosc() -- (re)display the field
307 =============================================================================
308*/
309
[7258c6a]310int16_t rd_iosc(int16_t nn)
[f40a309]311{
312 register struct instdef *ip;
[7258c6a]313 register int16_t val, ctl, fh, fl, v;
314 int16_t n;
315 int8_t ocs;
[f40a309]316
317 v = (nn >> 8) & 0x03;
318 n = nn & 0xFF;
319 ip = &vbufs[curvce];
320
321 switch (v) {
322
323 case 0:
324
325 val = ip->idhos1v;
326 ctl = ip->idhos1c;
327 break;
328
329 case 1:
330
331 val = ip->idhos2v;
332 ctl = ip->idhos2c;
333 break;
334
335 case 2:
336
337 val = ip->idhos3v;
338 ctl = ip->idhos3c;
339 break;
340
341 case 3:
342
343 val = ip->idhos4v;
344 ctl = ip->idhos4c;
345 break;
346 }
[fa38804]347
[f40a309]348 bform = ctl & OC_MOD;
349 ocs = ((v EQ 3) ? ' ' : (ctl & OC_SYN ? 'S' : 's'));
350
351 switch (bform) {
352
353 case OC_INT: /* interval */
354
355 sprintf(dspbuf, "Int %c%04d %c",
356 (val < 0 ? '-' : '+'),
357 ((val < 0 ? -val : val) >> 1),
358 ocs);
359 break;
360
361 case OC_RAT: /* ratio */
362
363 int2rat(val >> 1);
364 sprintf(dspbuf, "Rat %c/%c %c", ebuf[0], ebuf[2], ocs);
365 break;
366
367 case OC_FRQ: /* frequency */
368
369 fh = (val >> 1) / 10;
370 fl = (val >> 1) - (fh * 10);
371
372 sprintf(dspbuf, "Frq %02d.%d %c", fh, fl, ocs);
373 break;
374
375 case OC_PCH:
376
377 strcpy(dspbuf, "Pch ");
378 cnvc2p(&dspbuf[4], (val >> 1));
[8cc57e6]379 dspbuf[4] = (int8_t)(dspbuf[4] + '0');
380 dspbuf[5] = (int8_t)(dspbuf[5] + 'A');
[f40a309]381 dspbuf[6] = sfdsp[dspbuf[6] - 7];
[8cc57e6]382 dspbuf[7] = (int8_t)(dspbuf[7] + '0');
383 dspbuf[8] = (int8_t)(dspbuf[8] + '0');
[f40a309]384 dspbuf[9] = ' ';
385 dspbuf[10] = ocs;
386 dspbuf[11] = '\0';
387 break;
388 }
389
390 if (v_regs[5] & 0x0180)
391 vbank(0);
392
393 vcputsv(instob, 64, idbox[n][4], idbox[n][5], 18 + v , 36, dspbuf, 14);
394
395 return(SUCCESS);
396}
397
398/*
399 =============================================================================
400 setoscb() -- change oscillator data entry buffer format
401 =============================================================================
402*/
403
[7258c6a]404void setoscb(int16_t n, int16_t v)
[f40a309]405{
406 register struct instdef *ip;
[7258c6a]407 register int16_t bfm, ctl, val;
408 register int8_t ocs;
[f40a309]409
410 ip = &vbufs[curvce];
411
412 switch (v) {
413
414 case 0:
415
416 ctl = ip->idhos1c;
417 val = ip->idhos1v;
418 break;
419
420 case 1:
421
422 ctl = ip->idhos2c;
423 val = ip->idhos2v;
424 break;
425
426 case 2:
427
428 ctl = ip->idhos3c;
429 val = ip->idhos3v;
430 break;
431
432 case 3:
433
434 ctl = ip->idhos4c;
435 val = ip->idhos4v;
436 break;
437 }
438
439 ocs = ((v EQ 3) ? ' ' : (ctl & OC_SYN ? 'S' : 's'));
440
441 bfm = ctl & OC_MOD;
[fa38804]442
[f40a309]443 switch (bform) {
444
445 case OC_INT: /* interval */
446
447 if ((bfm EQ OC_RAT) OR (bfm EQ OC_INT)) {
448
449 sprintf(ebuf, "%04d%c", ((val < 0 ? -val : val) >> 1),
450 (val < 0 ? '-' : '+'));
451
452 sprintf(dspbuf, "Int %c%04d %c",
453 (val < 0 ? '-' : '+'),
454 ((val < 0 ? -val : val) >> 1),
455 ocs);
456
457 } else {
458
459 strcpy(ebuf, "0000+");
460 sprintf(dspbuf, "Int %s %c", intstr, ocs);
461 }
462
463 break;
464
465 case OC_RAT: /* ratio */
466
467 if (bfm EQ OC_RAT) {
468
469 int2rat(val >> 1);
470
471 sprintf(dspbuf, "Rat %c/%c %c",
472 ebuf[0], ebuf[2], ocs);
473
474 } else {
475
476 strcpy(ebuf, ratstr);
477 sprintf(dspbuf, "Rat %s %c", ratstr, ocs);
478 }
479
480 break;
[fa38804]481
[f40a309]482 case OC_FRQ: /* frequency */
483
484 strcpy(ebuf, frqstr);
485 sprintf(dspbuf, "Frq %s %c", frqstr, ocs);
486 break;
487
488 case OC_PCH: /* pitch */
489
490 ebuf[0] = 0; /* 0 */
491 ebuf[1] = 2; /* C */
492 ebuf[2] = 7; /* */
493 ebuf[3] = 0; /* 0 */
494 ebuf[4] = 0; /* 0 */
495
496 sprintf(dspbuf, "Pch %s %c", pchstr, ocs);
497 break;
498 }
499
500 ebflag = TRUE;
501
502 if (v_regs[5] & 0x0180)
503 vbank(0);
504
505 vcputsv(instob, 64, ID_ENTRY, idbox[n][5],
506 stcrow, 36, dspbuf, 14);
507}
508
509/*
510 =============================================================================
511 setosyn() -- set oscillator sync mode
512 =============================================================================
513*/
514
[7258c6a]515void setosyn(int16_t n, int16_t v, int16_t t)
[f40a309]516{
517 register struct instdef *ip;
[7258c6a]518 register int8_t *sc;
[f40a309]519
520 ip = &vbufs[curvce];
521
522 if (stcrow EQ 21)
523 return;
524
525 sc = t ? "S" : "s";
526
527 switch (v) {
528
529 case 0:
530
[8cc57e6]531 ip->idhos1c = (int8_t)((ip->idhos1c & ~OC_SYN) | (t ? OC_SYN : 0));
[f40a309]532 break;
533
534 case 1:
535
[8cc57e6]536 ip->idhos2c = (int8_t)((ip->idhos2c & ~OC_SYN) | (t ? OC_SYN : 0));
[f40a309]537 break;
538
539 case 2:
540
[8cc57e6]541 ip->idhos3c = (int8_t)((ip->idhos3c & ~OC_SYN) | (t ? OC_SYN : 0));
[f40a309]542 break;
543
544 case 3:
545
546 return;
547 }
548
549 dosync(curvce);
550
551 if (v_regs[5] & 0x0180)
552 vbank(0);
553
554 vcputsv(instob, 64, idbox[n][4], idbox[n][5], stcrow, stccol, sc, 14);
555 modinst();
556}
557
558/*
559 =============================================================================
560 nd_iosc() -- handle new data entry
561 =============================================================================
562*/
563
[7258c6a]564int16_t nd_iosc(int16_t nn, int16_t k)
[f40a309]565{
[7258c6a]566 register int16_t v, n;
[f40a309]567
568 n = nn & 0xFF;
569 v = (nn >> 8) & 3;
570
571 if (stccol LT 39) { /* mode */
572
573 if (k EQ 8) { /* - */
574
575 if (--bform LT 0)
576 bform = 3;
577
578 setoscb(n, v);
579 return(SUCCESS);
580
581 } else if (k EQ 9) { /* + */
582
583 if (++bform GT 3)
584 bform = 0;
585
586 setoscb(n, v);
587 return(SUCCESS);
588
589 } else
590 return(FAILURE);
[fa38804]591
[f40a309]592 } else if (stccol EQ 46) { /* sync */
593
594 if (stcrow EQ 21)
595 return(FAILURE);
596
597 if (k EQ 8) { /* - */
598
599 setosyn(n, v, 0); /* off */
600 return(SUCCESS);
601
602 } else if (k EQ 9) { /* + */
603
604 setosyn(n, v, 1); /* on */
605 return(SUCCESS);
606
607 } else
608 return(FAILURE);
609
[fa38804]610
[f40a309]611 } else if ((stccol GE 40) AND (stccol LE 44)) { /* value */
612
613 switch (bform) {
614
615 case OC_INT: /* interval */
616
617 if (stccol EQ 40) { /* sign */
618
619 if (k EQ 8) { /* - */
620
621 k = '-';
622 ebuf[4] = '-';
623
624 } else if (k EQ 9) { /* + */
625
626 k = '+';
627 ebuf[4] = '+';
628
629 } else
630 return(FAILURE);
631
632 } else {
633
[8cc57e6]634 ebuf[stccol - 41] = (int8_t)(k + '0');
[f40a309]635 }
636
[8cc57e6]637 dspbuf[0] = (int8_t)((k > 9) ? k : (k + '0'));
[f40a309]638 dspbuf[1] = '\0';
639
640 if (v_regs[5] & 0x0180)
641 vbank(0);
642
643 vcputsv(instob, 64, ID_ENTRY, idbox[n][5],
644 stcrow, stccol, dspbuf, 14);
645
646 if (stccol EQ 44)
647 return(SUCCESS);
648
649 advicur();
650 return(SUCCESS);
[fa38804]651
[f40a309]652 case OC_RAT: /* ratio */
653
654 if (stccol EQ 40) {
655
656 if (k) {
657
[8cc57e6]658 ebuf[0] = dspbuf[0] = (int8_t)(k + '0');
[f40a309]659 dspbuf[1] = '\0';
660
661 if (v_regs[5] & 0x0180)
662 vbank(0);
663
664 vcputsv(instob, 64, ID_ENTRY, idbox[n][5],
665 stcrow, stccol, dspbuf, 14);
666
667 advicur();
668 advicur();
669
670 return(SUCCESS);
671
672 } else
673 return(FAILURE);
674
675 } else if (stccol EQ 42) {
676
677 if (k) {
678
[8cc57e6]679 ebuf[2] = dspbuf[0] = (int8_t)(k + '0');
[f40a309]680 dspbuf[1] = '\0';
681
682 if (v_regs[5] & 0x0180)
683 vbank(0);
684
685 vcputsv(instob, 64, ID_ENTRY, idbox[n][5],
686 stcrow, stccol, dspbuf, 14);
687
688 return(SUCCESS);
689
690 } else
691 return(FAILURE);
692 } else {
693
694 return(FAILURE);
695 }
[fa38804]696
[f40a309]697 case OC_FRQ: /* frequency */
698
699 if (stccol EQ 42)
700 return(FAILURE);
701
[8cc57e6]702 ebuf[stccol - 40] = (int8_t)(k + '0');
703 dspbuf[0] = (int8_t)(k + '0');
[f40a309]704 dspbuf[1] = '\0';
705
706 if (v_regs[5] & 0x0180)
707 vbank(0);
708
709 vcputsv(instob, 64, ID_ENTRY, idbox[n][5],
710 stcrow, stccol, dspbuf, 14);
711
712 if (stccol EQ 44)
713 return(SUCCESS);
714
715 advicur();
716
717 if (stccol EQ 42)
718 advicur();
719
720 return(SUCCESS);
[fa38804]721
[f40a309]722 case OC_PCH: /* pitch */
723
724 switch (stccol) {
725
726 case 40:
727
[8cc57e6]728 ebuf[0] = (int8_t)k;
729 dspbuf[0] = (int8_t)(k + '0');
[f40a309]730 break;
731
732 case 41:
733
734 if (k GT 6)
735 return(FAILURE);
736
[8cc57e6]737 ebuf[1] = (int8_t)k;
738 dspbuf[0] = (int8_t)(k + 'A');
[f40a309]739 break;
740
741 case 42:
742
743 if (k EQ 7) { /* blank */
744
[8cc57e6]745 ebuf[2] = (int8_t)k;
[f40a309]746 dspbuf[0] = sfdsp[0];
747 break;
748
749 } else if (k EQ 8) { /* flat */
750
[8cc57e6]751 ebuf[2] = (int8_t)k;
[f40a309]752 dspbuf[0] = sfdsp[1];
753 break;
754
755 } else if (k EQ 9) { /* sharp */
756
[8cc57e6]757 ebuf[2] = (int8_t)k;
[f40a309]758 dspbuf[0] = sfdsp[2];
759 break;
760
761 } else
762 return(FAILURE);
763 case 43:
764 case 44:
765
[8cc57e6]766 ebuf[stccol - 40] = (int8_t)k;
767 dspbuf[0] = (int8_t)(k + '0');
[f40a309]768 break;
769 }
770
771 dspbuf[1] = '\0';
772
773 if (v_regs[5] & 0x0180)
774 vbank(0);
775
776 vcputsv(instob, 64, ID_ENTRY, idbox[n][5],
777 stcrow, stccol, dspbuf, 14);
778
779 if (stccol EQ 44)
780 return(SUCCESS);
781
782 advicur();
783 return(SUCCESS);
784 }
785
[599d89b]786 return(FAILURE);
787
[f40a309]788 } else {
789
790 return(FAILURE);
791 }
792}
[6262b5c]793
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