[a06aa8b] | 1 | /*
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| 2 | * Copyright (C) 2017 The Contributors
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| 3 | *
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| 4 | * This program is free software: you can redistribute it and/or modify
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| 5 | * it under the terms of the GNU General Public License as published by
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| 6 | * the Free Software Foundation, either version 3 of the License, or (at
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| 7 | * your option) any later version.
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| 8 | *
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| 9 | * This program is distributed in the hope that it will be useful, but
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| 10 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 12 | * General Public License for more details.
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| 13 | *
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| 14 | * A copy of the GNU General Public License can be found in the file
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| 15 | * "gpl-v3.txt" in the top directory of this repository.
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| 16 | */
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| 17 |
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[ff8d800] | 18 | #include <all.h>
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| 19 |
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| 20 | #define ver(...) { \
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| 21 | if (cpu_verbose) { \
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| 22 | SDL_LogVerbose(SDL_LOG_CATEGORY_APPLICATION, __VA_ARGS__); \
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| 23 | } \
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| 24 | }
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| 25 |
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[a06aa8b] | 26 | bool cpu_verbose = false;
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| 27 |
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[ff8d800] | 28 | #define CYCLES 10
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| 29 |
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[ba36b71] | 30 | #define VEC_SIZE 0x400
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| 31 |
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[a06aa8b] | 32 | #define RAM_START 0x0
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| 33 | #define RAM_SIZE 0x100000
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| 34 |
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| 35 | #define ROM_START 0x100000
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| 36 | #define ROM_SIZE 0x10000
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| 37 |
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| 38 | typedef void (*hw_init_t)(void);
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| 39 | typedef void (*hw_quit_t)(void);
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| 40 | typedef void (*hw_exec_t)(void);
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| 41 | typedef uint32_t (*hw_read_t)(uint32_t off, int32_t sz);
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| 42 | typedef void (*hw_write_t)(uint32_t off, int32_t sz, uint32_t val);
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| 43 |
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| 44 | typedef struct {
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| 45 | uint32_t addr_beg;
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| 46 | uint32_t addr_end;
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| 47 | hw_init_t init;
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| 48 | hw_quit_t quit;
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| 49 | hw_exec_t exec;
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| 50 | hw_read_t read;
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| 51 | hw_write_t write;
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| 52 | } hw_t;
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[ff8d800] | 53 |
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| 54 | static bool reset = true;
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| 55 |
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[a06aa8b] | 56 | static uint8_t ram_data[RAM_SIZE];
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| 57 | static uint8_t rom_data[ROM_SIZE];
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| 58 |
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[ba36b71] | 59 | static uint32_t ram_ro_beg = 0x1234;
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| 60 | static uint32_t ram_ro_end = 0x1234;
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| 61 | static uint32_t ram_rw_beg = 0x1234;
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| 62 | static uint32_t ram_rw_end = 0x1234;
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[a06aa8b] | 63 |
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[ba36b71] | 64 | static uint32_t rom_ro_beg;
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| 65 | static uint32_t rom_ro_end;
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| 66 | static uint32_t rom_rw_beg;
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| 67 | static uint32_t rom_rw_end;
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[a06aa8b] | 68 |
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| 69 | static hw_t hw_map[] = {
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| 70 | { 0x180000, 0x200000, fpu_init, fpu_quit, fpu_exec, fpu_read, fpu_write },
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| 71 | { 0x200000, 0x280000, vid_init, vid_quit, vid_exec, vid_read, vid_write },
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| 72 | { 0x3a0001, 0x3a4001, tim_init, tim_quit, tim_exec, tim_read, tim_write },
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| 73 | { 0x3a4001, 0x3a8001, lcd_init, lcd_quit, lcd_exec, lcd_read, lcd_write },
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| 74 | { 0x3a8001, 0x3ac001, ser_init, ser_quit, ser_exec, ser_read, ser_write },
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| 75 | { 0x3ac001, 0x3b0001, mid_init, mid_quit, mid_exec, mid_read, mid_write },
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| 76 | { 0x3b0001, 0x3b4001, fdd_init, fdd_quit, fdd_exec, fdd_read, fdd_write },
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| 77 | { 0x3b4001, 0x3b8001, snd_init, snd_quit, snd_exec, snd_read, snd_write },
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| 78 | { 0x3b8001, 0x3bc001, led_init, led_quit, led_exec, led_read, led_write },
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| 79 | { 0x3bc001, 0x3c0001, kbd_init, kbd_quit, kbd_exec, kbd_read, kbd_write }
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| 80 | };
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| 81 |
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| 82 | static hw_t *hw_by_addr(uint32_t addr)
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| 83 | {
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| 84 | for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
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| 85 | if (addr >= hw_map[i].addr_beg && addr < hw_map[i].addr_end) {
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| 86 | return hw_map + i;
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| 87 | }
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| 88 | }
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| 89 |
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| 90 | return NULL;
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| 91 | }
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| 92 |
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| 93 | static void hw_init(void)
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| 94 | {
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[ba36b71] | 95 | inf("initializing hardware");
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[b909777] | 96 |
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[a06aa8b] | 97 | for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
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| 98 | hw_map[i].init();
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| 99 | }
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| 100 | }
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| 101 |
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| 102 | static void hw_exec(void)
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| 103 | {
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| 104 | for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
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| 105 | hw_map[i].exec();
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| 106 | }
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| 107 | }
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| 108 |
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| 109 | static uint32_t hw_off(hw_t *hw, uint32_t addr)
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| 110 | {
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| 111 | if ((hw->addr_beg & 0x1) == 0) {
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| 112 | return addr - hw->addr_beg;
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| 113 | }
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| 114 |
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| 115 | return (addr - hw->addr_beg) / 2;
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| 116 | }
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| 117 |
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[b909777] | 118 | static void bios_init(const char *bios)
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| 119 | {
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[ba36b71] | 120 | inf("loading BIOS file %s", bios);
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[b909777] | 121 |
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| 122 | SDL_RWops *ops = SDL_RWFromFile(bios, "rb");
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| 123 |
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| 124 | if (ops == NULL) {
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| 125 | fail("error while opening BIOS file %s", bios);
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| 126 | }
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| 127 |
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| 128 | if (SDL_ReadBE16(ops) != 0x601b) {
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| 129 | fail("invalid BIOS file %s", bios);
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| 130 | }
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| 131 |
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| 132 | uint32_t text_len = SDL_ReadBE32(ops);
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| 133 | uint32_t data_len = SDL_ReadBE32(ops);
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| 134 | uint32_t bss_len = SDL_ReadBE32(ops);
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| 135 |
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| 136 | SDL_ReadBE32(ops);
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| 137 | SDL_ReadBE32(ops);
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| 138 |
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| 139 | uint32_t text_loc = SDL_ReadBE32(ops);
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| 140 |
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| 141 | SDL_ReadBE16(ops);
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| 142 |
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| 143 | uint32_t data_loc = SDL_ReadBE32(ops);
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| 144 | uint32_t bss_loc = SDL_ReadBE32(ops);
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| 145 |
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[ba36b71] | 146 | inf("BIOS text 0x%x:0x%x data 0x%x:0x%x bss 0x%x:0x%x",
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| 147 | text_loc, text_len, data_loc, data_len, bss_loc, bss_len);
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[b909777] | 148 |
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| 149 | size_t load_len = (size_t)SDL_RWsize(ops) - 36;
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| 150 |
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[ba36b71] | 151 | if (text_loc != ROM_START || text_loc + text_len != data_loc ||
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| 152 | load_len != text_len + data_len || load_len > ROM_SIZE) {
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| 153 | fail("invalid BIOS file %s", bios);
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[b909777] | 154 | }
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| 155 |
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| 156 | size_t loaded = 0;
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| 157 |
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| 158 | while (loaded < load_len) {
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| 159 | size_t n_rd = SDL_RWread(ops, rom_data + loaded, 1, load_len - loaded);
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| 160 |
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| 161 | if (n_rd == 0) {
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| 162 | fail("error while reading BIOS file %s", bios);
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| 163 | }
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| 164 |
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| 165 | loaded += n_rd;
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| 166 | }
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| 167 |
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| 168 | SDL_RWclose(ops);
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[ba36b71] | 169 |
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| 170 | rom_ro_beg = text_loc;
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| 171 | rom_ro_end = text_loc + text_len + data_len;
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| 172 | rom_rw_beg = bss_loc;
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| 173 | rom_rw_end = bss_loc + bss_len;
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| 174 |
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| 175 | ver("rom_ro_beg 0x%08x rom_ro_end 0x%08x", rom_ro_beg, rom_ro_end);
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| 176 | ver("rom_rw_beg 0x%08x rom_rw_end 0x%08x", rom_rw_beg, rom_rw_end);
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[b909777] | 177 | }
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| 178 |
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[ff8d800] | 179 | uint32_t m68k_read_disassembler_8(uint32_t addr)
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| 180 | {
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[a06aa8b] | 181 | return m68k_read_memory_8(addr);
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[ff8d800] | 182 | }
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| 183 |
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| 184 | uint32_t m68k_read_disassembler_16(uint32_t addr)
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| 185 | {
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[a06aa8b] | 186 | return m68k_read_memory_16(addr);
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[ff8d800] | 187 | }
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| 188 |
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| 189 | uint32_t m68k_read_disassembler_32(uint32_t addr)
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| 190 | {
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[a06aa8b] | 191 | return m68k_read_memory_32(addr);
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[ff8d800] | 192 | }
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| 193 |
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| 194 | uint32_t m68k_read_memory_8(uint32_t addr)
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| 195 | {
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| 196 | ver("mem rd 0x%08x:8", addr);
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[a06aa8b] | 197 |
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[ba36b71] | 198 | if (addr >= ram_ro_beg && addr <= ram_ro_end - 1) {
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| 199 | return ram_data[addr - RAM_START];
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| 200 | }
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| 201 |
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| 202 | if (addr >= ram_rw_beg && addr <= ram_rw_end - 1) {
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[a06aa8b] | 203 | return ram_data[addr - RAM_START];
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| 204 | }
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| 205 |
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[ba36b71] | 206 | if (addr >= rom_ro_beg && addr <= rom_ro_end - 1) {
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[a06aa8b] | 207 | return rom_data[addr - ROM_START];
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| 208 | }
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| 209 |
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[ba36b71] | 210 | if (addr >= rom_rw_beg && addr <= rom_rw_end - 1) {
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| 211 | // ROM has its BSS section in RAM.
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| 212 | return ram_data[addr - RAM_START];
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| 213 | }
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| 214 |
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[a06aa8b] | 215 | hw_t *hw = hw_by_addr(addr);
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| 216 |
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| 217 | if (hw != NULL) {
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| 218 | return hw->read(hw_off(hw, addr), 1);
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| 219 | }
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| 220 |
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[ba36b71] | 221 | if (addr <= VEC_SIZE - 1) {
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| 222 | return ram_data[addr];
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| 223 | }
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| 224 |
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[a06aa8b] | 225 | fail("invalid read 0x%08x:8", addr);
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[ff8d800] | 226 | }
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| 227 |
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| 228 | uint32_t m68k_read_memory_16(uint32_t addr)
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| 229 | {
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| 230 | ver("mem rd 0x%08x:16", addr);
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| 231 |
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[ba36b71] | 232 | if (addr >= ram_ro_beg && addr <= ram_ro_end - 2) {
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| 233 | return
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| 234 | ((uint32_t)ram_data[addr - RAM_START + 0] << 8) |
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| 235 | ((uint32_t)ram_data[addr - RAM_START + 1] << 0);
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| 236 | }
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| 237 |
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| 238 | if (addr >= ram_rw_beg && addr <= ram_rw_end - 2) {
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[a06aa8b] | 239 | return
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| 240 | ((uint32_t)ram_data[addr - RAM_START + 0] << 8) |
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| 241 | ((uint32_t)ram_data[addr - RAM_START + 1] << 0);
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| 242 | }
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| 243 |
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[ba36b71] | 244 | if (addr >= rom_ro_beg && addr <= rom_ro_end - 2) {
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[a06aa8b] | 245 | return
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| 246 | ((uint32_t)rom_data[addr - ROM_START + 0] << 8) |
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| 247 | ((uint32_t)rom_data[addr - ROM_START + 1] << 0);
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[ff8d800] | 248 | }
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| 249 |
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[ba36b71] | 250 | if (addr >= rom_rw_beg && addr <= rom_rw_end - 2) {
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| 251 | // ROM has its BSS section in RAM.
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| 252 | return
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| 253 | ((uint32_t)ram_data[addr - RAM_START + 0] << 8) |
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| 254 | ((uint32_t)ram_data[addr - RAM_START + 1] << 0);
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| 255 | }
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| 256 |
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[a06aa8b] | 257 | hw_t *hw = hw_by_addr(addr);
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| 258 |
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| 259 | if (hw != NULL) {
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| 260 | return hw->read(hw_off(hw, addr), 2);
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[ff8d800] | 261 | }
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| 262 |
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[ba36b71] | 263 | if (addr <= VEC_SIZE - 2) {
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| 264 | return
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| 265 | ((uint32_t)ram_data[addr - 0] << 8) |
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| 266 | ((uint32_t)ram_data[addr - 1] << 0);
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| 267 | }
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| 268 |
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[a06aa8b] | 269 | fail("invalid read 0x%08x:16", addr);
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[ff8d800] | 270 | }
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| 271 |
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| 272 | uint32_t m68k_read_memory_32(uint32_t addr)
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| 273 | {
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| 274 | ver("mem rd 0x%08x:32", addr);
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| 275 |
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| 276 | if (reset) {
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| 277 | if (addr == 0) {
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[b909777] | 278 | addr += ROM_START;
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[ff8d800] | 279 | }
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| 280 |
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[b909777] | 281 | else if (addr == 4) {
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| 282 | addr += ROM_START;
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[ff8d800] | 283 | reset = false;
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| 284 | }
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[b909777] | 285 | else {
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| 286 | fail("invalid reset sequence");
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| 287 | }
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[ff8d800] | 288 | }
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| 289 |
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[ba36b71] | 290 | if (addr >= ram_ro_beg && addr <= ram_ro_end - 4) {
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[a06aa8b] | 291 | return
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| 292 | ((uint32_t)ram_data[addr - RAM_START + 0] << 24) |
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| 293 | ((uint32_t)ram_data[addr - RAM_START + 1] << 16) |
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| 294 | ((uint32_t)ram_data[addr - RAM_START + 2] << 8) |
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| 295 | ((uint32_t)ram_data[addr - RAM_START + 3] << 0);
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| 296 | }
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| 297 |
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[ba36b71] | 298 | if (addr >= ram_rw_beg && addr <= ram_rw_end - 4) {
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| 299 | return
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| 300 | ((uint32_t)ram_data[addr - RAM_START + 0] << 24) |
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| 301 | ((uint32_t)ram_data[addr - RAM_START + 1] << 16) |
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| 302 | ((uint32_t)ram_data[addr - RAM_START + 2] << 8) |
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| 303 | ((uint32_t)ram_data[addr - RAM_START + 3] << 0);
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| 304 | }
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| 305 |
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| 306 | if (addr >= rom_ro_beg && addr <= rom_ro_end - 4) {
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[a06aa8b] | 307 | return
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| 308 | ((uint32_t)rom_data[addr - ROM_START + 0] << 24) |
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| 309 | ((uint32_t)rom_data[addr - ROM_START + 1] << 16) |
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| 310 | ((uint32_t)rom_data[addr - ROM_START + 2] << 8) |
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| 311 | ((uint32_t)rom_data[addr - ROM_START + 3] << 0);
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| 312 | }
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| 313 |
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[ba36b71] | 314 | if (addr >= rom_rw_beg && addr <= rom_rw_end - 4) {
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| 315 | // ROM has its BSS section in RAM.
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| 316 | return
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| 317 | ((uint32_t)ram_data[addr - RAM_START + 0] << 24) |
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| 318 | ((uint32_t)ram_data[addr - RAM_START + 1] << 16) |
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| 319 | ((uint32_t)ram_data[addr - RAM_START + 2] << 8) |
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| 320 | ((uint32_t)ram_data[addr - RAM_START + 3] << 0);
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| 321 | }
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| 322 |
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[a06aa8b] | 323 | hw_t *hw = hw_by_addr(addr);
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| 324 |
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| 325 | if (hw != NULL) {
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| 326 | return hw->read(hw_off(hw, addr), 4);
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| 327 | }
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| 328 |
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[ba36b71] | 329 | if (addr <= VEC_SIZE - 4) {
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| 330 | return
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| 331 | ((uint32_t)ram_data[addr + 0] << 24) |
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| 332 | ((uint32_t)ram_data[addr + 1] << 16) |
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| 333 | ((uint32_t)ram_data[addr + 2] << 8) |
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| 334 | ((uint32_t)ram_data[addr + 3] << 0);
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| 335 | }
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| 336 |
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[a06aa8b] | 337 | fail("invalid read 0x%08x:32", addr);
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[ff8d800] | 338 | }
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| 339 |
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| 340 | void m68k_write_memory_8(uint32_t addr, uint32_t val)
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| 341 | {
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| 342 | ver("mem wr 0x%08x:8 0x%02x", addr, val);
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[a06aa8b] | 343 |
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[ba36b71] | 344 | if (addr >= ram_rw_beg && addr <= ram_rw_end - 1) {
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[a06aa8b] | 345 | ram_data[addr - RAM_START] = (uint8_t)val;
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| 346 | return;
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| 347 | }
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| 348 |
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[ba36b71] | 349 | if (addr >= rom_rw_beg && addr <= rom_rw_end - 1) {
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[a06aa8b] | 350 | // ROM has its BSS section in RAM.
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| 351 | ram_data[addr - RAM_START] = (uint8_t)val;
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| 352 | return;
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| 353 | }
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| 354 |
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| 355 | hw_t *hw = hw_by_addr(addr);
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| 356 |
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| 357 | if (hw != NULL) {
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| 358 | hw->write(hw_off(hw, addr), 1, val);
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| 359 | return;
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| 360 | }
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| 361 |
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[ba36b71] | 362 | if (addr <= VEC_SIZE - 1) {
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| 363 | ram_data[addr] = (uint8_t)val;
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| 364 | return;
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| 365 | }
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| 366 |
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[a06aa8b] | 367 | fail("invalid write 0x%08x:8 0x%02x", addr, val);
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[ff8d800] | 368 | }
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| 369 |
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| 370 | void m68k_write_memory_16(uint32_t addr, uint32_t val)
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| 371 | {
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| 372 | ver("mem wr 0x%08x:16 0x%04x", addr, val);
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[a06aa8b] | 373 |
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[ba36b71] | 374 | if (addr >= ram_rw_beg && addr <= ram_rw_end - 2) {
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[a06aa8b] | 375 | ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 8);
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| 376 | ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 0);
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| 377 | return;
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| 378 | }
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| 379 |
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[ba36b71] | 380 | if (addr >= rom_rw_beg && addr <= rom_rw_end - 2) {
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[a06aa8b] | 381 | // ROM has its BSS section in RAM.
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| 382 | ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 8);
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| 383 | ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 0);
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| 384 | return;
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| 385 | }
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| 386 |
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| 387 | hw_t *hw = hw_by_addr(addr);
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| 388 |
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| 389 | if (hw != NULL) {
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| 390 | hw->write(hw_off(hw, addr), 2, val);
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| 391 | return;
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| 392 | }
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| 393 |
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[ba36b71] | 394 | if (addr <= VEC_SIZE - 2) {
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| 395 | ram_data[addr + 0] = (uint8_t)(val >> 8);
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| 396 | ram_data[addr + 1] = (uint8_t)(val >> 0);
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| 397 | return;
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| 398 | }
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| 399 |
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[a06aa8b] | 400 | fail("invalid write 0x%08x:16 0x%04x", addr, val);
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[ff8d800] | 401 | }
|
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| 402 |
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| 403 | void m68k_write_memory_32(uint32_t addr, uint32_t val)
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| 404 | {
|
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| 405 | ver("mem wr 0x%08x:32 0x%08x", addr, val);
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[a06aa8b] | 406 |
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[ba36b71] | 407 | if (addr >= ram_rw_beg && addr <= ram_rw_end - 4) {
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[a06aa8b] | 408 | ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 24);
|
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| 409 | ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 16);
|
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| 410 | ram_data[addr - RAM_START + 2] = (uint8_t)(val >> 8);
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| 411 | ram_data[addr - RAM_START + 3] = (uint8_t)(val >> 0);
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| 412 | return;
|
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| 413 | }
|
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| 414 |
|
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[ba36b71] | 415 | if (addr >= rom_rw_beg && addr <= rom_rw_end - 4) {
|
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[a06aa8b] | 416 | // ROM has its BSS section in RAM.
|
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| 417 | ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 24);
|
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| 418 | ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 16);
|
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| 419 | ram_data[addr - RAM_START + 2] = (uint8_t)(val >> 8);
|
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| 420 | ram_data[addr - RAM_START + 3] = (uint8_t)(val >> 0);
|
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| 421 | return;
|
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| 422 | }
|
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| 423 |
|
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| 424 | hw_t *hw = hw_by_addr(addr);
|
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| 425 |
|
---|
| 426 | if (hw != NULL) {
|
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| 427 | hw->write(hw_off(hw, addr), 4, val);
|
---|
| 428 | return;
|
---|
| 429 | }
|
---|
| 430 |
|
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[ba36b71] | 431 | if (addr <= VEC_SIZE - 4) {
|
---|
| 432 | ram_data[addr + 0] = (uint8_t)(val >> 24);
|
---|
| 433 | ram_data[addr + 1] = (uint8_t)(val >> 16);
|
---|
| 434 | ram_data[addr + 2] = (uint8_t)(val >> 8);
|
---|
| 435 | ram_data[addr + 3] = (uint8_t)(val >> 0);
|
---|
| 436 | return;
|
---|
| 437 | }
|
---|
| 438 |
|
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[a06aa8b] | 439 | fail("invalid write 0x%08x:32 0x%08x", addr, val);
|
---|
[ff8d800] | 440 | }
|
---|
| 441 |
|
---|
[b909777] | 442 | void cpu_loop(const char *bios)
|
---|
[ff8d800] | 443 | {
|
---|
[a06aa8b] | 444 | hw_init();
|
---|
[b909777] | 445 | bios_init(bios);
|
---|
[ff8d800] | 446 |
|
---|
[ba36b71] | 447 | inf("entering CPU loop");
|
---|
[ff8d800] | 448 | m68k_init();
|
---|
| 449 | m68k_set_cpu_type(M68K_CPU_TYPE_68000);
|
---|
| 450 | m68k_pulse_reset();
|
---|
| 451 |
|
---|
[a06aa8b] | 452 | for (int32_t c = 0; c < 5; ++c) {
|
---|
[ff8d800] | 453 | m68k_execute(CYCLES);
|
---|
[a06aa8b] | 454 | hw_exec();
|
---|
[ff8d800] | 455 | }
|
---|
| 456 | }
|
---|