[a06aa8b] | 1 | /*
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| 2 | * Copyright (C) 2017 The Contributors
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| 3 | *
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| 4 | * This program is free software: you can redistribute it and/or modify
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| 5 | * it under the terms of the GNU General Public License as published by
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| 6 | * the Free Software Foundation, either version 3 of the License, or (at
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| 7 | * your option) any later version.
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| 8 | *
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| 9 | * This program is distributed in the hope that it will be useful, but
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| 10 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 12 | * General Public License for more details.
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| 13 | *
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| 14 | * A copy of the GNU General Public License can be found in the file
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[2147e53] | 15 | * "gpl.txt" in the top directory of this repository.
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[a06aa8b] | 16 | */
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| 17 |
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[ff8d800] | 18 | #include <all.h>
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| 19 |
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[4c71d39] | 20 | #define ver(...) _ver(cpu_verbose, 0, __VA_ARGS__)
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| 21 | #define ver2(...) _ver(cpu_verbose, 1, __VA_ARGS__)
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| 22 | #define ver3(...) _ver(cpu_verbose, 2, __VA_ARGS__)
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[ff8d800] | 23 |
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[4c71d39] | 24 | int32_t cpu_verbose = 0;
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[a06aa8b] | 25 |
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[ebc8f69] | 26 | #define CPU_FREQ 7000000
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| 27 | #define PER_SEC 100000
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[ff8d800] | 28 |
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[555b171] | 29 | #define APP_START 0x10000
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[ba36b71] | 30 |
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[a06aa8b] | 31 | #define RAM_START 0x0
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| 32 | #define RAM_SIZE 0x100000
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| 33 |
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| 34 | #define ROM_START 0x100000
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| 35 | #define ROM_SIZE 0x10000
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| 36 |
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| 37 | typedef void (*hw_init_t)(void);
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| 38 | typedef void (*hw_quit_t)(void);
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| 39 | typedef void (*hw_exec_t)(void);
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| 40 | typedef uint32_t (*hw_read_t)(uint32_t off, int32_t sz);
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| 41 | typedef void (*hw_write_t)(uint32_t off, int32_t sz, uint32_t val);
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| 42 |
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| 43 | typedef struct {
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| 44 | uint32_t addr_beg;
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| 45 | uint32_t addr_end;
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| 46 | hw_init_t init;
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| 47 | hw_quit_t quit;
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| 48 | hw_exec_t exec;
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| 49 | hw_read_t read;
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| 50 | hw_write_t write;
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| 51 | } hw_t;
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[ff8d800] | 52 |
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| 53 | static bool reset = true;
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| 54 |
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[a06aa8b] | 55 | static uint8_t ram_data[RAM_SIZE];
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| 56 | static uint8_t rom_data[ROM_SIZE];
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| 57 |
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[ba36b71] | 58 | static uint32_t ram_ro_beg = 0x1234;
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| 59 | static uint32_t ram_ro_end = 0x1234;
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| 60 | static uint32_t ram_rw_beg = 0x1234;
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| 61 | static uint32_t ram_rw_end = 0x1234;
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[a06aa8b] | 62 |
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[ba36b71] | 63 | static uint32_t rom_ro_beg;
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| 64 | static uint32_t rom_ro_end;
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| 65 | static uint32_t rom_rw_beg;
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| 66 | static uint32_t rom_rw_end;
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[a06aa8b] | 67 |
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| 68 | static hw_t hw_map[] = {
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| 69 | { 0x180000, 0x200000, fpu_init, fpu_quit, fpu_exec, fpu_read, fpu_write },
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| 70 | { 0x200000, 0x280000, vid_init, vid_quit, vid_exec, vid_read, vid_write },
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| 71 | { 0x3a0001, 0x3a4001, tim_init, tim_quit, tim_exec, tim_read, tim_write },
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| 72 | { 0x3a4001, 0x3a8001, lcd_init, lcd_quit, lcd_exec, lcd_read, lcd_write },
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| 73 | { 0x3a8001, 0x3ac001, ser_init, ser_quit, ser_exec, ser_read, ser_write },
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| 74 | { 0x3ac001, 0x3b0001, mid_init, mid_quit, mid_exec, mid_read, mid_write },
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| 75 | { 0x3b0001, 0x3b4001, fdd_init, fdd_quit, fdd_exec, fdd_read, fdd_write },
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| 76 | { 0x3b4001, 0x3b8001, snd_init, snd_quit, snd_exec, snd_read, snd_write },
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| 77 | { 0x3b8001, 0x3bc001, led_init, led_quit, led_exec, led_read, led_write },
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| 78 | { 0x3bc001, 0x3c0001, kbd_init, kbd_quit, kbd_exec, kbd_read, kbd_write }
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| 79 | };
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| 80 |
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| 81 | static hw_t *hw_by_addr(uint32_t addr)
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| 82 | {
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| 83 | for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
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| 84 | if (addr >= hw_map[i].addr_beg && addr < hw_map[i].addr_end) {
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| 85 | return hw_map + i;
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| 86 | }
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| 87 | }
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| 88 |
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| 89 | return NULL;
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| 90 | }
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| 91 |
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| 92 | static void hw_init(void)
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| 93 | {
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[bb4fd0c] | 94 | inf("starting hardware");
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[b909777] | 95 |
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[a06aa8b] | 96 | for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
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| 97 | hw_map[i].init();
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| 98 | }
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| 99 | }
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| 100 |
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[bb4fd0c] | 101 | static void hw_quit(void)
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| 102 | {
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| 103 | inf("halting hardware");
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| 104 |
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| 105 | for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
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| 106 | hw_map[i].quit();
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| 107 | }
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| 108 | }
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| 109 |
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[a06aa8b] | 110 | static void hw_exec(void)
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| 111 | {
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| 112 | for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
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| 113 | hw_map[i].exec();
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| 114 | }
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| 115 | }
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| 116 |
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| 117 | static uint32_t hw_off(hw_t *hw, uint32_t addr)
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| 118 | {
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| 119 | if ((hw->addr_beg & 0x1) == 0) {
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| 120 | return addr - hw->addr_beg;
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| 121 | }
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| 122 |
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| 123 | return (addr - hw->addr_beg) / 2;
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| 124 | }
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| 125 |
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[b909777] | 126 | static void bios_init(const char *bios)
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| 127 | {
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[ba36b71] | 128 | inf("loading BIOS file %s", bios);
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[b909777] | 129 |
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| 130 | SDL_RWops *ops = SDL_RWFromFile(bios, "rb");
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| 131 |
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| 132 | if (ops == NULL) {
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| 133 | fail("error while opening BIOS file %s", bios);
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| 134 | }
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| 135 |
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| 136 | if (SDL_ReadBE16(ops) != 0x601b) {
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| 137 | fail("invalid BIOS file %s", bios);
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| 138 | }
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| 139 |
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| 140 | uint32_t text_len = SDL_ReadBE32(ops);
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| 141 | uint32_t data_len = SDL_ReadBE32(ops);
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| 142 | uint32_t bss_len = SDL_ReadBE32(ops);
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| 143 |
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| 144 | SDL_ReadBE32(ops);
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| 145 | SDL_ReadBE32(ops);
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| 146 |
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| 147 | uint32_t text_loc = SDL_ReadBE32(ops);
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| 148 |
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| 149 | SDL_ReadBE16(ops);
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| 150 |
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| 151 | uint32_t data_loc = SDL_ReadBE32(ops);
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| 152 | uint32_t bss_loc = SDL_ReadBE32(ops);
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| 153 |
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[ba36b71] | 154 | inf("BIOS text 0x%x:0x%x data 0x%x:0x%x bss 0x%x:0x%x",
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| 155 | text_loc, text_len, data_loc, data_len, bss_loc, bss_len);
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[b909777] | 156 |
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| 157 | size_t load_len = (size_t)SDL_RWsize(ops) - 36;
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| 158 |
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[ba36b71] | 159 | if (text_loc != ROM_START || text_loc + text_len != data_loc ||
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| 160 | load_len != text_len + data_len || load_len > ROM_SIZE) {
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| 161 | fail("invalid BIOS file %s", bios);
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[b909777] | 162 | }
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| 163 |
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| 164 | size_t loaded = 0;
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| 165 |
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| 166 | while (loaded < load_len) {
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| 167 | size_t n_rd = SDL_RWread(ops, rom_data + loaded, 1, load_len - loaded);
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| 168 |
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| 169 | if (n_rd == 0) {
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| 170 | fail("error while reading BIOS file %s", bios);
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| 171 | }
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| 172 |
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| 173 | loaded += n_rd;
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| 174 | }
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| 175 |
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| 176 | SDL_RWclose(ops);
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[ba36b71] | 177 |
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| 178 | rom_ro_beg = text_loc;
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| 179 | rom_ro_end = text_loc + text_len + data_len;
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| 180 | rom_rw_beg = bss_loc;
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| 181 | rom_rw_end = bss_loc + bss_len;
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| 182 |
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| 183 | ver("rom_ro_beg 0x%08x rom_ro_end 0x%08x", rom_ro_beg, rom_ro_end);
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| 184 | ver("rom_rw_beg 0x%08x rom_rw_end 0x%08x", rom_rw_beg, rom_rw_end);
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[b909777] | 185 | }
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| 186 |
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[ff8d800] | 187 | uint32_t m68k_read_disassembler_8(uint32_t addr)
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| 188 | {
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[a06aa8b] | 189 | return m68k_read_memory_8(addr);
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[ff8d800] | 190 | }
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| 191 |
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| 192 | uint32_t m68k_read_disassembler_16(uint32_t addr)
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| 193 | {
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[a06aa8b] | 194 | return m68k_read_memory_16(addr);
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[ff8d800] | 195 | }
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| 196 |
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| 197 | uint32_t m68k_read_disassembler_32(uint32_t addr)
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| 198 | {
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[a06aa8b] | 199 | return m68k_read_memory_32(addr);
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[ff8d800] | 200 | }
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| 201 |
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| 202 | uint32_t m68k_read_memory_8(uint32_t addr)
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| 203 | {
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[4c71d39] | 204 | ver3("mem rd 0x%08x:8", addr);
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[a06aa8b] | 205 |
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[ba36b71] | 206 | if (addr >= ram_ro_beg && addr <= ram_ro_end - 1) {
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| 207 | return ram_data[addr - RAM_START];
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| 208 | }
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| 209 |
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| 210 | if (addr >= ram_rw_beg && addr <= ram_rw_end - 1) {
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[a06aa8b] | 211 | return ram_data[addr - RAM_START];
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| 212 | }
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| 213 |
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[ba36b71] | 214 | if (addr >= rom_ro_beg && addr <= rom_ro_end - 1) {
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[a06aa8b] | 215 | return rom_data[addr - ROM_START];
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| 216 | }
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| 217 |
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[ba36b71] | 218 | if (addr >= rom_rw_beg && addr <= rom_rw_end - 1) {
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| 219 | // ROM has its BSS section in RAM.
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| 220 | return ram_data[addr - RAM_START];
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| 221 | }
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| 222 |
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[a06aa8b] | 223 | hw_t *hw = hw_by_addr(addr);
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| 224 |
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| 225 | if (hw != NULL) {
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| 226 | return hw->read(hw_off(hw, addr), 1);
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| 227 | }
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| 228 |
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[555b171] | 229 | if (addr <= APP_START - 1) {
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[ba36b71] | 230 | return ram_data[addr];
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| 231 | }
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| 232 |
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[a06aa8b] | 233 | fail("invalid read 0x%08x:8", addr);
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[ff8d800] | 234 | }
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| 235 |
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| 236 | uint32_t m68k_read_memory_16(uint32_t addr)
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| 237 | {
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[4c71d39] | 238 | ver3("mem rd 0x%08x:16", addr);
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[ff8d800] | 239 |
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[ba36b71] | 240 | if (addr >= ram_ro_beg && addr <= ram_ro_end - 2) {
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| 241 | return
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| 242 | ((uint32_t)ram_data[addr - RAM_START + 0] << 8) |
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| 243 | ((uint32_t)ram_data[addr - RAM_START + 1] << 0);
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| 244 | }
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| 245 |
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| 246 | if (addr >= ram_rw_beg && addr <= ram_rw_end - 2) {
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[a06aa8b] | 247 | return
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| 248 | ((uint32_t)ram_data[addr - RAM_START + 0] << 8) |
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| 249 | ((uint32_t)ram_data[addr - RAM_START + 1] << 0);
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| 250 | }
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| 251 |
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[ba36b71] | 252 | if (addr >= rom_ro_beg && addr <= rom_ro_end - 2) {
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[a06aa8b] | 253 | return
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| 254 | ((uint32_t)rom_data[addr - ROM_START + 0] << 8) |
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| 255 | ((uint32_t)rom_data[addr - ROM_START + 1] << 0);
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[ff8d800] | 256 | }
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| 257 |
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[ba36b71] | 258 | if (addr >= rom_rw_beg && addr <= rom_rw_end - 2) {
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| 259 | // ROM has its BSS section in RAM.
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| 260 | return
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| 261 | ((uint32_t)ram_data[addr - RAM_START + 0] << 8) |
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| 262 | ((uint32_t)ram_data[addr - RAM_START + 1] << 0);
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| 263 | }
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| 264 |
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[a06aa8b] | 265 | hw_t *hw = hw_by_addr(addr);
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| 266 |
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| 267 | if (hw != NULL) {
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| 268 | return hw->read(hw_off(hw, addr), 2);
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[ff8d800] | 269 | }
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| 270 |
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[555b171] | 271 | if (addr <= APP_START - 2) {
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[ba36b71] | 272 | return
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[9674f1a] | 273 | ((uint32_t)ram_data[addr + 0] << 8) |
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| 274 | ((uint32_t)ram_data[addr + 1] << 0);
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[ba36b71] | 275 | }
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| 276 |
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[a06aa8b] | 277 | fail("invalid read 0x%08x:16", addr);
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[ff8d800] | 278 | }
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| 279 |
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| 280 | uint32_t m68k_read_memory_32(uint32_t addr)
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| 281 | {
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[4c71d39] | 282 | ver3("mem rd 0x%08x:32", addr);
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[ff8d800] | 283 |
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| 284 | if (reset) {
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| 285 | if (addr == 0) {
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[b909777] | 286 | addr += ROM_START;
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[ff8d800] | 287 | }
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[b909777] | 288 | else if (addr == 4) {
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| 289 | addr += ROM_START;
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[ff8d800] | 290 | reset = false;
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| 291 | }
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[b909777] | 292 | else {
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| 293 | fail("invalid reset sequence");
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| 294 | }
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[ff8d800] | 295 | }
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| 296 |
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[ba36b71] | 297 | if (addr >= ram_ro_beg && addr <= ram_ro_end - 4) {
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[a06aa8b] | 298 | return
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| 299 | ((uint32_t)ram_data[addr - RAM_START + 0] << 24) |
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| 300 | ((uint32_t)ram_data[addr - RAM_START + 1] << 16) |
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| 301 | ((uint32_t)ram_data[addr - RAM_START + 2] << 8) |
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| 302 | ((uint32_t)ram_data[addr - RAM_START + 3] << 0);
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| 303 | }
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| 304 |
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[ba36b71] | 305 | if (addr >= ram_rw_beg && addr <= ram_rw_end - 4) {
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| 306 | return
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| 307 | ((uint32_t)ram_data[addr - RAM_START + 0] << 24) |
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| 308 | ((uint32_t)ram_data[addr - RAM_START + 1] << 16) |
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| 309 | ((uint32_t)ram_data[addr - RAM_START + 2] << 8) |
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| 310 | ((uint32_t)ram_data[addr - RAM_START + 3] << 0);
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| 311 | }
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| 312 |
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| 313 | if (addr >= rom_ro_beg && addr <= rom_ro_end - 4) {
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[a06aa8b] | 314 | return
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| 315 | ((uint32_t)rom_data[addr - ROM_START + 0] << 24) |
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| 316 | ((uint32_t)rom_data[addr - ROM_START + 1] << 16) |
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| 317 | ((uint32_t)rom_data[addr - ROM_START + 2] << 8) |
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| 318 | ((uint32_t)rom_data[addr - ROM_START + 3] << 0);
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| 319 | }
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| 320 |
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[ba36b71] | 321 | if (addr >= rom_rw_beg && addr <= rom_rw_end - 4) {
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| 322 | // ROM has its BSS section in RAM.
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| 323 | return
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| 324 | ((uint32_t)ram_data[addr - RAM_START + 0] << 24) |
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| 325 | ((uint32_t)ram_data[addr - RAM_START + 1] << 16) |
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| 326 | ((uint32_t)ram_data[addr - RAM_START + 2] << 8) |
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| 327 | ((uint32_t)ram_data[addr - RAM_START + 3] << 0);
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| 328 | }
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| 329 |
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[a06aa8b] | 330 | hw_t *hw = hw_by_addr(addr);
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| 331 |
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| 332 | if (hw != NULL) {
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| 333 | return hw->read(hw_off(hw, addr), 4);
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| 334 | }
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| 335 |
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[555b171] | 336 | if (addr <= APP_START - 4) {
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[ba36b71] | 337 | return
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| 338 | ((uint32_t)ram_data[addr + 0] << 24) |
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| 339 | ((uint32_t)ram_data[addr + 1] << 16) |
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| 340 | ((uint32_t)ram_data[addr + 2] << 8) |
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| 341 | ((uint32_t)ram_data[addr + 3] << 0);
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| 342 | }
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| 343 |
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[a06aa8b] | 344 | fail("invalid read 0x%08x:32", addr);
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[ff8d800] | 345 | }
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| 346 |
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| 347 | void m68k_write_memory_8(uint32_t addr, uint32_t val)
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| 348 | {
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[4c71d39] | 349 | ver3("mem wr 0x%08x:8 0x%02x", addr, val);
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[a06aa8b] | 350 |
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[ba36b71] | 351 | if (addr >= ram_rw_beg && addr <= ram_rw_end - 1) {
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[a06aa8b] | 352 | ram_data[addr - RAM_START] = (uint8_t)val;
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| 353 | return;
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| 354 | }
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| 355 |
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[ba36b71] | 356 | if (addr >= rom_rw_beg && addr <= rom_rw_end - 1) {
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[a06aa8b] | 357 | // ROM has its BSS section in RAM.
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| 358 | ram_data[addr - RAM_START] = (uint8_t)val;
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| 359 | return;
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| 360 | }
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| 361 |
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| 362 | hw_t *hw = hw_by_addr(addr);
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| 363 |
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| 364 | if (hw != NULL) {
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| 365 | hw->write(hw_off(hw, addr), 1, val);
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| 366 | return;
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| 367 | }
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| 368 |
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[555b171] | 369 | if (addr <= APP_START - 1) {
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[ba36b71] | 370 | ram_data[addr] = (uint8_t)val;
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| 371 | return;
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| 372 | }
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| 373 |
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[a06aa8b] | 374 | fail("invalid write 0x%08x:8 0x%02x", addr, val);
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[ff8d800] | 375 | }
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| 376 |
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| 377 | void m68k_write_memory_16(uint32_t addr, uint32_t val)
|
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| 378 | {
|
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[4c71d39] | 379 | ver3("mem wr 0x%08x:16 0x%04x", addr, val);
|
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[a06aa8b] | 380 |
|
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[ba36b71] | 381 | if (addr >= ram_rw_beg && addr <= ram_rw_end - 2) {
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[a06aa8b] | 382 | ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 8);
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| 383 | ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 0);
|
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| 384 | return;
|
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| 385 | }
|
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| 386 |
|
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[ba36b71] | 387 | if (addr >= rom_rw_beg && addr <= rom_rw_end - 2) {
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[a06aa8b] | 388 | // ROM has its BSS section in RAM.
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| 389 | ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 8);
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| 390 | ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 0);
|
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| 391 | return;
|
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| 392 | }
|
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| 393 |
|
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| 394 | hw_t *hw = hw_by_addr(addr);
|
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| 395 |
|
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| 396 | if (hw != NULL) {
|
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| 397 | hw->write(hw_off(hw, addr), 2, val);
|
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| 398 | return;
|
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| 399 | }
|
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| 400 |
|
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[555b171] | 401 | if (addr <= APP_START - 2) {
|
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[ba36b71] | 402 | ram_data[addr + 0] = (uint8_t)(val >> 8);
|
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| 403 | ram_data[addr + 1] = (uint8_t)(val >> 0);
|
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| 404 | return;
|
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| 405 | }
|
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| 406 |
|
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[a06aa8b] | 407 | fail("invalid write 0x%08x:16 0x%04x", addr, val);
|
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[ff8d800] | 408 | }
|
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| 409 |
|
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| 410 | void m68k_write_memory_32(uint32_t addr, uint32_t val)
|
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| 411 | {
|
---|
[4c71d39] | 412 | ver3("mem wr 0x%08x:32 0x%08x", addr, val);
|
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[a06aa8b] | 413 |
|
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[ba36b71] | 414 | if (addr >= ram_rw_beg && addr <= ram_rw_end - 4) {
|
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[a06aa8b] | 415 | ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 24);
|
---|
| 416 | ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 16);
|
---|
| 417 | ram_data[addr - RAM_START + 2] = (uint8_t)(val >> 8);
|
---|
| 418 | ram_data[addr - RAM_START + 3] = (uint8_t)(val >> 0);
|
---|
| 419 | return;
|
---|
| 420 | }
|
---|
| 421 |
|
---|
[ba36b71] | 422 | if (addr >= rom_rw_beg && addr <= rom_rw_end - 4) {
|
---|
[a06aa8b] | 423 | // ROM has its BSS section in RAM.
|
---|
| 424 | ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 24);
|
---|
| 425 | ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 16);
|
---|
| 426 | ram_data[addr - RAM_START + 2] = (uint8_t)(val >> 8);
|
---|
| 427 | ram_data[addr - RAM_START + 3] = (uint8_t)(val >> 0);
|
---|
| 428 | return;
|
---|
| 429 | }
|
---|
| 430 |
|
---|
| 431 | hw_t *hw = hw_by_addr(addr);
|
---|
| 432 |
|
---|
| 433 | if (hw != NULL) {
|
---|
| 434 | hw->write(hw_off(hw, addr), 4, val);
|
---|
| 435 | return;
|
---|
| 436 | }
|
---|
| 437 |
|
---|
[555b171] | 438 | if (addr <= APP_START - 4) {
|
---|
[ba36b71] | 439 | ram_data[addr + 0] = (uint8_t)(val >> 24);
|
---|
| 440 | ram_data[addr + 1] = (uint8_t)(val >> 16);
|
---|
| 441 | ram_data[addr + 2] = (uint8_t)(val >> 8);
|
---|
| 442 | ram_data[addr + 3] = (uint8_t)(val >> 0);
|
---|
| 443 | return;
|
---|
| 444 | }
|
---|
| 445 |
|
---|
[a06aa8b] | 446 | fail("invalid write 0x%08x:32 0x%08x", addr, val);
|
---|
[ff8d800] | 447 | }
|
---|
| 448 |
|
---|
[9674f1a] | 449 | static void inst_cb(void)
|
---|
| 450 | {
|
---|
| 451 | uint32_t pc = m68k_get_reg(NULL, M68K_REG_PC);
|
---|
| 452 | uint32_t op = m68k_read_memory_16(pc);
|
---|
| 453 |
|
---|
| 454 | if (op == 0x4e4d) {
|
---|
| 455 | uint32_t sp = m68k_get_reg(NULL, M68K_REG_SP);
|
---|
| 456 | uint32_t fun = m68k_read_memory_16(sp);
|
---|
| 457 |
|
---|
| 458 | switch (fun) {
|
---|
| 459 | case 1:
|
---|
| 460 | ver2("BIOS B_RDAV %u", m68k_read_memory_16(sp + 2));
|
---|
| 461 | break;
|
---|
| 462 |
|
---|
| 463 | case 2:
|
---|
| 464 | ver2("BIOS B_GETC %u", m68k_read_memory_16(sp + 2));
|
---|
| 465 | break;
|
---|
| 466 |
|
---|
| 467 | case 3:
|
---|
| 468 | ver2("BIOS B_PUTC %u %u",
|
---|
| 469 | m68k_read_memory_16(sp + 2),
|
---|
| 470 | m68k_read_memory_16(sp + 4));
|
---|
| 471 | break;
|
---|
| 472 |
|
---|
| 473 | case 4:
|
---|
| 474 | ver2("BIOS B_RDWR %u 0x%08x %u %u %u",
|
---|
| 475 | m68k_read_memory_16(sp + 2),
|
---|
| 476 | m68k_read_memory_32(sp + 4),
|
---|
| 477 | m68k_read_memory_16(sp + 8),
|
---|
| 478 | m68k_read_memory_16(sp + 10),
|
---|
| 479 | m68k_read_memory_16(sp + 12));
|
---|
| 480 | break;
|
---|
| 481 |
|
---|
| 482 | case 5:
|
---|
| 483 | ver2("BIOS B_SETV %u 0x%08x",
|
---|
| 484 | m68k_read_memory_16(sp + 2),
|
---|
| 485 | m68k_read_memory_32(sp + 4));
|
---|
| 486 | break;
|
---|
| 487 |
|
---|
| 488 | case 7:
|
---|
| 489 | ver2("BIOS B_GBPB %u", m68k_read_memory_16(sp + 2));
|
---|
| 490 | break;
|
---|
| 491 |
|
---|
| 492 | case 8:
|
---|
| 493 | ver2("BIOS B_THRE %u", m68k_read_memory_16(sp + 2));
|
---|
| 494 | break;
|
---|
| 495 |
|
---|
| 496 | case 9:
|
---|
| 497 | ver2("BIOS B_MCHG %u", m68k_read_memory_16(sp + 2));
|
---|
| 498 | break;
|
---|
| 499 |
|
---|
| 500 | case 10:
|
---|
| 501 | ver2("BIOS B_DMAP");
|
---|
| 502 | break;
|
---|
| 503 |
|
---|
| 504 | default:
|
---|
| 505 | fail("invalid function: BIOS %d", fun);
|
---|
| 506 | }
|
---|
| 507 | }
|
---|
| 508 | else if (op == 0x4e4e) {
|
---|
| 509 | uint32_t sp = m68k_get_reg(NULL, M68K_REG_SP);
|
---|
| 510 | uint32_t fun = m68k_read_memory_16(sp);
|
---|
| 511 |
|
---|
| 512 | switch (fun) {
|
---|
| 513 | case 0:
|
---|
| 514 | ver2("XBIOS X_PIOREC %u", m68k_read_memory_16(sp + 2));
|
---|
| 515 | break;
|
---|
| 516 |
|
---|
| 517 | case 1:
|
---|
| 518 | ver2("XBIOS X_SETPRT %u 0x%02x 0x%02x 0x%02x 0x%02x",
|
---|
| 519 | m68k_read_memory_16(sp + 2),
|
---|
| 520 | m68k_read_memory_16(sp + 4),
|
---|
| 521 | m68k_read_memory_16(sp + 6),
|
---|
| 522 | m68k_read_memory_16(sp + 8),
|
---|
| 523 | m68k_read_memory_16(sp + 10));
|
---|
| 524 | break;
|
---|
| 525 |
|
---|
| 526 | case 2:
|
---|
| 527 | ver2("XBIOS X_FLOPRD 0x%08x 0x%08x %u %u %u %u %u",
|
---|
| 528 | m68k_read_memory_32(sp + 2),
|
---|
| 529 | m68k_read_memory_32(sp + 6),
|
---|
| 530 | m68k_read_memory_16(sp + 10),
|
---|
| 531 | m68k_read_memory_16(sp + 12),
|
---|
| 532 | m68k_read_memory_16(sp + 14),
|
---|
| 533 | m68k_read_memory_16(sp + 16),
|
---|
| 534 | m68k_read_memory_16(sp + 18));
|
---|
| 535 | break;
|
---|
| 536 |
|
---|
| 537 | case 3:
|
---|
| 538 | ver2("XBIOS X_FLOPWR 0x%08x 0x%08x %u %u %u %u %u",
|
---|
| 539 | m68k_read_memory_32(sp + 2),
|
---|
| 540 | m68k_read_memory_32(sp + 6),
|
---|
| 541 | m68k_read_memory_16(sp + 10),
|
---|
| 542 | m68k_read_memory_16(sp + 12),
|
---|
| 543 | m68k_read_memory_16(sp + 14),
|
---|
| 544 | m68k_read_memory_16(sp + 16),
|
---|
| 545 | m68k_read_memory_16(sp + 18));
|
---|
| 546 | break;
|
---|
| 547 |
|
---|
| 548 | case 4:
|
---|
| 549 | ver2("XBIOS X_FORMAT 0x%08x 0x%08x %u %u %u %u %u 0x%08x %u",
|
---|
| 550 | m68k_read_memory_32(sp + 2),
|
---|
| 551 | m68k_read_memory_32(sp + 6),
|
---|
| 552 | m68k_read_memory_16(sp + 10),
|
---|
| 553 | m68k_read_memory_16(sp + 12),
|
---|
| 554 | m68k_read_memory_16(sp + 14),
|
---|
| 555 | m68k_read_memory_16(sp + 16),
|
---|
| 556 | m68k_read_memory_16(sp + 18),
|
---|
| 557 | m68k_read_memory_32(sp + 20),
|
---|
| 558 | m68k_read_memory_16(sp + 24));
|
---|
| 559 | break;
|
---|
| 560 |
|
---|
| 561 | case 5:
|
---|
| 562 | ver2("XBIOS X_VERIFY 0x%08x 0x%08x %u %u %u %u %u",
|
---|
| 563 | m68k_read_memory_32(sp + 2),
|
---|
| 564 | m68k_read_memory_32(sp + 6),
|
---|
| 565 | m68k_read_memory_16(sp + 10),
|
---|
| 566 | m68k_read_memory_16(sp + 12),
|
---|
| 567 | m68k_read_memory_16(sp + 14),
|
---|
| 568 | m68k_read_memory_16(sp + 16),
|
---|
| 569 | m68k_read_memory_16(sp + 18));
|
---|
| 570 | break;
|
---|
| 571 |
|
---|
| 572 | case 6:
|
---|
| 573 | ver2("XBIOS X_PRBOOT 0x%08x %u %u %u",
|
---|
| 574 | m68k_read_memory_32(sp + 2),
|
---|
| 575 | m68k_read_memory_16(sp + 6),
|
---|
| 576 | m68k_read_memory_16(sp + 8),
|
---|
| 577 | m68k_read_memory_16(sp + 10));
|
---|
| 578 | break;
|
---|
| 579 |
|
---|
| 580 | case 7:
|
---|
| 581 | ver2("XBIOS X_RANDOM");
|
---|
| 582 | break;
|
---|
| 583 |
|
---|
| 584 | case 8:
|
---|
| 585 | ver2("XBIOS X_ANALOG");
|
---|
| 586 | break;
|
---|
| 587 |
|
---|
| 588 | case 9:
|
---|
| 589 | ver2("XBIOS X_CLRAFI");
|
---|
| 590 | break;
|
---|
| 591 |
|
---|
| 592 | case 10:
|
---|
| 593 | ver2("XBIOS X_APICHK");
|
---|
| 594 | break;
|
---|
| 595 |
|
---|
| 596 | case 11:
|
---|
| 597 | ver2("XBIOS X_MTDEFS ");
|
---|
| 598 | break;
|
---|
| 599 |
|
---|
| 600 | default:
|
---|
| 601 | fail("invalid function: XBIOS %d", fun);
|
---|
| 602 | }
|
---|
| 603 | }
|
---|
| 604 | }
|
---|
| 605 |
|
---|
[b909777] | 606 | void cpu_loop(const char *bios)
|
---|
[ff8d800] | 607 | {
|
---|
[a06aa8b] | 608 | hw_init();
|
---|
[b909777] | 609 | bios_init(bios);
|
---|
[ff8d800] | 610 |
|
---|
[ba36b71] | 611 | inf("entering CPU loop");
|
---|
[ff8d800] | 612 | m68k_init();
|
---|
| 613 | m68k_set_cpu_type(M68K_CPU_TYPE_68000);
|
---|
[9674f1a] | 614 | m68k_set_instr_hook_callback(inst_cb);
|
---|
[ff8d800] | 615 | m68k_pulse_reset();
|
---|
| 616 |
|
---|
[ebc8f69] | 617 | uint64_t freq = SDL_GetPerformanceFrequency();
|
---|
| 618 | uint64_t quan = freq / PER_SEC;
|
---|
| 619 | inf("freq %" PRIu64 " quan %" PRIu64, freq, quan);
|
---|
| 620 |
|
---|
[e41c6b6] | 621 | bool run = true;
|
---|
[bb4fd0c] | 622 | bool down = false;
|
---|
[e41c6b6] | 623 |
|
---|
| 624 | while (run) {
|
---|
[ebc8f69] | 625 | uint64_t until = SDL_GetPerformanceCounter() + quan;
|
---|
| 626 |
|
---|
| 627 | m68k_execute(CPU_FREQ / PER_SEC);
|
---|
[a06aa8b] | 628 | hw_exec();
|
---|
[e41c6b6] | 629 |
|
---|
| 630 | SDL_Event ev;
|
---|
| 631 |
|
---|
| 632 | while (SDL_PollEvent(&ev) > 0) {
|
---|
[bb4fd0c] | 633 | // Work around duplicate key-down events on Linux.
|
---|
| 634 |
|
---|
| 635 | if (ev.type == SDL_KEYDOWN) {
|
---|
| 636 | if (down) {
|
---|
| 637 | continue;
|
---|
| 638 | }
|
---|
| 639 |
|
---|
| 640 | down = true;
|
---|
| 641 | }
|
---|
| 642 | else if (ev.type == SDL_KEYUP) {
|
---|
| 643 | down = false;
|
---|
| 644 | }
|
---|
| 645 |
|
---|
| 646 | if (ev.type == SDL_QUIT ||
|
---|
| 647 | (ev.type == SDL_KEYDOWN && ev.key.keysym.sym == SDLK_ESCAPE)) {
|
---|
[e41c6b6] | 648 | run = false;
|
---|
[bb4fd0c] | 649 | continue;
|
---|
| 650 | }
|
---|
| 651 |
|
---|
| 652 | if (ev.type == SDL_TEXTINPUT) {
|
---|
| 653 | ser_text(&ev.text);
|
---|
| 654 | continue;
|
---|
| 655 | }
|
---|
| 656 |
|
---|
| 657 | if (ev.type == SDL_KEYDOWN) {
|
---|
| 658 | ser_key(&ev.key);
|
---|
| 659 | continue;
|
---|
[e41c6b6] | 660 | }
|
---|
| 661 | }
|
---|
[ebc8f69] | 662 |
|
---|
| 663 | while (SDL_GetPerformanceCounter() < until) {
|
---|
| 664 | _mm_pause();
|
---|
| 665 | }
|
---|
[ff8d800] | 666 | }
|
---|
[e41c6b6] | 667 |
|
---|
| 668 | inf("leaving CPU loop");
|
---|
[bb4fd0c] | 669 | hw_quit();
|
---|
[ff8d800] | 670 | }
|
---|