1 | /*
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2 | * Copyright (C) 2017 The Contributors
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3 | *
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4 | * This program is free software: you can redistribute it and/or modify
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5 | * it under the terms of the GNU General Public License as published by
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6 | * the Free Software Foundation, either version 3 of the License, or (at
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7 | * your option) any later version.
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8 | *
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9 | * This program is distributed in the hope that it will be useful, but
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10 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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12 | * General Public License for more details.
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13 | *
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14 | * A copy of the GNU General Public License can be found in the file
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15 | * "gpl.txt" in the top directory of this repository.
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16 | */
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17 |
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18 | #include <all.h>
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19 |
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20 | #define ver(...) _ver(cpu_verbose, 0, __VA_ARGS__)
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21 | #define ver2(...) _ver(cpu_verbose, 1, __VA_ARGS__)
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22 | #define ver3(...) _ver(cpu_verbose, 2, __VA_ARGS__)
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23 |
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24 | int32_t cpu_verbose = 0;
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25 |
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26 | #define CPU_FREQ 7000000
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27 | #define PER_SEC 100000
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28 |
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29 | #define APP_START 0x10000
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30 |
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31 | #define RAM_START 0x0
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32 | #define RAM_SIZE 0x100000
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33 |
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34 | #define ROM_START 0x100000
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35 | #define ROM_SIZE 0x10000
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36 |
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37 | typedef void (*hw_init_t)(void);
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38 | typedef void (*hw_quit_t)(void);
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39 | typedef bool (*hw_exec_t)(void);
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40 | typedef uint32_t (*hw_read_t)(uint32_t off, int32_t sz);
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41 | typedef void (*hw_write_t)(uint32_t off, int32_t sz, uint32_t val);
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42 |
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43 | typedef struct {
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44 | uint32_t addr_beg;
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45 | uint32_t addr_end;
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46 | uint32_t irq;
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47 | hw_init_t init;
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48 | hw_quit_t quit;
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49 | hw_exec_t exec;
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50 | hw_read_t read;
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51 | hw_write_t write;
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52 | } hw_t;
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53 |
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54 | static bool reset = true;
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55 |
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56 | static uint8_t ram_data[RAM_SIZE];
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57 | static uint8_t rom_data[ROM_SIZE];
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58 |
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59 | static uint32_t ram_ro_beg = 0x1234;
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60 | static uint32_t ram_ro_end = 0x1234;
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61 | static uint32_t ram_rw_beg = 0x1234;
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62 | static uint32_t ram_rw_end = 0x1234;
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63 |
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64 | static uint32_t rom_ro_beg;
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65 | static uint32_t rom_ro_end;
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66 | static uint32_t rom_rw_beg;
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67 | static uint32_t rom_rw_end;
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68 |
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69 | static hw_t hw_map[] = {
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70 | { 0x180000, 0x200000, 0, fpu_init, fpu_quit, fpu_exec, fpu_read, fpu_write },
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71 | { 0x200000, 0x280000, 0, vid_init, vid_quit, vid_exec, vid_read, vid_write },
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72 | { 0x3a0001, 0x3a4001, 0, tim_init, tim_quit, tim_exec, tim_read, tim_write },
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73 | { 0x3a4001, 0x3a8001, 0, lcd_init, lcd_quit, lcd_exec, lcd_read, lcd_write },
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74 | { 0x3a8001, 0x3ac001, 5, ser_init, ser_quit, ser_exec, ser_read, ser_write },
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75 | { 0x3ac001, 0x3b0001, 0, mid_init, mid_quit, mid_exec, mid_read, mid_write },
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76 | { 0x3b0001, 0x3b4001, 0, fdd_init, fdd_quit, fdd_exec, fdd_read, fdd_write },
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77 | { 0x3b4001, 0x3b8001, 0, snd_init, snd_quit, snd_exec, snd_read, snd_write },
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78 | { 0x3b8001, 0x3bc001, 0, led_init, led_quit, led_exec, led_read, led_write },
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79 | { 0x3bc001, 0x3c0001, 0, kbd_init, kbd_quit, kbd_exec, kbd_read, kbd_write }
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80 | };
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81 |
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82 | static hw_t *hw_by_addr(uint32_t addr)
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83 | {
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84 | for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
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85 | if (addr >= hw_map[i].addr_beg && addr < hw_map[i].addr_end) {
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86 | return hw_map + i;
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87 | }
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88 | }
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89 |
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90 | return NULL;
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91 | }
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92 |
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93 | static void hw_init(void)
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94 | {
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95 | inf("starting hardware");
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96 |
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97 | for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
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98 | hw_map[i].init();
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99 | }
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100 | }
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101 |
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102 | static void hw_quit(void)
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103 | {
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104 | inf("halting hardware");
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105 |
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106 | for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
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107 | hw_map[i].quit();
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108 | }
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109 | }
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110 |
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111 | static uint32_t hw_exec(void)
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112 | {
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113 | uint32_t irq = 0;
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114 |
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115 | for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
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116 | if (hw_map[i].exec() && hw_map[i].irq > irq) {
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117 | irq = hw_map[i].irq;
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118 | }
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119 | }
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120 |
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121 | return irq;
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122 | }
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123 |
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124 | static uint32_t hw_off(hw_t *hw, uint32_t addr)
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125 | {
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126 | if ((hw->addr_beg & 0x1) == 0) {
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127 | return addr - hw->addr_beg;
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128 | }
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129 |
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130 | return (addr - hw->addr_beg) / 2;
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131 | }
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132 |
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133 | static void bios_init(void)
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134 | {
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135 | inf("loading BIOS file %s", bios);
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136 |
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137 | SDL_RWops *ops = SDL_RWFromFile(bios, "rb");
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138 |
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139 | if (ops == NULL) {
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140 | fail("error while opening BIOS file %s", bios);
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141 | }
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142 |
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143 | if (SDL_ReadBE16(ops) != 0x601b) {
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144 | fail("invalid BIOS file %s", bios);
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145 | }
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146 |
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147 | uint32_t text_len = SDL_ReadBE32(ops);
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148 | uint32_t data_len = SDL_ReadBE32(ops);
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149 | uint32_t bss_len = SDL_ReadBE32(ops);
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150 |
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151 | SDL_ReadBE32(ops);
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152 | SDL_ReadBE32(ops);
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153 |
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154 | uint32_t text_loc = SDL_ReadBE32(ops);
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155 |
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156 | SDL_ReadBE16(ops);
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157 |
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158 | uint32_t data_loc = SDL_ReadBE32(ops);
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159 | uint32_t bss_loc = SDL_ReadBE32(ops);
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160 |
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161 | inf("BIOS text 0x%x:0x%x data 0x%x:0x%x bss 0x%x:0x%x",
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162 | text_loc, text_len, data_loc, data_len, bss_loc, bss_len);
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163 |
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164 | size_t load_len = (size_t)SDL_RWsize(ops) - 36;
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165 |
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166 | if (text_loc != ROM_START || text_loc + text_len != data_loc ||
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167 | load_len != text_len + data_len || load_len > ROM_SIZE) {
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168 | fail("invalid BIOS file %s", bios);
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169 | }
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170 |
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171 | size_t loaded = 0;
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172 |
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173 | while (loaded < load_len) {
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174 | size_t n_rd = SDL_RWread(ops, rom_data + loaded, 1, load_len - loaded);
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175 |
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176 | if (n_rd == 0) {
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177 | fail("error while reading BIOS file %s", bios);
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178 | }
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179 |
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180 | loaded += n_rd;
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181 | }
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182 |
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183 | SDL_RWclose(ops);
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184 |
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185 | rom_ro_beg = text_loc;
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186 | rom_ro_end = text_loc + text_len + data_len;
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187 | rom_rw_beg = bss_loc;
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188 | rom_rw_end = bss_loc + bss_len;
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189 |
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190 | ver("rom_ro_beg 0x%08x rom_ro_end 0x%08x", rom_ro_beg, rom_ro_end);
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191 | ver("rom_rw_beg 0x%08x rom_rw_end 0x%08x", rom_rw_beg, rom_rw_end);
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192 | }
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193 |
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194 | uint32_t m68k_read_disassembler_8(uint32_t addr)
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195 | {
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196 | return m68k_read_memory_8(addr);
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197 | }
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198 |
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199 | uint32_t m68k_read_disassembler_16(uint32_t addr)
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200 | {
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201 | return m68k_read_memory_16(addr);
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202 | }
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203 |
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204 | uint32_t m68k_read_disassembler_32(uint32_t addr)
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205 | {
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206 | return m68k_read_memory_32(addr);
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207 | }
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208 |
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209 | uint32_t m68k_read_memory_8(uint32_t addr)
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210 | {
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211 | ver3("mem rd 0x%08x:8", addr);
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212 |
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213 | if (addr >= ram_ro_beg && addr <= ram_ro_end - 1) {
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214 | return ram_data[addr - RAM_START];
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215 | }
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216 |
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217 | if (addr >= ram_rw_beg && addr <= ram_rw_end - 1) {
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218 | return ram_data[addr - RAM_START];
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219 | }
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220 |
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221 | if (addr >= rom_ro_beg && addr <= rom_ro_end - 1) {
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222 | return rom_data[addr - ROM_START];
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223 | }
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224 |
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225 | if (addr >= rom_rw_beg && addr <= rom_rw_end - 1) {
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226 | // ROM has its BSS section in RAM.
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227 | return ram_data[addr - RAM_START];
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228 | }
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229 |
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230 | hw_t *hw = hw_by_addr(addr);
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231 |
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232 | if (hw != NULL) {
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233 | return hw->read(hw_off(hw, addr), 1);
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234 | }
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235 |
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236 | if (addr <= APP_START - 1) {
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237 | return ram_data[addr];
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238 | }
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239 |
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240 | fail("invalid read 0x%08x:8", addr);
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241 | }
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242 |
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243 | uint32_t m68k_read_memory_16(uint32_t addr)
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244 | {
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245 | ver3("mem rd 0x%08x:16", addr);
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246 |
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247 | if (addr >= ram_ro_beg && addr <= ram_ro_end - 2) {
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248 | return
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249 | ((uint32_t)ram_data[addr - RAM_START + 0] << 8) |
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250 | ((uint32_t)ram_data[addr - RAM_START + 1] << 0);
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251 | }
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252 |
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253 | if (addr >= ram_rw_beg && addr <= ram_rw_end - 2) {
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254 | return
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255 | ((uint32_t)ram_data[addr - RAM_START + 0] << 8) |
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256 | ((uint32_t)ram_data[addr - RAM_START + 1] << 0);
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257 | }
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258 |
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259 | if (addr >= rom_ro_beg && addr <= rom_ro_end - 2) {
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260 | return
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261 | ((uint32_t)rom_data[addr - ROM_START + 0] << 8) |
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262 | ((uint32_t)rom_data[addr - ROM_START + 1] << 0);
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263 | }
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264 |
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265 | if (addr >= rom_rw_beg && addr <= rom_rw_end - 2) {
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266 | // ROM has its BSS section in RAM.
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267 | return
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268 | ((uint32_t)ram_data[addr - RAM_START + 0] << 8) |
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269 | ((uint32_t)ram_data[addr - RAM_START + 1] << 0);
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270 | }
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271 |
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272 | hw_t *hw = hw_by_addr(addr);
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273 |
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274 | if (hw != NULL) {
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275 | return hw->read(hw_off(hw, addr), 2);
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276 | }
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277 |
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278 | if (addr <= APP_START - 2) {
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279 | return
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280 | ((uint32_t)ram_data[addr + 0] << 8) |
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281 | ((uint32_t)ram_data[addr + 1] << 0);
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282 | }
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283 |
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284 | fail("invalid read 0x%08x:16", addr);
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285 | }
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286 |
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287 | uint32_t m68k_read_memory_32(uint32_t addr)
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288 | {
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289 | ver3("mem rd 0x%08x:32", addr);
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290 |
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291 | if (reset) {
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292 | if (addr == 0) {
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293 | addr += ROM_START;
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294 | }
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295 | else if (addr == 4) {
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296 | addr += ROM_START;
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297 | reset = false;
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298 | }
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299 | else {
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300 | fail("invalid reset sequence");
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301 | }
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302 | }
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303 |
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304 | if (addr >= ram_ro_beg && addr <= ram_ro_end - 4) {
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305 | return
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306 | ((uint32_t)ram_data[addr - RAM_START + 0] << 24) |
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307 | ((uint32_t)ram_data[addr - RAM_START + 1] << 16) |
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308 | ((uint32_t)ram_data[addr - RAM_START + 2] << 8) |
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309 | ((uint32_t)ram_data[addr - RAM_START + 3] << 0);
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310 | }
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311 |
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312 | if (addr >= ram_rw_beg && addr <= ram_rw_end - 4) {
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313 | return
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314 | ((uint32_t)ram_data[addr - RAM_START + 0] << 24) |
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315 | ((uint32_t)ram_data[addr - RAM_START + 1] << 16) |
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316 | ((uint32_t)ram_data[addr - RAM_START + 2] << 8) |
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317 | ((uint32_t)ram_data[addr - RAM_START + 3] << 0);
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318 | }
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319 |
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320 | if (addr >= rom_ro_beg && addr <= rom_ro_end - 4) {
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321 | return
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322 | ((uint32_t)rom_data[addr - ROM_START + 0] << 24) |
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323 | ((uint32_t)rom_data[addr - ROM_START + 1] << 16) |
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324 | ((uint32_t)rom_data[addr - ROM_START + 2] << 8) |
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325 | ((uint32_t)rom_data[addr - ROM_START + 3] << 0);
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326 | }
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327 |
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328 | if (addr >= rom_rw_beg && addr <= rom_rw_end - 4) {
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329 | // ROM has its BSS section in RAM.
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330 | return
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331 | ((uint32_t)ram_data[addr - RAM_START + 0] << 24) |
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332 | ((uint32_t)ram_data[addr - RAM_START + 1] << 16) |
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333 | ((uint32_t)ram_data[addr - RAM_START + 2] << 8) |
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334 | ((uint32_t)ram_data[addr - RAM_START + 3] << 0);
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335 | }
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336 |
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337 | hw_t *hw = hw_by_addr(addr);
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338 |
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339 | if (hw != NULL) {
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340 | return hw->read(hw_off(hw, addr), 4);
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341 | }
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342 |
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343 | if (addr <= APP_START - 4) {
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344 | return
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345 | ((uint32_t)ram_data[addr + 0] << 24) |
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346 | ((uint32_t)ram_data[addr + 1] << 16) |
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347 | ((uint32_t)ram_data[addr + 2] << 8) |
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348 | ((uint32_t)ram_data[addr + 3] << 0);
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349 | }
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350 |
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351 | fail("invalid read 0x%08x:32", addr);
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352 | }
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353 |
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354 | void m68k_write_memory_8(uint32_t addr, uint32_t val)
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355 | {
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356 | ver3("mem wr 0x%08x:8 0x%02x", addr, val);
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357 |
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358 | if (addr >= ram_rw_beg && addr <= ram_rw_end - 1) {
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359 | ram_data[addr - RAM_START] = (uint8_t)val;
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360 | return;
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361 | }
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362 |
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363 | if (addr >= rom_rw_beg && addr <= rom_rw_end - 1) {
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364 | // ROM has its BSS section in RAM.
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365 | ram_data[addr - RAM_START] = (uint8_t)val;
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366 | return;
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367 | }
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368 |
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369 | hw_t *hw = hw_by_addr(addr);
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370 |
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371 | if (hw != NULL) {
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372 | hw->write(hw_off(hw, addr), 1, val);
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373 | return;
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374 | }
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375 |
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376 | if (addr <= APP_START - 1) {
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377 | ram_data[addr] = (uint8_t)val;
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378 | return;
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379 | }
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380 |
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381 | // handle loading midas.abs
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382 |
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383 | if (addr == APP_START) {
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384 | ram_rw_beg = APP_START;
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385 | ram_rw_end = RAM_START + RAM_SIZE;
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386 | return;
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387 | }
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388 |
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389 | fail("invalid write 0x%08x:8 0x%02x", addr, val);
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390 | }
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391 |
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392 | void m68k_write_memory_16(uint32_t addr, uint32_t val)
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393 | {
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394 | ver3("mem wr 0x%08x:16 0x%04x", addr, val);
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395 |
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396 | if (addr >= ram_rw_beg && addr <= ram_rw_end - 2) {
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397 | ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 8);
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398 | ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 0);
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399 | return;
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400 | }
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401 |
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402 | if (addr >= rom_rw_beg && addr <= rom_rw_end - 2) {
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403 | // ROM has its BSS section in RAM.
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404 | ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 8);
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405 | ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 0);
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406 | return;
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407 | }
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408 |
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409 | hw_t *hw = hw_by_addr(addr);
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410 |
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411 | if (hw != NULL) {
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412 | hw->write(hw_off(hw, addr), 2, val);
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413 | return;
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414 | }
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415 |
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416 | if (addr <= APP_START - 2) {
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417 | ram_data[addr + 0] = (uint8_t)(val >> 8);
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418 | ram_data[addr + 1] = (uint8_t)(val >> 0);
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419 | return;
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420 | }
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421 |
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422 | fail("invalid write 0x%08x:16 0x%04x", addr, val);
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423 | }
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424 |
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425 | void m68k_write_memory_32(uint32_t addr, uint32_t val)
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426 | {
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427 | ver3("mem wr 0x%08x:32 0x%08x", addr, val);
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428 |
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429 | if (addr >= ram_rw_beg && addr <= ram_rw_end - 4) {
|
---|
430 | ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 24);
|
---|
431 | ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 16);
|
---|
432 | ram_data[addr - RAM_START + 2] = (uint8_t)(val >> 8);
|
---|
433 | ram_data[addr - RAM_START + 3] = (uint8_t)(val >> 0);
|
---|
434 | return;
|
---|
435 | }
|
---|
436 |
|
---|
437 | if (addr >= rom_rw_beg && addr <= rom_rw_end - 4) {
|
---|
438 | // ROM has its BSS section in RAM.
|
---|
439 | ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 24);
|
---|
440 | ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 16);
|
---|
441 | ram_data[addr - RAM_START + 2] = (uint8_t)(val >> 8);
|
---|
442 | ram_data[addr - RAM_START + 3] = (uint8_t)(val >> 0);
|
---|
443 | return;
|
---|
444 | }
|
---|
445 |
|
---|
446 | hw_t *hw = hw_by_addr(addr);
|
---|
447 |
|
---|
448 | if (hw != NULL) {
|
---|
449 | hw->write(hw_off(hw, addr), 4, val);
|
---|
450 | return;
|
---|
451 | }
|
---|
452 |
|
---|
453 | if (addr <= APP_START - 4) {
|
---|
454 | ram_data[addr + 0] = (uint8_t)(val >> 24);
|
---|
455 | ram_data[addr + 1] = (uint8_t)(val >> 16);
|
---|
456 | ram_data[addr + 2] = (uint8_t)(val >> 8);
|
---|
457 | ram_data[addr + 3] = (uint8_t)(val >> 0);
|
---|
458 | return;
|
---|
459 | }
|
---|
460 |
|
---|
461 | fail("invalid write 0x%08x:32 0x%08x", addr, val);
|
---|
462 | }
|
---|
463 |
|
---|
464 | static void inst_cb(void)
|
---|
465 | {
|
---|
466 | uint32_t pc = m68k_get_reg(NULL, M68K_REG_PC);
|
---|
467 | uint32_t op = m68k_read_memory_16(pc);
|
---|
468 |
|
---|
469 | if (op == 0x4e4d) {
|
---|
470 | uint32_t sp = m68k_get_reg(NULL, M68K_REG_SP);
|
---|
471 | uint32_t fun = m68k_read_memory_16(sp);
|
---|
472 |
|
---|
473 | switch (fun) {
|
---|
474 | case 1:
|
---|
475 | ver2("BIOS B_RDAV %u", m68k_read_memory_16(sp + 2));
|
---|
476 | break;
|
---|
477 |
|
---|
478 | case 2:
|
---|
479 | ver2("BIOS B_GETC %u", m68k_read_memory_16(sp + 2));
|
---|
480 | break;
|
---|
481 |
|
---|
482 | case 3:
|
---|
483 | ver2("BIOS B_PUTC %u %u",
|
---|
484 | m68k_read_memory_16(sp + 2),
|
---|
485 | m68k_read_memory_16(sp + 4));
|
---|
486 | break;
|
---|
487 |
|
---|
488 | case 4:
|
---|
489 | ver2("BIOS B_RDWR %u 0x%08x %u %u %u",
|
---|
490 | m68k_read_memory_16(sp + 2),
|
---|
491 | m68k_read_memory_32(sp + 4),
|
---|
492 | m68k_read_memory_16(sp + 8),
|
---|
493 | m68k_read_memory_16(sp + 10),
|
---|
494 | m68k_read_memory_16(sp + 12));
|
---|
495 | break;
|
---|
496 |
|
---|
497 | case 5:
|
---|
498 | ver2("BIOS B_SETV %u 0x%08x",
|
---|
499 | m68k_read_memory_16(sp + 2),
|
---|
500 | m68k_read_memory_32(sp + 4));
|
---|
501 | break;
|
---|
502 |
|
---|
503 | case 7:
|
---|
504 | ver2("BIOS B_GBPB %u", m68k_read_memory_16(sp + 2));
|
---|
505 | break;
|
---|
506 |
|
---|
507 | case 8:
|
---|
508 | ver2("BIOS B_THRE %u", m68k_read_memory_16(sp + 2));
|
---|
509 | break;
|
---|
510 |
|
---|
511 | case 9:
|
---|
512 | ver2("BIOS B_MCHG %u", m68k_read_memory_16(sp + 2));
|
---|
513 | break;
|
---|
514 |
|
---|
515 | case 10:
|
---|
516 | ver2("BIOS B_DMAP");
|
---|
517 | break;
|
---|
518 |
|
---|
519 | default:
|
---|
520 | fail("invalid function: BIOS %d", fun);
|
---|
521 | }
|
---|
522 | }
|
---|
523 | else if (op == 0x4e4e) {
|
---|
524 | uint32_t sp = m68k_get_reg(NULL, M68K_REG_SP);
|
---|
525 | uint32_t fun = m68k_read_memory_16(sp);
|
---|
526 |
|
---|
527 | switch (fun) {
|
---|
528 | case 0:
|
---|
529 | ver2("XBIOS X_PIOREC %u", m68k_read_memory_16(sp + 2));
|
---|
530 | break;
|
---|
531 |
|
---|
532 | case 1:
|
---|
533 | ver2("XBIOS X_SETPRT %u 0x%02x 0x%02x 0x%02x 0x%02x",
|
---|
534 | m68k_read_memory_16(sp + 2),
|
---|
535 | m68k_read_memory_16(sp + 4),
|
---|
536 | m68k_read_memory_16(sp + 6),
|
---|
537 | m68k_read_memory_16(sp + 8),
|
---|
538 | m68k_read_memory_16(sp + 10));
|
---|
539 | break;
|
---|
540 |
|
---|
541 | case 2:
|
---|
542 | ver2("XBIOS X_FLOPRD 0x%08x 0x%08x %u %u %u %u %u",
|
---|
543 | m68k_read_memory_32(sp + 2),
|
---|
544 | m68k_read_memory_32(sp + 6),
|
---|
545 | m68k_read_memory_16(sp + 10),
|
---|
546 | m68k_read_memory_16(sp + 12),
|
---|
547 | m68k_read_memory_16(sp + 14),
|
---|
548 | m68k_read_memory_16(sp + 16),
|
---|
549 | m68k_read_memory_16(sp + 18));
|
---|
550 | break;
|
---|
551 |
|
---|
552 | case 3:
|
---|
553 | ver2("XBIOS X_FLOPWR 0x%08x 0x%08x %u %u %u %u %u",
|
---|
554 | m68k_read_memory_32(sp + 2),
|
---|
555 | m68k_read_memory_32(sp + 6),
|
---|
556 | m68k_read_memory_16(sp + 10),
|
---|
557 | m68k_read_memory_16(sp + 12),
|
---|
558 | m68k_read_memory_16(sp + 14),
|
---|
559 | m68k_read_memory_16(sp + 16),
|
---|
560 | m68k_read_memory_16(sp + 18));
|
---|
561 | break;
|
---|
562 |
|
---|
563 | case 4:
|
---|
564 | ver2("XBIOS X_FORMAT 0x%08x 0x%08x %u %u %u %u %u 0x%08x %u",
|
---|
565 | m68k_read_memory_32(sp + 2),
|
---|
566 | m68k_read_memory_32(sp + 6),
|
---|
567 | m68k_read_memory_16(sp + 10),
|
---|
568 | m68k_read_memory_16(sp + 12),
|
---|
569 | m68k_read_memory_16(sp + 14),
|
---|
570 | m68k_read_memory_16(sp + 16),
|
---|
571 | m68k_read_memory_16(sp + 18),
|
---|
572 | m68k_read_memory_32(sp + 20),
|
---|
573 | m68k_read_memory_16(sp + 24));
|
---|
574 | break;
|
---|
575 |
|
---|
576 | case 5:
|
---|
577 | ver2("XBIOS X_VERIFY 0x%08x 0x%08x %u %u %u %u %u",
|
---|
578 | m68k_read_memory_32(sp + 2),
|
---|
579 | m68k_read_memory_32(sp + 6),
|
---|
580 | m68k_read_memory_16(sp + 10),
|
---|
581 | m68k_read_memory_16(sp + 12),
|
---|
582 | m68k_read_memory_16(sp + 14),
|
---|
583 | m68k_read_memory_16(sp + 16),
|
---|
584 | m68k_read_memory_16(sp + 18));
|
---|
585 | break;
|
---|
586 |
|
---|
587 | case 6:
|
---|
588 | ver2("XBIOS X_PRBOOT 0x%08x %u %u %u",
|
---|
589 | m68k_read_memory_32(sp + 2),
|
---|
590 | m68k_read_memory_16(sp + 6),
|
---|
591 | m68k_read_memory_16(sp + 8),
|
---|
592 | m68k_read_memory_16(sp + 10));
|
---|
593 | break;
|
---|
594 |
|
---|
595 | case 7:
|
---|
596 | ver2("XBIOS X_RANDOM");
|
---|
597 | break;
|
---|
598 |
|
---|
599 | case 8:
|
---|
600 | ver2("XBIOS X_ANALOG");
|
---|
601 | break;
|
---|
602 |
|
---|
603 | case 9:
|
---|
604 | ver2("XBIOS X_CLRAFI");
|
---|
605 | break;
|
---|
606 |
|
---|
607 | case 10:
|
---|
608 | ver2("XBIOS X_APICHK");
|
---|
609 | break;
|
---|
610 |
|
---|
611 | case 11:
|
---|
612 | ver2("XBIOS X_MTDEFS ");
|
---|
613 | break;
|
---|
614 |
|
---|
615 | default:
|
---|
616 | fail("invalid function: XBIOS %d", fun);
|
---|
617 | }
|
---|
618 | }
|
---|
619 | }
|
---|
620 |
|
---|
621 | void cpu_loop(void)
|
---|
622 | {
|
---|
623 | hw_init();
|
---|
624 | bios_init();
|
---|
625 |
|
---|
626 | inf("entering CPU loop");
|
---|
627 | m68k_init();
|
---|
628 | m68k_set_cpu_type(M68K_CPU_TYPE_68000);
|
---|
629 | m68k_set_instr_hook_callback(inst_cb);
|
---|
630 | m68k_pulse_reset();
|
---|
631 |
|
---|
632 | uint64_t freq = SDL_GetPerformanceFrequency();
|
---|
633 | uint64_t quan = freq / PER_SEC;
|
---|
634 | inf("freq %" PRIu64 " quan %" PRIu64, freq, quan);
|
---|
635 |
|
---|
636 | bool run = true;
|
---|
637 |
|
---|
638 | #if defined EMU_LINUX
|
---|
639 | SDL_Scancode down = SDL_SCANCODE_UNKNOWN;
|
---|
640 | #endif
|
---|
641 |
|
---|
642 | while (run) {
|
---|
643 | uint64_t until = SDL_GetPerformanceCounter() + quan;
|
---|
644 |
|
---|
645 | m68k_execute(CPU_FREQ / PER_SEC);
|
---|
646 | uint32_t irq = hw_exec();
|
---|
647 |
|
---|
648 | if (irq > 0) {
|
---|
649 | ver2("irq %u", irq);
|
---|
650 | }
|
---|
651 |
|
---|
652 | m68k_set_irq(irq);
|
---|
653 |
|
---|
654 | SDL_Event ev;
|
---|
655 |
|
---|
656 | while (SDL_PollEvent(&ev) > 0) {
|
---|
657 | #if defined EMU_LINUX
|
---|
658 | // Work around duplicate key-down events on Linux.
|
---|
659 |
|
---|
660 | if (ev.type == SDL_KEYDOWN) {
|
---|
661 | if (down == ev.key.keysym.scancode) {
|
---|
662 | continue;
|
---|
663 | }
|
---|
664 |
|
---|
665 | down = ev.key.keysym.scancode;
|
---|
666 | }
|
---|
667 | else if (ev.type == SDL_KEYUP) {
|
---|
668 | down = SDL_SCANCODE_UNKNOWN;
|
---|
669 | }
|
---|
670 | #endif
|
---|
671 |
|
---|
672 | if (ev.type == SDL_QUIT ||
|
---|
673 | (ev.type == SDL_KEYDOWN && ev.key.keysym.sym == SDLK_ESCAPE)) {
|
---|
674 | run = false;
|
---|
675 | continue;
|
---|
676 | }
|
---|
677 |
|
---|
678 | if (ev.type == SDL_TEXTINPUT) {
|
---|
679 | ser_text(&ev.text);
|
---|
680 | continue;
|
---|
681 | }
|
---|
682 |
|
---|
683 | if (ev.type == SDL_KEYDOWN) {
|
---|
684 | ser_key(&ev.key);
|
---|
685 | continue;
|
---|
686 | }
|
---|
687 | }
|
---|
688 |
|
---|
689 | while (SDL_GetPerformanceCounter() < until) {
|
---|
690 | _mm_pause();
|
---|
691 | }
|
---|
692 | }
|
---|
693 |
|
---|
694 | inf("leaving CPU loop");
|
---|
695 | hw_quit();
|
---|
696 | }
|
---|