source: buchla-emu/emu/cpu.c@ e5a7d09

Last change on this file since e5a7d09 was 0529a19, checked in by Alexander Heinrich <alex.heinrich@…>, 8 years ago

Add basic handling of midi input.
  • Property mode set to 100644
File size: 17.5 KB
Line 
1/*
2 * Copyright (C) 2017 The Contributors
3 *
4 * This program is free software: you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation, either version 3 of the License, or (at
7 * your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
13 *
14 * A copy of the GNU General Public License can be found in the file
15 * "gpl.txt" in the top directory of this repository.
16 */
17
18#include <all.h>
19
20#define ver(...) _ver(cpu_verbose, 0, __VA_ARGS__)
21#define ver2(...) _ver(cpu_verbose, 1, __VA_ARGS__)
22#define ver3(...) _ver(cpu_verbose, 2, __VA_ARGS__)
23
24int32_t cpu_verbose = 0;
25
26#define MIDAS_ABS "midas.abs"
27
28#define CPU_FREQ 7000000
29#define PER_SEC 100000
30
31#define APP_START 0x10000
32
33#define RAM_START 0x0
34#define RAM_SIZE 0x100000
35
36#define ROM_START 0x100000
37#define ROM_SIZE 0x10000
38
39typedef void (*hw_init_t)(void);
40typedef void (*hw_quit_t)(void);
41typedef bool (*hw_exec_t)(void);
42typedef uint32_t (*hw_read_t)(uint32_t off, int32_t sz);
43typedef void (*hw_write_t)(uint32_t off, int32_t sz, uint32_t val);
44
45typedef struct {
46 uint32_t addr_beg;
47 uint32_t addr_end;
48 uint32_t irq;
49 hw_init_t init;
50 hw_quit_t quit;
51 hw_exec_t exec;
52 hw_read_t read;
53 hw_write_t write;
54} hw_t;
55
56typedef struct {
57 uint32_t text_loc;
58 uint32_t text_len;
59 uint32_t data_loc;
60 uint32_t data_len;
61 uint32_t bss_loc;
62 uint32_t bss_len;
63 size_t load_len;
64 SDL_RWops *ops;
65} abs_t;
66
67static uint64_t freq;
68static uint64_t quan;
69
70SDL_mutex *cpu_mutex;
71
72static bool reset = true;
73
74static uint8_t ram_data[RAM_SIZE];
75static uint8_t rom_data[ROM_SIZE];
76
77static uint32_t ram_ro_beg = 0x1234;
78static uint32_t ram_ro_end = 0x1234;
79static uint32_t ram_rw_beg = 0x1234;
80static uint32_t ram_rw_end = 0x1234;
81
82static uint32_t rom_ro_beg;
83static uint32_t rom_ro_end;
84static uint32_t rom_rw_beg;
85static uint32_t rom_rw_end;
86
87static hw_t hw_map[] = {
88 { 0x180000, 0x200000, 0, fpu_init, fpu_quit, fpu_exec, fpu_read, fpu_write },
89 { 0x200000, 0x280002, 1, vid_init, vid_quit, vid_exec, vid_read, vid_write },
90 { 0x3a0001, 0x3a4001, 4, tim_init, tim_quit, tim_exec, tim_read, tim_write },
91 { 0x3a4001, 0x3a8001, 0, lcd_init, lcd_quit, lcd_exec, lcd_read, lcd_write },
92 { 0x3a8001, 0x3ac001, 5, ser_init, ser_quit, ser_exec, ser_read, ser_write },
93 { 0x3ac001, 0x3b0001, 5, mid_init, mid_quit, mid_exec, mid_read, mid_write },
94 { 0x3b0001, 0x3b4001, 0, fdd_init, fdd_quit, fdd_exec, fdd_read, fdd_write },
95 { 0x3b4001, 0x3b8001, 0, snd_init, snd_quit, snd_exec, snd_read, snd_write },
96 { 0x3b8001, 0x3bc001, 0, led_init, led_quit, led_exec, led_read, led_write },
97 { 0x3bc001, 0x3c0001, 3, kbd_init, kbd_quit, kbd_exec, kbd_read, kbd_write }
98};
99
100static hw_t *hw_by_addr(uint32_t addr)
101{
102 for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
103 if (addr >= hw_map[i].addr_beg && addr < hw_map[i].addr_end) {
104 return hw_map + i;
105 }
106 }
107
108 return NULL;
109}
110
111static void hw_init(void)
112{
113 inf("starting hardware");
114
115 for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
116 hw_map[i].init();
117 }
118}
119
120static void hw_quit(void)
121{
122 inf("halting hardware");
123
124 for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
125 hw_map[i].quit();
126 }
127}
128
129static uint32_t hw_exec(void)
130{
131 uint32_t irq = 0;
132
133 for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
134 if (hw_map[i].exec() && hw_map[i].irq > irq) {
135 irq = hw_map[i].irq;
136 }
137 }
138
139 return irq;
140}
141
142static uint32_t hw_off(hw_t *hw, uint32_t addr)
143{
144 if ((hw->addr_beg & 0x1) == 0) {
145 return addr - hw->addr_beg;
146 }
147
148 return (addr - hw->addr_beg) / 2;
149}
150
151static void open_abs(const char *path, abs_t *abs)
152{
153 abs->ops = SDL_RWFromFile(path, "rb");
154
155 if (abs->ops == NULL) {
156 fail("error while opening .abs file %s", path);
157 }
158
159 if (SDL_ReadBE16(abs->ops) != 0x601b) {
160 fail("invalid .abs file %s", path);
161 }
162
163 abs->text_len = SDL_ReadBE32(abs->ops);
164 abs->data_len = SDL_ReadBE32(abs->ops);
165 abs->bss_len = SDL_ReadBE32(abs->ops);
166
167 SDL_ReadBE32(abs->ops);
168 SDL_ReadBE32(abs->ops);
169
170 abs->text_loc = SDL_ReadBE32(abs->ops);
171
172 SDL_ReadBE16(abs->ops);
173
174 abs->data_loc = SDL_ReadBE32(abs->ops);
175 abs->bss_loc = SDL_ReadBE32(abs->ops);
176
177 inf("text 0x%x:0x%x data 0x%x:0x%x bss 0x%x:0x%x",
178 abs->text_loc, abs->text_len, abs->data_loc, abs->data_len, abs->bss_loc, abs->bss_len);
179
180 abs->load_len = (size_t)SDL_RWsize(abs->ops) - 36;
181}
182
183static void load_abs(const char *path, abs_t *abs, uint8_t *data)
184{
185 size_t loaded = 0;
186
187 while (loaded < abs->load_len) {
188 size_t n_rd = SDL_RWread(abs->ops, data + loaded, 1, abs->load_len - loaded);
189
190 if (n_rd == 0) {
191 fail("error while reading .abs file %s", path);
192 }
193
194 loaded += n_rd;
195 }
196
197 SDL_RWclose(abs->ops);
198}
199
200static void bios_init(void)
201{
202 inf("loading BIOS file %s", bios);
203
204 abs_t abs;
205 open_abs(bios, &abs);
206
207 if (abs.text_loc != ROM_START || abs.text_loc + abs.text_len != abs.data_loc ||
208 abs.load_len != abs.text_len + abs.data_len || abs.load_len > ROM_SIZE) {
209 fail("invalid BIOS file %s", bios);
210 }
211
212 load_abs(bios, &abs, rom_data);
213
214 rom_ro_beg = abs.text_loc;
215 rom_ro_end = abs.text_loc + abs.text_len + abs.data_len;
216 rom_rw_beg = abs.bss_loc;
217 rom_rw_end = abs.bss_loc + abs.bss_len;
218
219 ver("rom_ro_beg 0x%08x rom_ro_end 0x%08x", rom_ro_beg, rom_ro_end);
220 ver("rom_rw_beg 0x%08x rom_rw_end 0x%08x", rom_rw_beg, rom_rw_end);
221}
222
223static void midas_init(void)
224{
225 SDL_RWops *ops = SDL_RWFromFile(MIDAS_ABS, "rb");
226
227 if (ops == NULL) {
228 return;
229 }
230
231 SDL_RWclose(ops);
232
233 inf("loading MIDAS file " MIDAS_ABS);
234
235 abs_t abs;
236 open_abs(MIDAS_ABS, &abs);
237
238 if (abs.text_loc != APP_START ||
239 abs.text_loc + abs.text_len != abs.data_loc ||
240 abs.data_loc + abs.data_len != abs.bss_loc ||
241 abs.load_len != abs.text_len + abs.data_len ||
242 abs.bss_loc + abs.bss_len > RAM_SIZE) {
243 fail("invalid MIDAS file " MIDAS_ABS);
244 }
245
246 load_abs(MIDAS_ABS, &abs, ram_data + APP_START - RAM_START);
247
248 ram_ro_beg = ram_rw_beg = APP_START;
249 ram_ro_end = ram_rw_end = RAM_START + RAM_SIZE;
250}
251
252uint32_t m68k_read_disassembler_8(uint32_t addr)
253{
254 return m68k_read_memory_8(addr);
255}
256
257uint32_t m68k_read_disassembler_16(uint32_t addr)
258{
259 return m68k_read_memory_16(addr);
260}
261
262uint32_t m68k_read_disassembler_32(uint32_t addr)
263{
264 return m68k_read_memory_32(addr);
265}
266
267uint32_t m68k_read_memory_8(uint32_t addr)
268{
269 ver3("mem rd 0x%08x:8", addr);
270
271 if (addr >= ram_ro_beg && addr <= ram_ro_end - 1) {
272 return ram_data[addr - RAM_START];
273 }
274
275 if (addr >= ram_rw_beg && addr <= ram_rw_end - 1) {
276 return ram_data[addr - RAM_START];
277 }
278
279 if (addr >= rom_ro_beg && addr <= rom_ro_end - 1) {
280 return rom_data[addr - ROM_START];
281 }
282
283 if (addr >= rom_rw_beg && addr <= rom_rw_end - 1) {
284 // ROM has its BSS section in RAM.
285 return ram_data[addr - RAM_START];
286 }
287
288 hw_t *hw = hw_by_addr(addr);
289
290 if (hw != NULL) {
291 return hw->read(hw_off(hw, addr), 1);
292 }
293
294 if (addr <= APP_START - 1) {
295 return ram_data[addr];
296 }
297
298 fail("invalid read 0x%08x:8", addr);
299}
300
301uint32_t m68k_read_memory_16(uint32_t addr)
302{
303 ver3("mem rd 0x%08x:16", addr);
304
305 if (addr >= ram_ro_beg && addr <= ram_ro_end - 2) {
306 return
307 ((uint32_t)ram_data[addr - RAM_START + 0] << 8) |
308 ((uint32_t)ram_data[addr - RAM_START + 1] << 0);
309 }
310
311 if (addr >= ram_rw_beg && addr <= ram_rw_end - 2) {
312 return
313 ((uint32_t)ram_data[addr - RAM_START + 0] << 8) |
314 ((uint32_t)ram_data[addr - RAM_START + 1] << 0);
315 }
316
317 if (addr >= rom_ro_beg && addr <= rom_ro_end - 2) {
318 return
319 ((uint32_t)rom_data[addr - ROM_START + 0] << 8) |
320 ((uint32_t)rom_data[addr - ROM_START + 1] << 0);
321 }
322
323 if (addr >= rom_rw_beg && addr <= rom_rw_end - 2) {
324 // ROM has its BSS section in RAM.
325 return
326 ((uint32_t)ram_data[addr - RAM_START + 0] << 8) |
327 ((uint32_t)ram_data[addr - RAM_START + 1] << 0);
328 }
329
330 hw_t *hw = hw_by_addr(addr);
331
332 if (hw != NULL) {
333 return hw->read(hw_off(hw, addr), 2);
334 }
335
336 if (addr <= APP_START - 2) {
337 return
338 ((uint32_t)ram_data[addr + 0] << 8) |
339 ((uint32_t)ram_data[addr + 1] << 0);
340 }
341
342 fail("invalid read 0x%08x:16", addr);
343}
344
345uint32_t m68k_read_memory_32(uint32_t addr)
346{
347 ver3("mem rd 0x%08x:32", addr);
348
349 if (reset) {
350 if (addr == 0) {
351 addr += ROM_START;
352 }
353 else if (addr == 4) {
354 addr += ROM_START;
355 reset = false;
356 }
357 else {
358 fail("invalid reset sequence");
359 }
360 }
361
362 if (addr >= ram_ro_beg && addr <= ram_ro_end - 4) {
363 return
364 ((uint32_t)ram_data[addr - RAM_START + 0] << 24) |
365 ((uint32_t)ram_data[addr - RAM_START + 1] << 16) |
366 ((uint32_t)ram_data[addr - RAM_START + 2] << 8) |
367 ((uint32_t)ram_data[addr - RAM_START + 3] << 0);
368 }
369
370 if (addr >= ram_rw_beg && addr <= ram_rw_end - 4) {
371 return
372 ((uint32_t)ram_data[addr - RAM_START + 0] << 24) |
373 ((uint32_t)ram_data[addr - RAM_START + 1] << 16) |
374 ((uint32_t)ram_data[addr - RAM_START + 2] << 8) |
375 ((uint32_t)ram_data[addr - RAM_START + 3] << 0);
376 }
377
378 if (addr >= rom_ro_beg && addr <= rom_ro_end - 4) {
379 return
380 ((uint32_t)rom_data[addr - ROM_START + 0] << 24) |
381 ((uint32_t)rom_data[addr - ROM_START + 1] << 16) |
382 ((uint32_t)rom_data[addr - ROM_START + 2] << 8) |
383 ((uint32_t)rom_data[addr - ROM_START + 3] << 0);
384 }
385
386 if (addr >= rom_rw_beg && addr <= rom_rw_end - 4) {
387 // ROM has its BSS section in RAM.
388 return
389 ((uint32_t)ram_data[addr - RAM_START + 0] << 24) |
390 ((uint32_t)ram_data[addr - RAM_START + 1] << 16) |
391 ((uint32_t)ram_data[addr - RAM_START + 2] << 8) |
392 ((uint32_t)ram_data[addr - RAM_START + 3] << 0);
393 }
394
395 hw_t *hw = hw_by_addr(addr);
396
397 if (hw != NULL) {
398 return hw->read(hw_off(hw, addr), 4);
399 }
400
401 if (addr <= APP_START - 4) {
402 return
403 ((uint32_t)ram_data[addr + 0] << 24) |
404 ((uint32_t)ram_data[addr + 1] << 16) |
405 ((uint32_t)ram_data[addr + 2] << 8) |
406 ((uint32_t)ram_data[addr + 3] << 0);
407 }
408
409 fail("invalid read 0x%08x:32", addr);
410}
411
412void m68k_write_memory_8(uint32_t addr, uint32_t val)
413{
414 ver3("mem wr 0x%08x:8 0x%02x", addr, val);
415
416 if (addr >= ram_rw_beg && addr <= ram_rw_end - 1) {
417 ram_data[addr - RAM_START] = (uint8_t)val;
418 return;
419 }
420
421 if (addr >= rom_rw_beg && addr <= rom_rw_end - 1) {
422 // ROM has its BSS section in RAM.
423 ram_data[addr - RAM_START] = (uint8_t)val;
424 return;
425 }
426
427 hw_t *hw = hw_by_addr(addr);
428
429 if (hw != NULL) {
430 hw->write(hw_off(hw, addr), 1, val);
431 return;
432 }
433
434 if (addr <= APP_START - 1) {
435 ram_data[addr] = (uint8_t)val;
436 return;
437 }
438
439 // once midas.abs gets loaded, activate RAM
440
441 if (addr == APP_START) {
442 ram_data[addr] = (uint8_t)val;
443 ram_rw_beg = APP_START;
444 ram_rw_end = RAM_START + RAM_SIZE;
445 return;
446 }
447
448 fail("invalid write 0x%08x:8 0x%02x", addr, val);
449}
450
451void m68k_write_memory_16(uint32_t addr, uint32_t val)
452{
453 ver3("mem wr 0x%08x:16 0x%04x", addr, val);
454
455 if (addr >= ram_rw_beg && addr <= ram_rw_end - 2) {
456 ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 8);
457 ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 0);
458 return;
459 }
460
461 if (addr >= rom_rw_beg && addr <= rom_rw_end - 2) {
462 // ROM has its BSS section in RAM.
463 ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 8);
464 ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 0);
465 return;
466 }
467
468 hw_t *hw = hw_by_addr(addr);
469
470 if (hw != NULL) {
471 hw->write(hw_off(hw, addr), 2, val);
472 return;
473 }
474
475 if (addr <= APP_START - 2) {
476 ram_data[addr + 0] = (uint8_t)(val >> 8);
477 ram_data[addr + 1] = (uint8_t)(val >> 0);
478 return;
479 }
480
481 fail("invalid write 0x%08x:16 0x%04x", addr, val);
482}
483
484void m68k_write_memory_32(uint32_t addr, uint32_t val)
485{
486 ver3("mem wr 0x%08x:32 0x%08x", addr, val);
487
488 if (addr >= ram_rw_beg && addr <= ram_rw_end - 4) {
489 ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 24);
490 ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 16);
491 ram_data[addr - RAM_START + 2] = (uint8_t)(val >> 8);
492 ram_data[addr - RAM_START + 3] = (uint8_t)(val >> 0);
493 return;
494 }
495
496 if (addr >= rom_rw_beg && addr <= rom_rw_end - 4) {
497 // ROM has its BSS section in RAM.
498 ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 24);
499 ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 16);
500 ram_data[addr - RAM_START + 2] = (uint8_t)(val >> 8);
501 ram_data[addr - RAM_START + 3] = (uint8_t)(val >> 0);
502 return;
503 }
504
505 hw_t *hw = hw_by_addr(addr);
506
507 if (hw != NULL) {
508 hw->write(hw_off(hw, addr), 4, val);
509 return;
510 }
511
512 if (addr <= APP_START - 4) {
513 ram_data[addr + 0] = (uint8_t)(val >> 24);
514 ram_data[addr + 1] = (uint8_t)(val >> 16);
515 ram_data[addr + 2] = (uint8_t)(val >> 8);
516 ram_data[addr + 3] = (uint8_t)(val >> 0);
517 return;
518 }
519
520 fail("invalid write 0x%08x:32 0x%08x", addr, val);
521}
522
523uint8_t cpu_peek(int32_t addr)
524{
525 if (addr >= RAM_START && addr <= RAM_START + RAM_SIZE - 1) {
526 return ram_data[addr - RAM_START];
527 }
528
529 if (addr >= ROM_START && addr <= ROM_START + ROM_SIZE - 1) {
530 return rom_data[addr - ROM_START];
531 }
532
533 return 0;
534}
535
536void cpu_poke(int32_t addr, uint8_t val)
537{
538 if (addr >= RAM_START && addr <= RAM_START + RAM_SIZE - 1) {
539 ram_data[addr - RAM_START] = val;
540 }
541
542 if (addr >= ROM_START && addr <= ROM_START + ROM_SIZE - 1) {
543 rom_data[addr - ROM_START] = val;
544 }
545}
546
547static void inst_cb(void)
548{
549 uint32_t pc = m68k_get_reg(NULL, M68K_REG_PC);
550 uint32_t op = m68k_read_memory_16(pc);
551
552 gdb_inst(op == 0x4e4f);
553
554 if (op == 0x4e4d) {
555 uint32_t sp = m68k_get_reg(NULL, M68K_REG_SP);
556 uint32_t fun = m68k_read_memory_16(sp);
557
558 switch (fun) {
559 case 1:
560 ver2("BIOS B_RDAV %u", m68k_read_memory_16(sp + 2));
561 break;
562
563 case 2:
564 ver2("BIOS B_GETC %u", m68k_read_memory_16(sp + 2));
565 break;
566
567 case 3:
568 ver2("BIOS B_PUTC %u %u",
569 m68k_read_memory_16(sp + 2),
570 m68k_read_memory_16(sp + 4));
571 break;
572
573 case 4:
574 ver2("BIOS B_RDWR %u 0x%08x %u %u %u",
575 m68k_read_memory_16(sp + 2),
576 m68k_read_memory_32(sp + 4),
577 m68k_read_memory_16(sp + 8),
578 m68k_read_memory_16(sp + 10),
579 m68k_read_memory_16(sp + 12));
580 break;
581
582 case 5:
583 ver2("BIOS B_SETV %u 0x%08x",
584 m68k_read_memory_16(sp + 2),
585 m68k_read_memory_32(sp + 4));
586 break;
587
588 case 7:
589 ver2("BIOS B_GBPB %u", m68k_read_memory_16(sp + 2));
590 break;
591
592 case 8:
593 ver2("BIOS B_THRE %u", m68k_read_memory_16(sp + 2));
594 break;
595
596 case 9:
597 ver2("BIOS B_MCHG %u", m68k_read_memory_16(sp + 2));
598 break;
599
600 case 10:
601 ver2("BIOS B_DMAP");
602 break;
603
604 default:
605 fail("invalid function: BIOS %d", fun);
606 }
607 }
608 else if (op == 0x4e4e) {
609 uint32_t sp = m68k_get_reg(NULL, M68K_REG_SP);
610 uint32_t fun = m68k_read_memory_16(sp);
611
612 switch (fun) {
613 case 0:
614 ver2("XBIOS X_PIOREC %u", m68k_read_memory_16(sp + 2));
615 break;
616
617 case 1:
618 ver2("XBIOS X_SETPRT %u 0x%02x 0x%02x 0x%02x 0x%02x",
619 m68k_read_memory_16(sp + 2),
620 m68k_read_memory_16(sp + 4),
621 m68k_read_memory_16(sp + 6),
622 m68k_read_memory_16(sp + 8),
623 m68k_read_memory_16(sp + 10));
624 break;
625
626 case 2:
627 ver2("XBIOS X_FLOPRD 0x%08x 0x%08x %u %u %u %u %u",
628 m68k_read_memory_32(sp + 2),
629 m68k_read_memory_32(sp + 6),
630 m68k_read_memory_16(sp + 10),
631 m68k_read_memory_16(sp + 12),
632 m68k_read_memory_16(sp + 14),
633 m68k_read_memory_16(sp + 16),
634 m68k_read_memory_16(sp + 18));
635 break;
636
637 case 3:
638 ver2("XBIOS X_FLOPWR 0x%08x 0x%08x %u %u %u %u %u",
639 m68k_read_memory_32(sp + 2),
640 m68k_read_memory_32(sp + 6),
641 m68k_read_memory_16(sp + 10),
642 m68k_read_memory_16(sp + 12),
643 m68k_read_memory_16(sp + 14),
644 m68k_read_memory_16(sp + 16),
645 m68k_read_memory_16(sp + 18));
646 break;
647
648 case 4:
649 ver2("XBIOS X_FORMAT 0x%08x 0x%08x %u %u %u %u %u 0x%08x %u",
650 m68k_read_memory_32(sp + 2),
651 m68k_read_memory_32(sp + 6),
652 m68k_read_memory_16(sp + 10),
653 m68k_read_memory_16(sp + 12),
654 m68k_read_memory_16(sp + 14),
655 m68k_read_memory_16(sp + 16),
656 m68k_read_memory_16(sp + 18),
657 m68k_read_memory_32(sp + 20),
658 m68k_read_memory_16(sp + 24));
659 break;
660
661 case 5:
662 ver2("XBIOS X_VERIFY 0x%08x 0x%08x %u %u %u %u %u",
663 m68k_read_memory_32(sp + 2),
664 m68k_read_memory_32(sp + 6),
665 m68k_read_memory_16(sp + 10),
666 m68k_read_memory_16(sp + 12),
667 m68k_read_memory_16(sp + 14),
668 m68k_read_memory_16(sp + 16),
669 m68k_read_memory_16(sp + 18));
670 break;
671
672 case 6:
673 ver2("XBIOS X_PRBOOT 0x%08x %u %u %u",
674 m68k_read_memory_32(sp + 2),
675 m68k_read_memory_16(sp + 6),
676 m68k_read_memory_16(sp + 8),
677 m68k_read_memory_16(sp + 10));
678 break;
679
680 case 7:
681 ver2("XBIOS X_RANDOM");
682 break;
683
684 case 8:
685 ver2("XBIOS X_ANALOG");
686 break;
687
688 case 9:
689 ver2("XBIOS X_CLRAFI");
690 break;
691
692 case 10:
693 ver2("XBIOS X_APICHK");
694 break;
695
696 case 11:
697 ver2("XBIOS X_MTDEFS ");
698 break;
699
700 default:
701 fail("invalid function: XBIOS %d", fun);
702 }
703 }
704}
705
706void cpu_init(void)
707{
708 cpu_mutex = SDL_CreateMutex();
709
710 if (cpu_mutex == NULL) {
711 fail("SDL_CreateMutex() failed: %s", SDL_GetError());
712 }
713
714 freq = SDL_GetPerformanceFrequency();
715 quan = freq / PER_SEC;
716
717 inf("freq %" PRIu64 " quan %" PRIu64, freq, quan);
718
719 hw_init();
720 bios_init();
721 midas_init();
722
723 m68k_init();
724 m68k_set_cpu_type(M68K_CPU_TYPE_68000);
725 m68k_set_instr_hook_callback(inst_cb);
726 m68k_pulse_reset();
727}
728
729void cpu_quit(void)
730{
731 hw_quit();
732 SDL_DestroyMutex(cpu_mutex);
733}
734
735void cpu_loop(void)
736{
737 inf("entering CPU loop");
738 int32_t count = 0;
739
740 while (SDL_AtomicGet(&run) != 0) {
741 uint64_t until = SDL_GetPerformanceCounter() + quan;
742
743 if (SDL_LockMutex(cpu_mutex) < 0) {
744 fail("SDL_LockMutex() failed: %s", SDL_GetError());
745 }
746
747 m68k_execute(CPU_FREQ / PER_SEC);
748 uint32_t irq = hw_exec();
749
750 if (irq > 0) {
751 ver2("irq %u", irq);
752 }
753
754 m68k_set_irq(irq);
755
756 if (SDL_UnlockMutex(cpu_mutex) < 0) {
757 fail("SDL_UnlockMutex() failed: %s", SDL_GetError());
758 }
759
760 if ((++count & 0x1ff) == 0) {
761 SDL_Delay(0);
762 }
763
764 while (SDL_GetPerformanceCounter() < until) {
765 for (int32_t i = 0; i < 100; ++i) {
766 _mm_pause();
767 }
768 }
769 }
770
771 inf("leaving CPU loop");
772}
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