source: buchla-emu/emu/cpu.c@ c1c1ca5

Last change on this file since c1c1ca5 was ac4e192, checked in by Thomas Lopatic <thomas@…>, 8 years ago

Started VSDD emulation.
  • Property mode set to 100644
File size: 16.3 KB
Line 
1/*
2 * Copyright (C) 2017 The Contributors
3 *
4 * This program is free software: you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation, either version 3 of the License, or (at
7 * your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
13 *
14 * A copy of the GNU General Public License can be found in the file
15 * "gpl.txt" in the top directory of this repository.
16 */
17
18#include <all.h>
19
20#define ver(...) _ver(cpu_verbose, 0, __VA_ARGS__)
21#define ver2(...) _ver(cpu_verbose, 1, __VA_ARGS__)
22#define ver3(...) _ver(cpu_verbose, 2, __VA_ARGS__)
23
24int32_t cpu_verbose = 0;
25
26#define CPU_FREQ 7000000
27#define PER_SEC 100000
28
29#define APP_START 0x10000
30
31#define RAM_START 0x0
32#define RAM_SIZE 0x100000
33
34#define ROM_START 0x100000
35#define ROM_SIZE 0x10000
36
37typedef void (*hw_init_t)(void);
38typedef void (*hw_quit_t)(void);
39typedef bool (*hw_exec_t)(void);
40typedef uint32_t (*hw_read_t)(uint32_t off, int32_t sz);
41typedef void (*hw_write_t)(uint32_t off, int32_t sz, uint32_t val);
42
43typedef struct {
44 uint32_t addr_beg;
45 uint32_t addr_end;
46 uint32_t irq;
47 hw_init_t init;
48 hw_quit_t quit;
49 hw_exec_t exec;
50 hw_read_t read;
51 hw_write_t write;
52} hw_t;
53
54static uint64_t freq;
55static uint64_t quan;
56
57SDL_mutex *cpu_mutex;
58
59static bool reset = true;
60
61static uint8_t ram_data[RAM_SIZE];
62static uint8_t rom_data[ROM_SIZE];
63
64static uint32_t ram_ro_beg = 0x1234;
65static uint32_t ram_ro_end = 0x1234;
66static uint32_t ram_rw_beg = 0x1234;
67static uint32_t ram_rw_end = 0x1234;
68
69static uint32_t rom_ro_beg;
70static uint32_t rom_ro_end;
71static uint32_t rom_rw_beg;
72static uint32_t rom_rw_end;
73
74static hw_t hw_map[] = {
75 { 0x180000, 0x200000, 0, fpu_init, fpu_quit, fpu_exec, fpu_read, fpu_write },
76 { 0x200000, 0x280002, 1, vid_init, vid_quit, vid_exec, vid_read, vid_write },
77 { 0x3a0001, 0x3a4001, 4, tim_init, tim_quit, tim_exec, tim_read, tim_write },
78 { 0x3a4001, 0x3a8001, 0, lcd_init, lcd_quit, lcd_exec, lcd_read, lcd_write },
79 { 0x3a8001, 0x3ac001, 5, ser_init, ser_quit, ser_exec, ser_read, ser_write },
80 { 0x3ac001, 0x3b0001, 0, mid_init, mid_quit, mid_exec, mid_read, mid_write },
81 { 0x3b0001, 0x3b4001, 0, fdd_init, fdd_quit, fdd_exec, fdd_read, fdd_write },
82 { 0x3b4001, 0x3b8001, 0, snd_init, snd_quit, snd_exec, snd_read, snd_write },
83 { 0x3b8001, 0x3bc001, 0, led_init, led_quit, led_exec, led_read, led_write },
84 { 0x3bc001, 0x3c0001, 0, kbd_init, kbd_quit, kbd_exec, kbd_read, kbd_write }
85};
86
87static hw_t *hw_by_addr(uint32_t addr)
88{
89 for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
90 if (addr >= hw_map[i].addr_beg && addr < hw_map[i].addr_end) {
91 return hw_map + i;
92 }
93 }
94
95 return NULL;
96}
97
98static void hw_init(void)
99{
100 inf("starting hardware");
101
102 for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
103 hw_map[i].init();
104 }
105}
106
107static void hw_quit(void)
108{
109 inf("halting hardware");
110
111 for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
112 hw_map[i].quit();
113 }
114}
115
116static uint32_t hw_exec(void)
117{
118 uint32_t irq = 0;
119
120 for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
121 if (hw_map[i].exec() && hw_map[i].irq > irq) {
122 irq = hw_map[i].irq;
123 }
124 }
125
126 return irq;
127}
128
129static uint32_t hw_off(hw_t *hw, uint32_t addr)
130{
131 if ((hw->addr_beg & 0x1) == 0) {
132 return addr - hw->addr_beg;
133 }
134
135 return (addr - hw->addr_beg) / 2;
136}
137
138static void bios_init(void)
139{
140 inf("loading BIOS file %s", bios);
141
142 SDL_RWops *ops = SDL_RWFromFile(bios, "rb");
143
144 if (ops == NULL) {
145 fail("error while opening BIOS file %s", bios);
146 }
147
148 if (SDL_ReadBE16(ops) != 0x601b) {
149 fail("invalid BIOS file %s", bios);
150 }
151
152 uint32_t text_len = SDL_ReadBE32(ops);
153 uint32_t data_len = SDL_ReadBE32(ops);
154 uint32_t bss_len = SDL_ReadBE32(ops);
155
156 SDL_ReadBE32(ops);
157 SDL_ReadBE32(ops);
158
159 uint32_t text_loc = SDL_ReadBE32(ops);
160
161 SDL_ReadBE16(ops);
162
163 uint32_t data_loc = SDL_ReadBE32(ops);
164 uint32_t bss_loc = SDL_ReadBE32(ops);
165
166 inf("BIOS text 0x%x:0x%x data 0x%x:0x%x bss 0x%x:0x%x",
167 text_loc, text_len, data_loc, data_len, bss_loc, bss_len);
168
169 size_t load_len = (size_t)SDL_RWsize(ops) - 36;
170
171 if (text_loc != ROM_START || text_loc + text_len != data_loc ||
172 load_len != text_len + data_len || load_len > ROM_SIZE) {
173 fail("invalid BIOS file %s", bios);
174 }
175
176 size_t loaded = 0;
177
178 while (loaded < load_len) {
179 size_t n_rd = SDL_RWread(ops, rom_data + loaded, 1, load_len - loaded);
180
181 if (n_rd == 0) {
182 fail("error while reading BIOS file %s", bios);
183 }
184
185 loaded += n_rd;
186 }
187
188 SDL_RWclose(ops);
189
190 rom_ro_beg = text_loc;
191 rom_ro_end = text_loc + text_len + data_len;
192 rom_rw_beg = bss_loc;
193 rom_rw_end = bss_loc + bss_len;
194
195 ver("rom_ro_beg 0x%08x rom_ro_end 0x%08x", rom_ro_beg, rom_ro_end);
196 ver("rom_rw_beg 0x%08x rom_rw_end 0x%08x", rom_rw_beg, rom_rw_end);
197}
198
199uint32_t m68k_read_disassembler_8(uint32_t addr)
200{
201 return m68k_read_memory_8(addr);
202}
203
204uint32_t m68k_read_disassembler_16(uint32_t addr)
205{
206 return m68k_read_memory_16(addr);
207}
208
209uint32_t m68k_read_disassembler_32(uint32_t addr)
210{
211 return m68k_read_memory_32(addr);
212}
213
214uint32_t m68k_read_memory_8(uint32_t addr)
215{
216 ver3("mem rd 0x%08x:8", addr);
217
218 if (addr >= ram_ro_beg && addr <= ram_ro_end - 1) {
219 return ram_data[addr - RAM_START];
220 }
221
222 if (addr >= ram_rw_beg && addr <= ram_rw_end - 1) {
223 return ram_data[addr - RAM_START];
224 }
225
226 if (addr >= rom_ro_beg && addr <= rom_ro_end - 1) {
227 return rom_data[addr - ROM_START];
228 }
229
230 if (addr >= rom_rw_beg && addr <= rom_rw_end - 1) {
231 // ROM has its BSS section in RAM.
232 return ram_data[addr - RAM_START];
233 }
234
235 hw_t *hw = hw_by_addr(addr);
236
237 if (hw != NULL) {
238 return hw->read(hw_off(hw, addr), 1);
239 }
240
241 if (addr <= APP_START - 1) {
242 return ram_data[addr];
243 }
244
245 fail("invalid read 0x%08x:8", addr);
246}
247
248uint32_t m68k_read_memory_16(uint32_t addr)
249{
250 ver3("mem rd 0x%08x:16", addr);
251
252 if (addr >= ram_ro_beg && addr <= ram_ro_end - 2) {
253 return
254 ((uint32_t)ram_data[addr - RAM_START + 0] << 8) |
255 ((uint32_t)ram_data[addr - RAM_START + 1] << 0);
256 }
257
258 if (addr >= ram_rw_beg && addr <= ram_rw_end - 2) {
259 return
260 ((uint32_t)ram_data[addr - RAM_START + 0] << 8) |
261 ((uint32_t)ram_data[addr - RAM_START + 1] << 0);
262 }
263
264 if (addr >= rom_ro_beg && addr <= rom_ro_end - 2) {
265 return
266 ((uint32_t)rom_data[addr - ROM_START + 0] << 8) |
267 ((uint32_t)rom_data[addr - ROM_START + 1] << 0);
268 }
269
270 if (addr >= rom_rw_beg && addr <= rom_rw_end - 2) {
271 // ROM has its BSS section in RAM.
272 return
273 ((uint32_t)ram_data[addr - RAM_START + 0] << 8) |
274 ((uint32_t)ram_data[addr - RAM_START + 1] << 0);
275 }
276
277 hw_t *hw = hw_by_addr(addr);
278
279 if (hw != NULL) {
280 return hw->read(hw_off(hw, addr), 2);
281 }
282
283 if (addr <= APP_START - 2) {
284 return
285 ((uint32_t)ram_data[addr + 0] << 8) |
286 ((uint32_t)ram_data[addr + 1] << 0);
287 }
288
289 fail("invalid read 0x%08x:16", addr);
290}
291
292uint32_t m68k_read_memory_32(uint32_t addr)
293{
294 ver3("mem rd 0x%08x:32", addr);
295
296 if (reset) {
297 if (addr == 0) {
298 addr += ROM_START;
299 }
300 else if (addr == 4) {
301 addr += ROM_START;
302 reset = false;
303 }
304 else {
305 fail("invalid reset sequence");
306 }
307 }
308
309 if (addr >= ram_ro_beg && addr <= ram_ro_end - 4) {
310 return
311 ((uint32_t)ram_data[addr - RAM_START + 0] << 24) |
312 ((uint32_t)ram_data[addr - RAM_START + 1] << 16) |
313 ((uint32_t)ram_data[addr - RAM_START + 2] << 8) |
314 ((uint32_t)ram_data[addr - RAM_START + 3] << 0);
315 }
316
317 if (addr >= ram_rw_beg && addr <= ram_rw_end - 4) {
318 return
319 ((uint32_t)ram_data[addr - RAM_START + 0] << 24) |
320 ((uint32_t)ram_data[addr - RAM_START + 1] << 16) |
321 ((uint32_t)ram_data[addr - RAM_START + 2] << 8) |
322 ((uint32_t)ram_data[addr - RAM_START + 3] << 0);
323 }
324
325 if (addr >= rom_ro_beg && addr <= rom_ro_end - 4) {
326 return
327 ((uint32_t)rom_data[addr - ROM_START + 0] << 24) |
328 ((uint32_t)rom_data[addr - ROM_START + 1] << 16) |
329 ((uint32_t)rom_data[addr - ROM_START + 2] << 8) |
330 ((uint32_t)rom_data[addr - ROM_START + 3] << 0);
331 }
332
333 if (addr >= rom_rw_beg && addr <= rom_rw_end - 4) {
334 // ROM has its BSS section in RAM.
335 return
336 ((uint32_t)ram_data[addr - RAM_START + 0] << 24) |
337 ((uint32_t)ram_data[addr - RAM_START + 1] << 16) |
338 ((uint32_t)ram_data[addr - RAM_START + 2] << 8) |
339 ((uint32_t)ram_data[addr - RAM_START + 3] << 0);
340 }
341
342 hw_t *hw = hw_by_addr(addr);
343
344 if (hw != NULL) {
345 return hw->read(hw_off(hw, addr), 4);
346 }
347
348 if (addr <= APP_START - 4) {
349 return
350 ((uint32_t)ram_data[addr + 0] << 24) |
351 ((uint32_t)ram_data[addr + 1] << 16) |
352 ((uint32_t)ram_data[addr + 2] << 8) |
353 ((uint32_t)ram_data[addr + 3] << 0);
354 }
355
356 fail("invalid read 0x%08x:32", addr);
357}
358
359void m68k_write_memory_8(uint32_t addr, uint32_t val)
360{
361 ver3("mem wr 0x%08x:8 0x%02x", addr, val);
362
363 if (addr >= ram_rw_beg && addr <= ram_rw_end - 1) {
364 ram_data[addr - RAM_START] = (uint8_t)val;
365 return;
366 }
367
368 if (addr >= rom_rw_beg && addr <= rom_rw_end - 1) {
369 // ROM has its BSS section in RAM.
370 ram_data[addr - RAM_START] = (uint8_t)val;
371 return;
372 }
373
374 hw_t *hw = hw_by_addr(addr);
375
376 if (hw != NULL) {
377 hw->write(hw_off(hw, addr), 1, val);
378 return;
379 }
380
381 if (addr <= APP_START - 1) {
382 ram_data[addr] = (uint8_t)val;
383 return;
384 }
385
386 // once midas.abs gets loaded, activate RAM
387
388 if (addr == APP_START) {
389 ram_data[addr] = (uint8_t)val;
390 ram_rw_beg = APP_START;
391 ram_rw_end = RAM_START + RAM_SIZE;
392 return;
393 }
394
395 fail("invalid write 0x%08x:8 0x%02x", addr, val);
396}
397
398void m68k_write_memory_16(uint32_t addr, uint32_t val)
399{
400 ver3("mem wr 0x%08x:16 0x%04x", addr, val);
401
402 if (addr >= ram_rw_beg && addr <= ram_rw_end - 2) {
403 ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 8);
404 ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 0);
405 return;
406 }
407
408 if (addr >= rom_rw_beg && addr <= rom_rw_end - 2) {
409 // ROM has its BSS section in RAM.
410 ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 8);
411 ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 0);
412 return;
413 }
414
415 hw_t *hw = hw_by_addr(addr);
416
417 if (hw != NULL) {
418 hw->write(hw_off(hw, addr), 2, val);
419 return;
420 }
421
422 if (addr <= APP_START - 2) {
423 ram_data[addr + 0] = (uint8_t)(val >> 8);
424 ram_data[addr + 1] = (uint8_t)(val >> 0);
425 return;
426 }
427
428 fail("invalid write 0x%08x:16 0x%04x", addr, val);
429}
430
431void m68k_write_memory_32(uint32_t addr, uint32_t val)
432{
433 ver3("mem wr 0x%08x:32 0x%08x", addr, val);
434
435 if (addr >= ram_rw_beg && addr <= ram_rw_end - 4) {
436 ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 24);
437 ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 16);
438 ram_data[addr - RAM_START + 2] = (uint8_t)(val >> 8);
439 ram_data[addr - RAM_START + 3] = (uint8_t)(val >> 0);
440 return;
441 }
442
443 if (addr >= rom_rw_beg && addr <= rom_rw_end - 4) {
444 // ROM has its BSS section in RAM.
445 ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 24);
446 ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 16);
447 ram_data[addr - RAM_START + 2] = (uint8_t)(val >> 8);
448 ram_data[addr - RAM_START + 3] = (uint8_t)(val >> 0);
449 return;
450 }
451
452 hw_t *hw = hw_by_addr(addr);
453
454 if (hw != NULL) {
455 hw->write(hw_off(hw, addr), 4, val);
456 return;
457 }
458
459 if (addr <= APP_START - 4) {
460 ram_data[addr + 0] = (uint8_t)(val >> 24);
461 ram_data[addr + 1] = (uint8_t)(val >> 16);
462 ram_data[addr + 2] = (uint8_t)(val >> 8);
463 ram_data[addr + 3] = (uint8_t)(val >> 0);
464 return;
465 }
466
467 fail("invalid write 0x%08x:32 0x%08x", addr, val);
468}
469
470uint8_t cpu_peek(int32_t addr)
471{
472 if (addr >= RAM_START && addr <= RAM_START + RAM_SIZE - 1) {
473 return ram_data[addr - RAM_START];
474 }
475
476 if (addr >= ROM_START && addr <= ROM_START + ROM_SIZE - 1) {
477 return rom_data[addr - ROM_START];
478 }
479
480 return 0;
481}
482
483void cpu_poke(int32_t addr, uint8_t val)
484{
485 if (addr >= RAM_START && addr <= RAM_START + RAM_SIZE - 1) {
486 ram_data[addr - RAM_START] = val;
487 }
488
489 if (addr >= ROM_START && addr <= ROM_START + ROM_SIZE - 1) {
490 rom_data[addr - ROM_START] = val;
491 }
492}
493
494static void inst_cb(void)
495{
496 uint32_t pc = m68k_get_reg(NULL, M68K_REG_PC);
497 uint32_t op = m68k_read_memory_16(pc);
498
499 gdb_inst(op == 0x4e4f);
500
501 if (op == 0x4e4d) {
502 uint32_t sp = m68k_get_reg(NULL, M68K_REG_SP);
503 uint32_t fun = m68k_read_memory_16(sp);
504
505 switch (fun) {
506 case 1:
507 ver2("BIOS B_RDAV %u", m68k_read_memory_16(sp + 2));
508 break;
509
510 case 2:
511 ver2("BIOS B_GETC %u", m68k_read_memory_16(sp + 2));
512 break;
513
514 case 3:
515 ver2("BIOS B_PUTC %u %u",
516 m68k_read_memory_16(sp + 2),
517 m68k_read_memory_16(sp + 4));
518 break;
519
520 case 4:
521 ver2("BIOS B_RDWR %u 0x%08x %u %u %u",
522 m68k_read_memory_16(sp + 2),
523 m68k_read_memory_32(sp + 4),
524 m68k_read_memory_16(sp + 8),
525 m68k_read_memory_16(sp + 10),
526 m68k_read_memory_16(sp + 12));
527 break;
528
529 case 5:
530 ver2("BIOS B_SETV %u 0x%08x",
531 m68k_read_memory_16(sp + 2),
532 m68k_read_memory_32(sp + 4));
533 break;
534
535 case 7:
536 ver2("BIOS B_GBPB %u", m68k_read_memory_16(sp + 2));
537 break;
538
539 case 8:
540 ver2("BIOS B_THRE %u", m68k_read_memory_16(sp + 2));
541 break;
542
543 case 9:
544 ver2("BIOS B_MCHG %u", m68k_read_memory_16(sp + 2));
545 break;
546
547 case 10:
548 ver2("BIOS B_DMAP");
549 break;
550
551 default:
552 fail("invalid function: BIOS %d", fun);
553 }
554 }
555 else if (op == 0x4e4e) {
556 uint32_t sp = m68k_get_reg(NULL, M68K_REG_SP);
557 uint32_t fun = m68k_read_memory_16(sp);
558
559 switch (fun) {
560 case 0:
561 ver2("XBIOS X_PIOREC %u", m68k_read_memory_16(sp + 2));
562 break;
563
564 case 1:
565 ver2("XBIOS X_SETPRT %u 0x%02x 0x%02x 0x%02x 0x%02x",
566 m68k_read_memory_16(sp + 2),
567 m68k_read_memory_16(sp + 4),
568 m68k_read_memory_16(sp + 6),
569 m68k_read_memory_16(sp + 8),
570 m68k_read_memory_16(sp + 10));
571 break;
572
573 case 2:
574 ver2("XBIOS X_FLOPRD 0x%08x 0x%08x %u %u %u %u %u",
575 m68k_read_memory_32(sp + 2),
576 m68k_read_memory_32(sp + 6),
577 m68k_read_memory_16(sp + 10),
578 m68k_read_memory_16(sp + 12),
579 m68k_read_memory_16(sp + 14),
580 m68k_read_memory_16(sp + 16),
581 m68k_read_memory_16(sp + 18));
582 break;
583
584 case 3:
585 ver2("XBIOS X_FLOPWR 0x%08x 0x%08x %u %u %u %u %u",
586 m68k_read_memory_32(sp + 2),
587 m68k_read_memory_32(sp + 6),
588 m68k_read_memory_16(sp + 10),
589 m68k_read_memory_16(sp + 12),
590 m68k_read_memory_16(sp + 14),
591 m68k_read_memory_16(sp + 16),
592 m68k_read_memory_16(sp + 18));
593 break;
594
595 case 4:
596 ver2("XBIOS X_FORMAT 0x%08x 0x%08x %u %u %u %u %u 0x%08x %u",
597 m68k_read_memory_32(sp + 2),
598 m68k_read_memory_32(sp + 6),
599 m68k_read_memory_16(sp + 10),
600 m68k_read_memory_16(sp + 12),
601 m68k_read_memory_16(sp + 14),
602 m68k_read_memory_16(sp + 16),
603 m68k_read_memory_16(sp + 18),
604 m68k_read_memory_32(sp + 20),
605 m68k_read_memory_16(sp + 24));
606 break;
607
608 case 5:
609 ver2("XBIOS X_VERIFY 0x%08x 0x%08x %u %u %u %u %u",
610 m68k_read_memory_32(sp + 2),
611 m68k_read_memory_32(sp + 6),
612 m68k_read_memory_16(sp + 10),
613 m68k_read_memory_16(sp + 12),
614 m68k_read_memory_16(sp + 14),
615 m68k_read_memory_16(sp + 16),
616 m68k_read_memory_16(sp + 18));
617 break;
618
619 case 6:
620 ver2("XBIOS X_PRBOOT 0x%08x %u %u %u",
621 m68k_read_memory_32(sp + 2),
622 m68k_read_memory_16(sp + 6),
623 m68k_read_memory_16(sp + 8),
624 m68k_read_memory_16(sp + 10));
625 break;
626
627 case 7:
628 ver2("XBIOS X_RANDOM");
629 break;
630
631 case 8:
632 ver2("XBIOS X_ANALOG");
633 break;
634
635 case 9:
636 ver2("XBIOS X_CLRAFI");
637 break;
638
639 case 10:
640 ver2("XBIOS X_APICHK");
641 break;
642
643 case 11:
644 ver2("XBIOS X_MTDEFS ");
645 break;
646
647 default:
648 fail("invalid function: XBIOS %d", fun);
649 }
650 }
651}
652
653void cpu_init(void)
654{
655 cpu_mutex = SDL_CreateMutex();
656
657 if (cpu_mutex == NULL) {
658 fail("SDL_CreateMutex() failed: %s", SDL_GetError());
659 }
660
661 freq = SDL_GetPerformanceFrequency();
662 quan = freq / PER_SEC;
663
664 inf("freq %" PRIu64 " quan %" PRIu64, freq, quan);
665
666 hw_init();
667 bios_init();
668
669 m68k_init();
670 m68k_set_cpu_type(M68K_CPU_TYPE_68000);
671 m68k_set_instr_hook_callback(inst_cb);
672 m68k_pulse_reset();
673}
674
675void cpu_quit(void)
676{
677 hw_quit();
678 SDL_DestroyMutex(cpu_mutex);
679}
680
681void cpu_loop(void)
682{
683 inf("entering CPU loop");
684 int32_t count = 0;
685
686 while (SDL_AtomicGet(&run) != 0) {
687 uint64_t until = SDL_GetPerformanceCounter() + quan;
688
689 if (SDL_LockMutex(cpu_mutex) < 0) {
690 fail("SDL_LockMutex() failed: %s", SDL_GetError());
691 }
692
693 m68k_execute(CPU_FREQ / PER_SEC);
694 uint32_t irq = hw_exec();
695
696 if (irq > 0) {
697 ver2("irq %u", irq);
698 }
699
700 m68k_set_irq(irq);
701
702 if (SDL_UnlockMutex(cpu_mutex) < 0) {
703 fail("SDL_UnlockMutex() failed: %s", SDL_GetError());
704 }
705
706 if ((++count & 0x1ff) == 0) {
707 SDL_Delay(0);
708 }
709
710 while (SDL_GetPerformanceCounter() < until) {
711 for (int32_t i = 0; i < 100; ++i) {
712 _mm_pause();
713 }
714 }
715 }
716
717 inf("leaving CPU loop");
718}
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