source: buchla-emu/emu/cpu.c@ 7eb8971

Last change on this file since 7eb8971 was 7eb8971, checked in by Thomas Lopatic <thomas@…>, 7 years ago

Don't use Linux fix on OS X.
  • Property mode set to 100644
File size: 15.6 KB
Line 
1/*
2 * Copyright (C) 2017 The Contributors
3 *
4 * This program is free software: you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation, either version 3 of the License, or (at
7 * your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
13 *
14 * A copy of the GNU General Public License can be found in the file
15 * "gpl.txt" in the top directory of this repository.
16 */
17
18#include <all.h>
19
20#define ver(...) _ver(cpu_verbose, 0, __VA_ARGS__)
21#define ver2(...) _ver(cpu_verbose, 1, __VA_ARGS__)
22#define ver3(...) _ver(cpu_verbose, 2, __VA_ARGS__)
23
24int32_t cpu_verbose = 0;
25
26#define CPU_FREQ 7000000
27#define PER_SEC 100000
28
29#define APP_START 0x10000
30
31#define RAM_START 0x0
32#define RAM_SIZE 0x100000
33
34#define ROM_START 0x100000
35#define ROM_SIZE 0x10000
36
37typedef void (*hw_init_t)(void);
38typedef void (*hw_quit_t)(void);
39typedef void (*hw_exec_t)(void);
40typedef uint32_t (*hw_read_t)(uint32_t off, int32_t sz);
41typedef void (*hw_write_t)(uint32_t off, int32_t sz, uint32_t val);
42
43typedef struct {
44 uint32_t addr_beg;
45 uint32_t addr_end;
46 hw_init_t init;
47 hw_quit_t quit;
48 hw_exec_t exec;
49 hw_read_t read;
50 hw_write_t write;
51} hw_t;
52
53static bool reset = true;
54
55static uint8_t ram_data[RAM_SIZE];
56static uint8_t rom_data[ROM_SIZE];
57
58static uint32_t ram_ro_beg = 0x1234;
59static uint32_t ram_ro_end = 0x1234;
60static uint32_t ram_rw_beg = 0x1234;
61static uint32_t ram_rw_end = 0x1234;
62
63static uint32_t rom_ro_beg;
64static uint32_t rom_ro_end;
65static uint32_t rom_rw_beg;
66static uint32_t rom_rw_end;
67
68static hw_t hw_map[] = {
69 { 0x180000, 0x200000, fpu_init, fpu_quit, fpu_exec, fpu_read, fpu_write },
70 { 0x200000, 0x280000, vid_init, vid_quit, vid_exec, vid_read, vid_write },
71 { 0x3a0001, 0x3a4001, tim_init, tim_quit, tim_exec, tim_read, tim_write },
72 { 0x3a4001, 0x3a8001, lcd_init, lcd_quit, lcd_exec, lcd_read, lcd_write },
73 { 0x3a8001, 0x3ac001, ser_init, ser_quit, ser_exec, ser_read, ser_write },
74 { 0x3ac001, 0x3b0001, mid_init, mid_quit, mid_exec, mid_read, mid_write },
75 { 0x3b0001, 0x3b4001, fdd_init, fdd_quit, fdd_exec, fdd_read, fdd_write },
76 { 0x3b4001, 0x3b8001, snd_init, snd_quit, snd_exec, snd_read, snd_write },
77 { 0x3b8001, 0x3bc001, led_init, led_quit, led_exec, led_read, led_write },
78 { 0x3bc001, 0x3c0001, kbd_init, kbd_quit, kbd_exec, kbd_read, kbd_write }
79};
80
81static hw_t *hw_by_addr(uint32_t addr)
82{
83 for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
84 if (addr >= hw_map[i].addr_beg && addr < hw_map[i].addr_end) {
85 return hw_map + i;
86 }
87 }
88
89 return NULL;
90}
91
92static void hw_init(void)
93{
94 inf("starting hardware");
95
96 for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
97 hw_map[i].init();
98 }
99}
100
101static void hw_quit(void)
102{
103 inf("halting hardware");
104
105 for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
106 hw_map[i].quit();
107 }
108}
109
110static void hw_exec(void)
111{
112 for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
113 hw_map[i].exec();
114 }
115}
116
117static uint32_t hw_off(hw_t *hw, uint32_t addr)
118{
119 if ((hw->addr_beg & 0x1) == 0) {
120 return addr - hw->addr_beg;
121 }
122
123 return (addr - hw->addr_beg) / 2;
124}
125
126static void bios_init(const char *bios)
127{
128 inf("loading BIOS file %s", bios);
129
130 SDL_RWops *ops = SDL_RWFromFile(bios, "rb");
131
132 if (ops == NULL) {
133 fail("error while opening BIOS file %s", bios);
134 }
135
136 if (SDL_ReadBE16(ops) != 0x601b) {
137 fail("invalid BIOS file %s", bios);
138 }
139
140 uint32_t text_len = SDL_ReadBE32(ops);
141 uint32_t data_len = SDL_ReadBE32(ops);
142 uint32_t bss_len = SDL_ReadBE32(ops);
143
144 SDL_ReadBE32(ops);
145 SDL_ReadBE32(ops);
146
147 uint32_t text_loc = SDL_ReadBE32(ops);
148
149 SDL_ReadBE16(ops);
150
151 uint32_t data_loc = SDL_ReadBE32(ops);
152 uint32_t bss_loc = SDL_ReadBE32(ops);
153
154 inf("BIOS text 0x%x:0x%x data 0x%x:0x%x bss 0x%x:0x%x",
155 text_loc, text_len, data_loc, data_len, bss_loc, bss_len);
156
157 size_t load_len = (size_t)SDL_RWsize(ops) - 36;
158
159 if (text_loc != ROM_START || text_loc + text_len != data_loc ||
160 load_len != text_len + data_len || load_len > ROM_SIZE) {
161 fail("invalid BIOS file %s", bios);
162 }
163
164 size_t loaded = 0;
165
166 while (loaded < load_len) {
167 size_t n_rd = SDL_RWread(ops, rom_data + loaded, 1, load_len - loaded);
168
169 if (n_rd == 0) {
170 fail("error while reading BIOS file %s", bios);
171 }
172
173 loaded += n_rd;
174 }
175
176 SDL_RWclose(ops);
177
178 rom_ro_beg = text_loc;
179 rom_ro_end = text_loc + text_len + data_len;
180 rom_rw_beg = bss_loc;
181 rom_rw_end = bss_loc + bss_len;
182
183 ver("rom_ro_beg 0x%08x rom_ro_end 0x%08x", rom_ro_beg, rom_ro_end);
184 ver("rom_rw_beg 0x%08x rom_rw_end 0x%08x", rom_rw_beg, rom_rw_end);
185}
186
187uint32_t m68k_read_disassembler_8(uint32_t addr)
188{
189 return m68k_read_memory_8(addr);
190}
191
192uint32_t m68k_read_disassembler_16(uint32_t addr)
193{
194 return m68k_read_memory_16(addr);
195}
196
197uint32_t m68k_read_disassembler_32(uint32_t addr)
198{
199 return m68k_read_memory_32(addr);
200}
201
202uint32_t m68k_read_memory_8(uint32_t addr)
203{
204 ver3("mem rd 0x%08x:8", addr);
205
206 if (addr >= ram_ro_beg && addr <= ram_ro_end - 1) {
207 return ram_data[addr - RAM_START];
208 }
209
210 if (addr >= ram_rw_beg && addr <= ram_rw_end - 1) {
211 return ram_data[addr - RAM_START];
212 }
213
214 if (addr >= rom_ro_beg && addr <= rom_ro_end - 1) {
215 return rom_data[addr - ROM_START];
216 }
217
218 if (addr >= rom_rw_beg && addr <= rom_rw_end - 1) {
219 // ROM has its BSS section in RAM.
220 return ram_data[addr - RAM_START];
221 }
222
223 hw_t *hw = hw_by_addr(addr);
224
225 if (hw != NULL) {
226 return hw->read(hw_off(hw, addr), 1);
227 }
228
229 if (addr <= APP_START - 1) {
230 return ram_data[addr];
231 }
232
233 fail("invalid read 0x%08x:8", addr);
234}
235
236uint32_t m68k_read_memory_16(uint32_t addr)
237{
238 ver3("mem rd 0x%08x:16", addr);
239
240 if (addr >= ram_ro_beg && addr <= ram_ro_end - 2) {
241 return
242 ((uint32_t)ram_data[addr - RAM_START + 0] << 8) |
243 ((uint32_t)ram_data[addr - RAM_START + 1] << 0);
244 }
245
246 if (addr >= ram_rw_beg && addr <= ram_rw_end - 2) {
247 return
248 ((uint32_t)ram_data[addr - RAM_START + 0] << 8) |
249 ((uint32_t)ram_data[addr - RAM_START + 1] << 0);
250 }
251
252 if (addr >= rom_ro_beg && addr <= rom_ro_end - 2) {
253 return
254 ((uint32_t)rom_data[addr - ROM_START + 0] << 8) |
255 ((uint32_t)rom_data[addr - ROM_START + 1] << 0);
256 }
257
258 if (addr >= rom_rw_beg && addr <= rom_rw_end - 2) {
259 // ROM has its BSS section in RAM.
260 return
261 ((uint32_t)ram_data[addr - RAM_START + 0] << 8) |
262 ((uint32_t)ram_data[addr - RAM_START + 1] << 0);
263 }
264
265 hw_t *hw = hw_by_addr(addr);
266
267 if (hw != NULL) {
268 return hw->read(hw_off(hw, addr), 2);
269 }
270
271 if (addr <= APP_START - 2) {
272 return
273 ((uint32_t)ram_data[addr + 0] << 8) |
274 ((uint32_t)ram_data[addr + 1] << 0);
275 }
276
277 fail("invalid read 0x%08x:16", addr);
278}
279
280uint32_t m68k_read_memory_32(uint32_t addr)
281{
282 ver3("mem rd 0x%08x:32", addr);
283
284 if (reset) {
285 if (addr == 0) {
286 addr += ROM_START;
287 }
288 else if (addr == 4) {
289 addr += ROM_START;
290 reset = false;
291 }
292 else {
293 fail("invalid reset sequence");
294 }
295 }
296
297 if (addr >= ram_ro_beg && addr <= ram_ro_end - 4) {
298 return
299 ((uint32_t)ram_data[addr - RAM_START + 0] << 24) |
300 ((uint32_t)ram_data[addr - RAM_START + 1] << 16) |
301 ((uint32_t)ram_data[addr - RAM_START + 2] << 8) |
302 ((uint32_t)ram_data[addr - RAM_START + 3] << 0);
303 }
304
305 if (addr >= ram_rw_beg && addr <= ram_rw_end - 4) {
306 return
307 ((uint32_t)ram_data[addr - RAM_START + 0] << 24) |
308 ((uint32_t)ram_data[addr - RAM_START + 1] << 16) |
309 ((uint32_t)ram_data[addr - RAM_START + 2] << 8) |
310 ((uint32_t)ram_data[addr - RAM_START + 3] << 0);
311 }
312
313 if (addr >= rom_ro_beg && addr <= rom_ro_end - 4) {
314 return
315 ((uint32_t)rom_data[addr - ROM_START + 0] << 24) |
316 ((uint32_t)rom_data[addr - ROM_START + 1] << 16) |
317 ((uint32_t)rom_data[addr - ROM_START + 2] << 8) |
318 ((uint32_t)rom_data[addr - ROM_START + 3] << 0);
319 }
320
321 if (addr >= rom_rw_beg && addr <= rom_rw_end - 4) {
322 // ROM has its BSS section in RAM.
323 return
324 ((uint32_t)ram_data[addr - RAM_START + 0] << 24) |
325 ((uint32_t)ram_data[addr - RAM_START + 1] << 16) |
326 ((uint32_t)ram_data[addr - RAM_START + 2] << 8) |
327 ((uint32_t)ram_data[addr - RAM_START + 3] << 0);
328 }
329
330 hw_t *hw = hw_by_addr(addr);
331
332 if (hw != NULL) {
333 return hw->read(hw_off(hw, addr), 4);
334 }
335
336 if (addr <= APP_START - 4) {
337 return
338 ((uint32_t)ram_data[addr + 0] << 24) |
339 ((uint32_t)ram_data[addr + 1] << 16) |
340 ((uint32_t)ram_data[addr + 2] << 8) |
341 ((uint32_t)ram_data[addr + 3] << 0);
342 }
343
344 fail("invalid read 0x%08x:32", addr);
345}
346
347void m68k_write_memory_8(uint32_t addr, uint32_t val)
348{
349 ver3("mem wr 0x%08x:8 0x%02x", addr, val);
350
351 if (addr >= ram_rw_beg && addr <= ram_rw_end - 1) {
352 ram_data[addr - RAM_START] = (uint8_t)val;
353 return;
354 }
355
356 if (addr >= rom_rw_beg && addr <= rom_rw_end - 1) {
357 // ROM has its BSS section in RAM.
358 ram_data[addr - RAM_START] = (uint8_t)val;
359 return;
360 }
361
362 hw_t *hw = hw_by_addr(addr);
363
364 if (hw != NULL) {
365 hw->write(hw_off(hw, addr), 1, val);
366 return;
367 }
368
369 if (addr <= APP_START - 1) {
370 ram_data[addr] = (uint8_t)val;
371 return;
372 }
373
374 fail("invalid write 0x%08x:8 0x%02x", addr, val);
375}
376
377void m68k_write_memory_16(uint32_t addr, uint32_t val)
378{
379 ver3("mem wr 0x%08x:16 0x%04x", addr, val);
380
381 if (addr >= ram_rw_beg && addr <= ram_rw_end - 2) {
382 ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 8);
383 ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 0);
384 return;
385 }
386
387 if (addr >= rom_rw_beg && addr <= rom_rw_end - 2) {
388 // ROM has its BSS section in RAM.
389 ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 8);
390 ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 0);
391 return;
392 }
393
394 hw_t *hw = hw_by_addr(addr);
395
396 if (hw != NULL) {
397 hw->write(hw_off(hw, addr), 2, val);
398 return;
399 }
400
401 if (addr <= APP_START - 2) {
402 ram_data[addr + 0] = (uint8_t)(val >> 8);
403 ram_data[addr + 1] = (uint8_t)(val >> 0);
404 return;
405 }
406
407 fail("invalid write 0x%08x:16 0x%04x", addr, val);
408}
409
410void m68k_write_memory_32(uint32_t addr, uint32_t val)
411{
412 ver3("mem wr 0x%08x:32 0x%08x", addr, val);
413
414 if (addr >= ram_rw_beg && addr <= ram_rw_end - 4) {
415 ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 24);
416 ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 16);
417 ram_data[addr - RAM_START + 2] = (uint8_t)(val >> 8);
418 ram_data[addr - RAM_START + 3] = (uint8_t)(val >> 0);
419 return;
420 }
421
422 if (addr >= rom_rw_beg && addr <= rom_rw_end - 4) {
423 // ROM has its BSS section in RAM.
424 ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 24);
425 ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 16);
426 ram_data[addr - RAM_START + 2] = (uint8_t)(val >> 8);
427 ram_data[addr - RAM_START + 3] = (uint8_t)(val >> 0);
428 return;
429 }
430
431 hw_t *hw = hw_by_addr(addr);
432
433 if (hw != NULL) {
434 hw->write(hw_off(hw, addr), 4, val);
435 return;
436 }
437
438 if (addr <= APP_START - 4) {
439 ram_data[addr + 0] = (uint8_t)(val >> 24);
440 ram_data[addr + 1] = (uint8_t)(val >> 16);
441 ram_data[addr + 2] = (uint8_t)(val >> 8);
442 ram_data[addr + 3] = (uint8_t)(val >> 0);
443 return;
444 }
445
446 fail("invalid write 0x%08x:32 0x%08x", addr, val);
447}
448
449static void inst_cb(void)
450{
451 uint32_t pc = m68k_get_reg(NULL, M68K_REG_PC);
452 uint32_t op = m68k_read_memory_16(pc);
453
454 if (op == 0x4e4d) {
455 uint32_t sp = m68k_get_reg(NULL, M68K_REG_SP);
456 uint32_t fun = m68k_read_memory_16(sp);
457
458 switch (fun) {
459 case 1:
460 ver2("BIOS B_RDAV %u", m68k_read_memory_16(sp + 2));
461 break;
462
463 case 2:
464 ver2("BIOS B_GETC %u", m68k_read_memory_16(sp + 2));
465 break;
466
467 case 3:
468 ver2("BIOS B_PUTC %u %u",
469 m68k_read_memory_16(sp + 2),
470 m68k_read_memory_16(sp + 4));
471 break;
472
473 case 4:
474 ver2("BIOS B_RDWR %u 0x%08x %u %u %u",
475 m68k_read_memory_16(sp + 2),
476 m68k_read_memory_32(sp + 4),
477 m68k_read_memory_16(sp + 8),
478 m68k_read_memory_16(sp + 10),
479 m68k_read_memory_16(sp + 12));
480 break;
481
482 case 5:
483 ver2("BIOS B_SETV %u 0x%08x",
484 m68k_read_memory_16(sp + 2),
485 m68k_read_memory_32(sp + 4));
486 break;
487
488 case 7:
489 ver2("BIOS B_GBPB %u", m68k_read_memory_16(sp + 2));
490 break;
491
492 case 8:
493 ver2("BIOS B_THRE %u", m68k_read_memory_16(sp + 2));
494 break;
495
496 case 9:
497 ver2("BIOS B_MCHG %u", m68k_read_memory_16(sp + 2));
498 break;
499
500 case 10:
501 ver2("BIOS B_DMAP");
502 break;
503
504 default:
505 fail("invalid function: BIOS %d", fun);
506 }
507 }
508 else if (op == 0x4e4e) {
509 uint32_t sp = m68k_get_reg(NULL, M68K_REG_SP);
510 uint32_t fun = m68k_read_memory_16(sp);
511
512 switch (fun) {
513 case 0:
514 ver2("XBIOS X_PIOREC %u", m68k_read_memory_16(sp + 2));
515 break;
516
517 case 1:
518 ver2("XBIOS X_SETPRT %u 0x%02x 0x%02x 0x%02x 0x%02x",
519 m68k_read_memory_16(sp + 2),
520 m68k_read_memory_16(sp + 4),
521 m68k_read_memory_16(sp + 6),
522 m68k_read_memory_16(sp + 8),
523 m68k_read_memory_16(sp + 10));
524 break;
525
526 case 2:
527 ver2("XBIOS X_FLOPRD 0x%08x 0x%08x %u %u %u %u %u",
528 m68k_read_memory_32(sp + 2),
529 m68k_read_memory_32(sp + 6),
530 m68k_read_memory_16(sp + 10),
531 m68k_read_memory_16(sp + 12),
532 m68k_read_memory_16(sp + 14),
533 m68k_read_memory_16(sp + 16),
534 m68k_read_memory_16(sp + 18));
535 break;
536
537 case 3:
538 ver2("XBIOS X_FLOPWR 0x%08x 0x%08x %u %u %u %u %u",
539 m68k_read_memory_32(sp + 2),
540 m68k_read_memory_32(sp + 6),
541 m68k_read_memory_16(sp + 10),
542 m68k_read_memory_16(sp + 12),
543 m68k_read_memory_16(sp + 14),
544 m68k_read_memory_16(sp + 16),
545 m68k_read_memory_16(sp + 18));
546 break;
547
548 case 4:
549 ver2("XBIOS X_FORMAT 0x%08x 0x%08x %u %u %u %u %u 0x%08x %u",
550 m68k_read_memory_32(sp + 2),
551 m68k_read_memory_32(sp + 6),
552 m68k_read_memory_16(sp + 10),
553 m68k_read_memory_16(sp + 12),
554 m68k_read_memory_16(sp + 14),
555 m68k_read_memory_16(sp + 16),
556 m68k_read_memory_16(sp + 18),
557 m68k_read_memory_32(sp + 20),
558 m68k_read_memory_16(sp + 24));
559 break;
560
561 case 5:
562 ver2("XBIOS X_VERIFY 0x%08x 0x%08x %u %u %u %u %u",
563 m68k_read_memory_32(sp + 2),
564 m68k_read_memory_32(sp + 6),
565 m68k_read_memory_16(sp + 10),
566 m68k_read_memory_16(sp + 12),
567 m68k_read_memory_16(sp + 14),
568 m68k_read_memory_16(sp + 16),
569 m68k_read_memory_16(sp + 18));
570 break;
571
572 case 6:
573 ver2("XBIOS X_PRBOOT 0x%08x %u %u %u",
574 m68k_read_memory_32(sp + 2),
575 m68k_read_memory_16(sp + 6),
576 m68k_read_memory_16(sp + 8),
577 m68k_read_memory_16(sp + 10));
578 break;
579
580 case 7:
581 ver2("XBIOS X_RANDOM");
582 break;
583
584 case 8:
585 ver2("XBIOS X_ANALOG");
586 break;
587
588 case 9:
589 ver2("XBIOS X_CLRAFI");
590 break;
591
592 case 10:
593 ver2("XBIOS X_APICHK");
594 break;
595
596 case 11:
597 ver2("XBIOS X_MTDEFS ");
598 break;
599
600 default:
601 fail("invalid function: XBIOS %d", fun);
602 }
603 }
604}
605
606void cpu_loop(const char *bios)
607{
608 hw_init();
609 bios_init(bios);
610
611 inf("entering CPU loop");
612 m68k_init();
613 m68k_set_cpu_type(M68K_CPU_TYPE_68000);
614 m68k_set_instr_hook_callback(inst_cb);
615 m68k_pulse_reset();
616
617 uint64_t freq = SDL_GetPerformanceFrequency();
618 uint64_t quan = freq / PER_SEC;
619 inf("freq %" PRIu64 " quan %" PRIu64, freq, quan);
620
621 bool run = true;
622
623#if defined EMU_LINUX
624 SDL_Scancode down = SDL_SCANCODE_UNKNOWN;
625#endif
626
627 while (run) {
628 uint64_t until = SDL_GetPerformanceCounter() + quan;
629
630 m68k_execute(CPU_FREQ / PER_SEC);
631 hw_exec();
632
633 SDL_Event ev;
634
635 while (SDL_PollEvent(&ev) > 0) {
636#if defined EMU_LINUX
637 // Work around duplicate key-down events on Linux.
638
639 if (ev.type == SDL_KEYDOWN) {
640 if (down == ev.key.keysym.scancode) {
641 continue;
642 }
643
644 down = ev.key.keysym.scancode;
645 }
646 else if (ev.type == SDL_KEYUP) {
647 down = SDL_SCANCODE_UNKNOWN;
648 }
649#endif
650
651 if (ev.type == SDL_QUIT ||
652 (ev.type == SDL_KEYDOWN && ev.key.keysym.sym == SDLK_ESCAPE)) {
653 run = false;
654 continue;
655 }
656
657 if (ev.type == SDL_TEXTINPUT) {
658 ser_text(&ev.text);
659 continue;
660 }
661
662 if (ev.type == SDL_KEYDOWN) {
663 ser_key(&ev.key);
664 continue;
665 }
666 }
667
668 while (SDL_GetPerformanceCounter() < until) {
669 _mm_pause();
670 }
671 }
672
673 inf("leaving CPU loop");
674 hw_quit();
675}
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