source: buchla-emu/emu/cpu.c@ 8967dbc

Last change on this file since 8967dbc was c5b6c90, checked in by Thomas Lopatic <thomas@…>, 7 years ago

Successfully loaded midas.abs from disk.
  • Property mode set to 100644
File size: 15.9 KB
Line 
1/*
2 * Copyright (C) 2017 The Contributors
3 *
4 * This program is free software: you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation, either version 3 of the License, or (at
7 * your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
13 *
14 * A copy of the GNU General Public License can be found in the file
15 * "gpl.txt" in the top directory of this repository.
16 */
17
18#include <all.h>
19
20#define ver(...) _ver(cpu_verbose, 0, __VA_ARGS__)
21#define ver2(...) _ver(cpu_verbose, 1, __VA_ARGS__)
22#define ver3(...) _ver(cpu_verbose, 2, __VA_ARGS__)
23
24int32_t cpu_verbose = 0;
25
26#define CPU_FREQ 7000000
27#define PER_SEC 100000
28
29#define APP_START 0x10000
30
31#define RAM_START 0x0
32#define RAM_SIZE 0x100000
33
34#define ROM_START 0x100000
35#define ROM_SIZE 0x10000
36
37typedef void (*hw_init_t)(void);
38typedef void (*hw_quit_t)(void);
39typedef bool (*hw_exec_t)(void);
40typedef uint32_t (*hw_read_t)(uint32_t off, int32_t sz);
41typedef void (*hw_write_t)(uint32_t off, int32_t sz, uint32_t val);
42
43typedef struct {
44 uint32_t addr_beg;
45 uint32_t addr_end;
46 uint32_t irq;
47 hw_init_t init;
48 hw_quit_t quit;
49 hw_exec_t exec;
50 hw_read_t read;
51 hw_write_t write;
52} hw_t;
53
54static bool reset = true;
55
56static uint8_t ram_data[RAM_SIZE];
57static uint8_t rom_data[ROM_SIZE];
58
59static uint32_t ram_ro_beg = 0x1234;
60static uint32_t ram_ro_end = 0x1234;
61static uint32_t ram_rw_beg = 0x1234;
62static uint32_t ram_rw_end = 0x1234;
63
64static uint32_t rom_ro_beg;
65static uint32_t rom_ro_end;
66static uint32_t rom_rw_beg;
67static uint32_t rom_rw_end;
68
69static hw_t hw_map[] = {
70 { 0x180000, 0x200000, 0, fpu_init, fpu_quit, fpu_exec, fpu_read, fpu_write },
71 { 0x200000, 0x280000, 0, vid_init, vid_quit, vid_exec, vid_read, vid_write },
72 { 0x3a0001, 0x3a4001, 0, tim_init, tim_quit, tim_exec, tim_read, tim_write },
73 { 0x3a4001, 0x3a8001, 0, lcd_init, lcd_quit, lcd_exec, lcd_read, lcd_write },
74 { 0x3a8001, 0x3ac001, 5, ser_init, ser_quit, ser_exec, ser_read, ser_write },
75 { 0x3ac001, 0x3b0001, 0, mid_init, mid_quit, mid_exec, mid_read, mid_write },
76 { 0x3b0001, 0x3b4001, 0, fdd_init, fdd_quit, fdd_exec, fdd_read, fdd_write },
77 { 0x3b4001, 0x3b8001, 0, snd_init, snd_quit, snd_exec, snd_read, snd_write },
78 { 0x3b8001, 0x3bc001, 0, led_init, led_quit, led_exec, led_read, led_write },
79 { 0x3bc001, 0x3c0001, 0, kbd_init, kbd_quit, kbd_exec, kbd_read, kbd_write }
80};
81
82static hw_t *hw_by_addr(uint32_t addr)
83{
84 for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
85 if (addr >= hw_map[i].addr_beg && addr < hw_map[i].addr_end) {
86 return hw_map + i;
87 }
88 }
89
90 return NULL;
91}
92
93static void hw_init(void)
94{
95 inf("starting hardware");
96
97 for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
98 hw_map[i].init();
99 }
100}
101
102static void hw_quit(void)
103{
104 inf("halting hardware");
105
106 for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
107 hw_map[i].quit();
108 }
109}
110
111static uint32_t hw_exec(void)
112{
113 uint32_t irq = 0;
114
115 for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
116 if (hw_map[i].exec() && hw_map[i].irq > irq) {
117 irq = hw_map[i].irq;
118 }
119 }
120
121 return irq;
122}
123
124static uint32_t hw_off(hw_t *hw, uint32_t addr)
125{
126 if ((hw->addr_beg & 0x1) == 0) {
127 return addr - hw->addr_beg;
128 }
129
130 return (addr - hw->addr_beg) / 2;
131}
132
133static void bios_init(void)
134{
135 inf("loading BIOS file %s", bios);
136
137 SDL_RWops *ops = SDL_RWFromFile(bios, "rb");
138
139 if (ops == NULL) {
140 fail("error while opening BIOS file %s", bios);
141 }
142
143 if (SDL_ReadBE16(ops) != 0x601b) {
144 fail("invalid BIOS file %s", bios);
145 }
146
147 uint32_t text_len = SDL_ReadBE32(ops);
148 uint32_t data_len = SDL_ReadBE32(ops);
149 uint32_t bss_len = SDL_ReadBE32(ops);
150
151 SDL_ReadBE32(ops);
152 SDL_ReadBE32(ops);
153
154 uint32_t text_loc = SDL_ReadBE32(ops);
155
156 SDL_ReadBE16(ops);
157
158 uint32_t data_loc = SDL_ReadBE32(ops);
159 uint32_t bss_loc = SDL_ReadBE32(ops);
160
161 inf("BIOS text 0x%x:0x%x data 0x%x:0x%x bss 0x%x:0x%x",
162 text_loc, text_len, data_loc, data_len, bss_loc, bss_len);
163
164 size_t load_len = (size_t)SDL_RWsize(ops) - 36;
165
166 if (text_loc != ROM_START || text_loc + text_len != data_loc ||
167 load_len != text_len + data_len || load_len > ROM_SIZE) {
168 fail("invalid BIOS file %s", bios);
169 }
170
171 size_t loaded = 0;
172
173 while (loaded < load_len) {
174 size_t n_rd = SDL_RWread(ops, rom_data + loaded, 1, load_len - loaded);
175
176 if (n_rd == 0) {
177 fail("error while reading BIOS file %s", bios);
178 }
179
180 loaded += n_rd;
181 }
182
183 SDL_RWclose(ops);
184
185 rom_ro_beg = text_loc;
186 rom_ro_end = text_loc + text_len + data_len;
187 rom_rw_beg = bss_loc;
188 rom_rw_end = bss_loc + bss_len;
189
190 ver("rom_ro_beg 0x%08x rom_ro_end 0x%08x", rom_ro_beg, rom_ro_end);
191 ver("rom_rw_beg 0x%08x rom_rw_end 0x%08x", rom_rw_beg, rom_rw_end);
192}
193
194uint32_t m68k_read_disassembler_8(uint32_t addr)
195{
196 return m68k_read_memory_8(addr);
197}
198
199uint32_t m68k_read_disassembler_16(uint32_t addr)
200{
201 return m68k_read_memory_16(addr);
202}
203
204uint32_t m68k_read_disassembler_32(uint32_t addr)
205{
206 return m68k_read_memory_32(addr);
207}
208
209uint32_t m68k_read_memory_8(uint32_t addr)
210{
211 ver3("mem rd 0x%08x:8", addr);
212
213 if (addr >= ram_ro_beg && addr <= ram_ro_end - 1) {
214 return ram_data[addr - RAM_START];
215 }
216
217 if (addr >= ram_rw_beg && addr <= ram_rw_end - 1) {
218 return ram_data[addr - RAM_START];
219 }
220
221 if (addr >= rom_ro_beg && addr <= rom_ro_end - 1) {
222 return rom_data[addr - ROM_START];
223 }
224
225 if (addr >= rom_rw_beg && addr <= rom_rw_end - 1) {
226 // ROM has its BSS section in RAM.
227 return ram_data[addr - RAM_START];
228 }
229
230 hw_t *hw = hw_by_addr(addr);
231
232 if (hw != NULL) {
233 return hw->read(hw_off(hw, addr), 1);
234 }
235
236 if (addr <= APP_START - 1) {
237 return ram_data[addr];
238 }
239
240 fail("invalid read 0x%08x:8", addr);
241}
242
243uint32_t m68k_read_memory_16(uint32_t addr)
244{
245 ver3("mem rd 0x%08x:16", addr);
246
247 if (addr >= ram_ro_beg && addr <= ram_ro_end - 2) {
248 return
249 ((uint32_t)ram_data[addr - RAM_START + 0] << 8) |
250 ((uint32_t)ram_data[addr - RAM_START + 1] << 0);
251 }
252
253 if (addr >= ram_rw_beg && addr <= ram_rw_end - 2) {
254 return
255 ((uint32_t)ram_data[addr - RAM_START + 0] << 8) |
256 ((uint32_t)ram_data[addr - RAM_START + 1] << 0);
257 }
258
259 if (addr >= rom_ro_beg && addr <= rom_ro_end - 2) {
260 return
261 ((uint32_t)rom_data[addr - ROM_START + 0] << 8) |
262 ((uint32_t)rom_data[addr - ROM_START + 1] << 0);
263 }
264
265 if (addr >= rom_rw_beg && addr <= rom_rw_end - 2) {
266 // ROM has its BSS section in RAM.
267 return
268 ((uint32_t)ram_data[addr - RAM_START + 0] << 8) |
269 ((uint32_t)ram_data[addr - RAM_START + 1] << 0);
270 }
271
272 hw_t *hw = hw_by_addr(addr);
273
274 if (hw != NULL) {
275 return hw->read(hw_off(hw, addr), 2);
276 }
277
278 if (addr <= APP_START - 2) {
279 return
280 ((uint32_t)ram_data[addr + 0] << 8) |
281 ((uint32_t)ram_data[addr + 1] << 0);
282 }
283
284 fail("invalid read 0x%08x:16", addr);
285}
286
287uint32_t m68k_read_memory_32(uint32_t addr)
288{
289 ver3("mem rd 0x%08x:32", addr);
290
291 if (reset) {
292 if (addr == 0) {
293 addr += ROM_START;
294 }
295 else if (addr == 4) {
296 addr += ROM_START;
297 reset = false;
298 }
299 else {
300 fail("invalid reset sequence");
301 }
302 }
303
304 if (addr >= ram_ro_beg && addr <= ram_ro_end - 4) {
305 return
306 ((uint32_t)ram_data[addr - RAM_START + 0] << 24) |
307 ((uint32_t)ram_data[addr - RAM_START + 1] << 16) |
308 ((uint32_t)ram_data[addr - RAM_START + 2] << 8) |
309 ((uint32_t)ram_data[addr - RAM_START + 3] << 0);
310 }
311
312 if (addr >= ram_rw_beg && addr <= ram_rw_end - 4) {
313 return
314 ((uint32_t)ram_data[addr - RAM_START + 0] << 24) |
315 ((uint32_t)ram_data[addr - RAM_START + 1] << 16) |
316 ((uint32_t)ram_data[addr - RAM_START + 2] << 8) |
317 ((uint32_t)ram_data[addr - RAM_START + 3] << 0);
318 }
319
320 if (addr >= rom_ro_beg && addr <= rom_ro_end - 4) {
321 return
322 ((uint32_t)rom_data[addr - ROM_START + 0] << 24) |
323 ((uint32_t)rom_data[addr - ROM_START + 1] << 16) |
324 ((uint32_t)rom_data[addr - ROM_START + 2] << 8) |
325 ((uint32_t)rom_data[addr - ROM_START + 3] << 0);
326 }
327
328 if (addr >= rom_rw_beg && addr <= rom_rw_end - 4) {
329 // ROM has its BSS section in RAM.
330 return
331 ((uint32_t)ram_data[addr - RAM_START + 0] << 24) |
332 ((uint32_t)ram_data[addr - RAM_START + 1] << 16) |
333 ((uint32_t)ram_data[addr - RAM_START + 2] << 8) |
334 ((uint32_t)ram_data[addr - RAM_START + 3] << 0);
335 }
336
337 hw_t *hw = hw_by_addr(addr);
338
339 if (hw != NULL) {
340 return hw->read(hw_off(hw, addr), 4);
341 }
342
343 if (addr <= APP_START - 4) {
344 return
345 ((uint32_t)ram_data[addr + 0] << 24) |
346 ((uint32_t)ram_data[addr + 1] << 16) |
347 ((uint32_t)ram_data[addr + 2] << 8) |
348 ((uint32_t)ram_data[addr + 3] << 0);
349 }
350
351 fail("invalid read 0x%08x:32", addr);
352}
353
354void m68k_write_memory_8(uint32_t addr, uint32_t val)
355{
356 ver3("mem wr 0x%08x:8 0x%02x", addr, val);
357
358 if (addr >= ram_rw_beg && addr <= ram_rw_end - 1) {
359 ram_data[addr - RAM_START] = (uint8_t)val;
360 return;
361 }
362
363 if (addr >= rom_rw_beg && addr <= rom_rw_end - 1) {
364 // ROM has its BSS section in RAM.
365 ram_data[addr - RAM_START] = (uint8_t)val;
366 return;
367 }
368
369 hw_t *hw = hw_by_addr(addr);
370
371 if (hw != NULL) {
372 hw->write(hw_off(hw, addr), 1, val);
373 return;
374 }
375
376 if (addr <= APP_START - 1) {
377 ram_data[addr] = (uint8_t)val;
378 return;
379 }
380
381 // handle loading midas.abs
382
383 if (addr == APP_START) {
384 ram_rw_beg = APP_START;
385 ram_rw_end = RAM_START + RAM_SIZE;
386 return;
387 }
388
389 fail("invalid write 0x%08x:8 0x%02x", addr, val);
390}
391
392void m68k_write_memory_16(uint32_t addr, uint32_t val)
393{
394 ver3("mem wr 0x%08x:16 0x%04x", addr, val);
395
396 if (addr >= ram_rw_beg && addr <= ram_rw_end - 2) {
397 ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 8);
398 ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 0);
399 return;
400 }
401
402 if (addr >= rom_rw_beg && addr <= rom_rw_end - 2) {
403 // ROM has its BSS section in RAM.
404 ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 8);
405 ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 0);
406 return;
407 }
408
409 hw_t *hw = hw_by_addr(addr);
410
411 if (hw != NULL) {
412 hw->write(hw_off(hw, addr), 2, val);
413 return;
414 }
415
416 if (addr <= APP_START - 2) {
417 ram_data[addr + 0] = (uint8_t)(val >> 8);
418 ram_data[addr + 1] = (uint8_t)(val >> 0);
419 return;
420 }
421
422 fail("invalid write 0x%08x:16 0x%04x", addr, val);
423}
424
425void m68k_write_memory_32(uint32_t addr, uint32_t val)
426{
427 ver3("mem wr 0x%08x:32 0x%08x", addr, val);
428
429 if (addr >= ram_rw_beg && addr <= ram_rw_end - 4) {
430 ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 24);
431 ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 16);
432 ram_data[addr - RAM_START + 2] = (uint8_t)(val >> 8);
433 ram_data[addr - RAM_START + 3] = (uint8_t)(val >> 0);
434 return;
435 }
436
437 if (addr >= rom_rw_beg && addr <= rom_rw_end - 4) {
438 // ROM has its BSS section in RAM.
439 ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 24);
440 ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 16);
441 ram_data[addr - RAM_START + 2] = (uint8_t)(val >> 8);
442 ram_data[addr - RAM_START + 3] = (uint8_t)(val >> 0);
443 return;
444 }
445
446 hw_t *hw = hw_by_addr(addr);
447
448 if (hw != NULL) {
449 hw->write(hw_off(hw, addr), 4, val);
450 return;
451 }
452
453 if (addr <= APP_START - 4) {
454 ram_data[addr + 0] = (uint8_t)(val >> 24);
455 ram_data[addr + 1] = (uint8_t)(val >> 16);
456 ram_data[addr + 2] = (uint8_t)(val >> 8);
457 ram_data[addr + 3] = (uint8_t)(val >> 0);
458 return;
459 }
460
461 fail("invalid write 0x%08x:32 0x%08x", addr, val);
462}
463
464static void inst_cb(void)
465{
466 uint32_t pc = m68k_get_reg(NULL, M68K_REG_PC);
467 uint32_t op = m68k_read_memory_16(pc);
468
469 if (op == 0x4e4d) {
470 uint32_t sp = m68k_get_reg(NULL, M68K_REG_SP);
471 uint32_t fun = m68k_read_memory_16(sp);
472
473 switch (fun) {
474 case 1:
475 ver2("BIOS B_RDAV %u", m68k_read_memory_16(sp + 2));
476 break;
477
478 case 2:
479 ver2("BIOS B_GETC %u", m68k_read_memory_16(sp + 2));
480 break;
481
482 case 3:
483 ver2("BIOS B_PUTC %u %u",
484 m68k_read_memory_16(sp + 2),
485 m68k_read_memory_16(sp + 4));
486 break;
487
488 case 4:
489 ver2("BIOS B_RDWR %u 0x%08x %u %u %u",
490 m68k_read_memory_16(sp + 2),
491 m68k_read_memory_32(sp + 4),
492 m68k_read_memory_16(sp + 8),
493 m68k_read_memory_16(sp + 10),
494 m68k_read_memory_16(sp + 12));
495 break;
496
497 case 5:
498 ver2("BIOS B_SETV %u 0x%08x",
499 m68k_read_memory_16(sp + 2),
500 m68k_read_memory_32(sp + 4));
501 break;
502
503 case 7:
504 ver2("BIOS B_GBPB %u", m68k_read_memory_16(sp + 2));
505 break;
506
507 case 8:
508 ver2("BIOS B_THRE %u", m68k_read_memory_16(sp + 2));
509 break;
510
511 case 9:
512 ver2("BIOS B_MCHG %u", m68k_read_memory_16(sp + 2));
513 break;
514
515 case 10:
516 ver2("BIOS B_DMAP");
517 break;
518
519 default:
520 fail("invalid function: BIOS %d", fun);
521 }
522 }
523 else if (op == 0x4e4e) {
524 uint32_t sp = m68k_get_reg(NULL, M68K_REG_SP);
525 uint32_t fun = m68k_read_memory_16(sp);
526
527 switch (fun) {
528 case 0:
529 ver2("XBIOS X_PIOREC %u", m68k_read_memory_16(sp + 2));
530 break;
531
532 case 1:
533 ver2("XBIOS X_SETPRT %u 0x%02x 0x%02x 0x%02x 0x%02x",
534 m68k_read_memory_16(sp + 2),
535 m68k_read_memory_16(sp + 4),
536 m68k_read_memory_16(sp + 6),
537 m68k_read_memory_16(sp + 8),
538 m68k_read_memory_16(sp + 10));
539 break;
540
541 case 2:
542 ver2("XBIOS X_FLOPRD 0x%08x 0x%08x %u %u %u %u %u",
543 m68k_read_memory_32(sp + 2),
544 m68k_read_memory_32(sp + 6),
545 m68k_read_memory_16(sp + 10),
546 m68k_read_memory_16(sp + 12),
547 m68k_read_memory_16(sp + 14),
548 m68k_read_memory_16(sp + 16),
549 m68k_read_memory_16(sp + 18));
550 break;
551
552 case 3:
553 ver2("XBIOS X_FLOPWR 0x%08x 0x%08x %u %u %u %u %u",
554 m68k_read_memory_32(sp + 2),
555 m68k_read_memory_32(sp + 6),
556 m68k_read_memory_16(sp + 10),
557 m68k_read_memory_16(sp + 12),
558 m68k_read_memory_16(sp + 14),
559 m68k_read_memory_16(sp + 16),
560 m68k_read_memory_16(sp + 18));
561 break;
562
563 case 4:
564 ver2("XBIOS X_FORMAT 0x%08x 0x%08x %u %u %u %u %u 0x%08x %u",
565 m68k_read_memory_32(sp + 2),
566 m68k_read_memory_32(sp + 6),
567 m68k_read_memory_16(sp + 10),
568 m68k_read_memory_16(sp + 12),
569 m68k_read_memory_16(sp + 14),
570 m68k_read_memory_16(sp + 16),
571 m68k_read_memory_16(sp + 18),
572 m68k_read_memory_32(sp + 20),
573 m68k_read_memory_16(sp + 24));
574 break;
575
576 case 5:
577 ver2("XBIOS X_VERIFY 0x%08x 0x%08x %u %u %u %u %u",
578 m68k_read_memory_32(sp + 2),
579 m68k_read_memory_32(sp + 6),
580 m68k_read_memory_16(sp + 10),
581 m68k_read_memory_16(sp + 12),
582 m68k_read_memory_16(sp + 14),
583 m68k_read_memory_16(sp + 16),
584 m68k_read_memory_16(sp + 18));
585 break;
586
587 case 6:
588 ver2("XBIOS X_PRBOOT 0x%08x %u %u %u",
589 m68k_read_memory_32(sp + 2),
590 m68k_read_memory_16(sp + 6),
591 m68k_read_memory_16(sp + 8),
592 m68k_read_memory_16(sp + 10));
593 break;
594
595 case 7:
596 ver2("XBIOS X_RANDOM");
597 break;
598
599 case 8:
600 ver2("XBIOS X_ANALOG");
601 break;
602
603 case 9:
604 ver2("XBIOS X_CLRAFI");
605 break;
606
607 case 10:
608 ver2("XBIOS X_APICHK");
609 break;
610
611 case 11:
612 ver2("XBIOS X_MTDEFS ");
613 break;
614
615 default:
616 fail("invalid function: XBIOS %d", fun);
617 }
618 }
619}
620
621void cpu_loop(void)
622{
623 hw_init();
624 bios_init();
625
626 inf("entering CPU loop");
627 m68k_init();
628 m68k_set_cpu_type(M68K_CPU_TYPE_68000);
629 m68k_set_instr_hook_callback(inst_cb);
630 m68k_pulse_reset();
631
632 uint64_t freq = SDL_GetPerformanceFrequency();
633 uint64_t quan = freq / PER_SEC;
634 inf("freq %" PRIu64 " quan %" PRIu64, freq, quan);
635
636 bool run = true;
637
638#if defined EMU_LINUX
639 SDL_Scancode down = SDL_SCANCODE_UNKNOWN;
640#endif
641
642 while (run) {
643 uint64_t until = SDL_GetPerformanceCounter() + quan;
644
645 m68k_execute(CPU_FREQ / PER_SEC);
646 uint32_t irq = hw_exec();
647
648 if (irq > 0) {
649 ver2("irq %u", irq);
650 }
651
652 m68k_set_irq(irq);
653
654 SDL_Event ev;
655
656 while (SDL_PollEvent(&ev) > 0) {
657#if defined EMU_LINUX
658 // Work around duplicate key-down events on Linux.
659
660 if (ev.type == SDL_KEYDOWN) {
661 if (down == ev.key.keysym.scancode) {
662 continue;
663 }
664
665 down = ev.key.keysym.scancode;
666 }
667 else if (ev.type == SDL_KEYUP) {
668 down = SDL_SCANCODE_UNKNOWN;
669 }
670#endif
671
672 if (ev.type == SDL_QUIT ||
673 (ev.type == SDL_KEYDOWN && ev.key.keysym.sym == SDLK_ESCAPE)) {
674 run = false;
675 continue;
676 }
677
678 if (ev.type == SDL_TEXTINPUT) {
679 ser_text(&ev.text);
680 continue;
681 }
682
683 if (ev.type == SDL_KEYDOWN) {
684 ser_key(&ev.key);
685 continue;
686 }
687 }
688
689 while (SDL_GetPerformanceCounter() < until) {
690 _mm_pause();
691 }
692 }
693
694 inf("leaving CPU loop");
695 hw_quit();
696}
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