source: buchla-emu/emu/fdd.c

0.1
Last change on this file was 9b204fa, checked in by Thomas Lopatic <thomas@…>, 7 years ago

Persist disk image.
  • Property mode set to 100644
File size: 7.4 KB
Line 
1/*
2 * Copyright (C) 2017 The Contributors
3 *
4 * This program is free software: you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation, either version 3 of the License, or (at
7 * your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
13 *
14 * A copy of the GNU General Public License can be found in the file
15 * "gpl.txt" in the top directory of this repository.
16 */
17
18#include <all.h>
19
20#define ver(...) _ver(fdd_verbose, 0, __VA_ARGS__)
21#define ver2(...) _ver(fdd_verbose, 1, __VA_ARGS__)
22#define ver3(...) _ver(fdd_verbose, 2, __VA_ARGS__)
23
24int32_t fdd_verbose = 0;
25
26#define N_CYL 80
27#define N_SID 2
28#define N_SEC 9
29#define SZ_SEC 512
30
31#define SZ_DISK (N_CYL * N_SID * N_SEC * SZ_SEC)
32
33#define REG_COM_STAT 0
34#define REG_TRA 1
35#define REG_SEC 2
36#define REG_DAT 3
37
38#define COM_REST 0x00
39#define COM_SEEK 0x10
40#define COM_SEEK_VER 0x14
41#define COM_RD_SEC 0x80
42#define COM_RD_SEC_MUL 0x90
43#define COM_WR_SEC_WP 0xa0
44#define COM_WR_SEC 0xa2
45#define COM_INT 0xd0
46#define COM_WR_TRA_WP 0xf0
47#define COM_WR_TRA 0xf2
48
49#define COM_LAT_CYC 5
50#define COM_EXE_CYC 5
51
52typedef enum {
53 STEP_IDLE,
54 STEP_PREP,
55 STEP_EXEC
56} step_t;
57
58typedef struct {
59 int32_t reg_tra;
60 int32_t reg_sec;
61 int32_t reg_dat;
62 int32_t sid;
63 step_t step;
64 int32_t com;
65 int32_t cyc;
66 uint8_t *dat;
67 bool tra_0;
68} state_t;
69
70static state_t state = {
71 .reg_tra = 0, .reg_sec = 0, .reg_dat = 0, .sid = 0,
72 .step = STEP_IDLE, .com = -1, .cyc = 0, .dat = NULL, .tra_0 = false
73};
74
75static uint8_t image[SZ_DISK];
76
77static const char *com_string(int32_t com)
78{
79 switch (com) {
80 case COM_REST:
81 return "COM_REST";
82
83 case COM_SEEK:
84 return "COM_SEEK";
85
86 case COM_SEEK_VER:
87 return "COM_SEEK_VER";
88
89 case COM_RD_SEC:
90 return "COM_RD_SEC";
91
92 case COM_RD_SEC_MUL:
93 return "COM_RD_SEC_MUL";
94
95 case COM_WR_SEC_WP:
96 return "COM_WR_SEC_WP";
97
98 case COM_WR_SEC:
99 return "COM_WR_SEC";
100
101 case COM_WR_TRA_WP:
102 return "COM_WR_TRA_WP";
103
104 case COM_WR_TRA:
105 return "COM_WR_TRA";
106
107 default:
108 fail("unknown command 0x%02x", com);
109 }
110}
111
112static void stat_string(int32_t stat, char *buff) {
113 buff[0] = 0;
114
115 if ((stat & 0x80) != 0) {
116 strcat(buff, " mot_on");
117 }
118
119 if ((stat & 0x04) != 0) {
120 strcat(buff, " zero");
121 }
122
123 if ((stat & 0x02) != 0) {
124 strcat(buff, " dat_req");
125 }
126
127 if ((stat & 0x01) != 0) {
128 strcat(buff, " busy");
129 }
130}
131
132void fdd_set_side(int32_t sid)
133{
134 ver2("sid <- %d", sid);
135 state.sid = sid;
136}
137
138void fdd_set_sel(int32_t sel)
139{
140 ver2("sel <- %d", sel);
141}
142
143void fdd_init(void)
144{
145 ver("fdd init");
146 inf("reading disk image file %s", disk);
147
148 SDL_RWops *ops = SDL_RWFromFile(disk, "rb");
149
150 if (ops == NULL) {
151 fail("error while opening disk image file %s for reading", disk);
152 }
153
154 size_t loaded = 0;
155
156 while (loaded < SZ_DISK) {
157 size_t n_rd = SDL_RWread(ops, image + loaded, 1, SZ_DISK - loaded);
158
159 if (n_rd == 0) {
160 fail("error while reading disk image file %s", disk);
161 }
162
163 loaded += n_rd;
164 }
165
166 SDL_RWclose(ops);
167}
168
169void fdd_quit(void)
170{
171 ver("fdd quit");
172 inf("writing disk image file %s", disk);
173
174 SDL_RWops *ops = SDL_RWFromFile(disk, "wb");
175
176 if (ops == NULL) {
177 fail("error while opening disk image file %s for writing", disk);
178 }
179
180 size_t stored = 0;
181
182 while (stored < SZ_DISK) {
183 size_t n_wr = SDL_RWwrite(ops, image + stored, 1, SZ_DISK - stored);
184
185 if (n_wr == 0) {
186 fail("error while writing disk image file %s", disk);
187 }
188
189 stored += n_wr;
190 }
191
192 SDL_RWclose(ops);
193}
194
195bool fdd_exec(void)
196{
197 ver3("fdd exec");
198
199 switch (state.step) {
200 case STEP_IDLE:
201 break;
202
203 case STEP_PREP:
204 ver3("prep %d", state.cyc);
205 --state.cyc;
206
207 if (state.cyc == 0) {
208 ver2("exec %s", com_string(state.com));
209 state.step = STEP_EXEC;
210 state.cyc = COM_EXE_CYC;
211 }
212
213 break;
214
215 case STEP_EXEC:
216 ver3("exec %d", state.cyc);
217 --state.cyc;
218
219 if (state.cyc == 0) {
220 ver2("idle %s", com_string(state.com));
221 state.step = STEP_IDLE;
222 }
223
224 break;
225 }
226
227 return false;
228}
229
230uint32_t fdd_read(uint32_t off, int32_t sz)
231{
232 ver3("fdd rd %u:%d", off, sz * 8);
233
234 if (sz != 1 || off > 3) {
235 fail("invalid fdd rd %u:%d", off, sz * 8);
236 }
237
238 uint32_t rv;
239
240 switch (off) {
241 case REG_COM_STAT:
242 rv = 0x80; // motor on
243
244 if (state.step == STEP_EXEC) {
245 rv |= 0x01; // busy
246
247 switch (state.com) {
248 case COM_RD_SEC:
249 case COM_RD_SEC_MUL:
250 case COM_WR_SEC:
251 case COM_WR_SEC_WP:
252 rv |= 0x02; // data request
253 break;
254 }
255 }
256
257 if (state.tra_0) {
258 rv |= 0x04; // track zero
259 }
260
261 char stat[100];
262 stat_string((int32_t)rv, stat);
263 ver3("stat -> 0x%02x%s", rv, stat);
264 break;
265
266 case REG_TRA:
267 rv = (uint32_t)state.reg_tra;
268 ver2("tra -> %u", rv);
269 break;
270
271 case REG_SEC:
272 rv = (uint32_t)state.reg_sec;
273 ver2("sec -> %u", rv);
274 break;
275
276 case REG_DAT:
277 if (state.step != STEP_EXEC ||
278 (state.com != COM_RD_SEC && state.com != COM_RD_SEC_MUL)) {
279 fail("unexpected data register read");
280 }
281
282 rv = *state.dat;
283 int32_t addr = (int32_t)(state.dat - image);
284
285 if ((addr & (SZ_SEC - 1)) == 0) {
286 ver2("addr 0x%06x -> 0x%02x", addr, rv);
287 }
288 else {
289 ver3("addr 0x%06x -> 0x%02x", addr, rv);
290 }
291
292 ++state.dat;
293 ++addr;
294
295 if ((addr & (SZ_SEC - 1)) == 0 && state.com == COM_RD_SEC) {
296 state.step = STEP_IDLE;
297 state.cyc = 0;
298 }
299 else {
300 state.cyc = COM_EXE_CYC;
301 }
302
303 break;
304
305 default:
306 rv = 0;
307 break;
308 }
309
310 return rv;
311}
312
313void fdd_write(uint32_t off, int32_t sz, uint32_t val)
314{
315 ver3("fdd wr %u:%d 0x%0*x", off, sz * 8, sz * 2, val);
316
317 if (sz != 1 || off > 3) {
318 fail("invalid fdd wr %u:%d", off, sz * 8);
319 }
320
321 switch (off) {
322 case REG_COM_STAT:
323 ver2("com <- 0x%02x, tra %d, sid %d, sec %d",
324 val, state.reg_tra, state.sid, state.reg_sec);
325
326 state.com = (int32_t)val;
327
328 ver2("prep %s", com_string(state.com));
329 state.step = STEP_PREP;
330 state.cyc = COM_LAT_CYC;
331
332 switch (val) {
333 case COM_REST:
334 state.reg_tra = 0;
335 state.tra_0 = true;
336 state.dat = NULL;
337 break;
338
339 case COM_SEEK:
340 case COM_SEEK_VER:
341 state.reg_tra = state.reg_dat;
342 state.tra_0 = state.reg_tra == 0;
343 state.dat = NULL;
344 break;
345
346 case COM_RD_SEC:
347 case COM_RD_SEC_MUL:
348 case COM_WR_SEC:
349 case COM_WR_SEC_WP: {
350 size_t sec_off = (size_t)(((state.reg_tra * N_SID + state.sid) * N_SEC +
351 state.reg_sec - 1) * SZ_SEC);
352 state.dat = image + sec_off;
353 state.tra_0 = false;
354 break;
355 }
356
357 case COM_INT:
358 state.step = STEP_IDLE;
359 state.cyc = 0;
360 state.dat = NULL;
361 state.tra_0 = false;
362 break;
363
364 case COM_WR_TRA:
365 case COM_WR_TRA_WP:
366 state.tra_0 = false;
367 fail("format not yet supported");
368 break;
369 }
370
371 break;
372
373 case REG_TRA:
374 state.reg_tra = (int32_t)val;
375 ver2("tra <- %u", val);
376 break;
377
378 case REG_SEC:
379 state.reg_sec = (int32_t)val;
380 ver2("sec <- %u", val);
381 break;
382
383 case REG_DAT:
384 if (state.step == STEP_EXEC &&
385 (state.com == COM_WR_SEC || state.com == COM_WR_SEC_WP)) {
386 *state.dat = (uint8_t)val;
387 int32_t addr = (int32_t)(state.dat - image);
388
389 if ((addr & (SZ_SEC - 1)) == 0) {
390 ver2("addr 0x%06x <- 0x%02x", addr, val);
391 }
392 else {
393 ver3("addr 0x%06x <- 0x%02x", addr, val);
394 }
395
396 ++state.dat;
397 ++addr;
398
399 if ((addr & (SZ_SEC - 1)) == 0) {
400 state.step = STEP_IDLE;
401 state.cyc = 0;
402 }
403 else {
404 state.cyc = COM_EXE_CYC;
405 }
406 }
407 else {
408 state.reg_dat = (int32_t)val;
409 ver2("dat <- 0x%02x", val);
410 }
411
412 break;
413
414 default:
415 break;
416 }
417}
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