1 | /*
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2 | * Copyright (C) 2017 The Contributors
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3 | *
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4 | * This program is free software: you can redistribute it and/or modify
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5 | * it under the terms of the GNU General Public License as published by
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6 | * the Free Software Foundation, either version 3 of the License, or (at
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7 | * your option) any later version.
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8 | *
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9 | * This program is distributed in the hope that it will be useful, but
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10 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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12 | * General Public License for more details.
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13 | *
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14 | * A copy of the GNU General Public License can be found in the file
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15 | * "gpl.txt" in the top directory of this repository.
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16 | */
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17 |
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18 | #include <all.h>
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19 |
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20 | #define ver(...) _ver(tim_verbose, 0, __VA_ARGS__)
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21 | #define ver2(...) _ver(tim_verbose, 1, __VA_ARGS__)
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22 | #define ver3(...) _ver(tim_verbose, 2, __VA_ARGS__)
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23 |
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24 | typedef struct {
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25 | uint32_t irq;
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26 | bool run;
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27 | uint32_t latch;
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28 | uint32_t count;
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29 | } state_timer;
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30 |
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31 | static state_timer timers[] = {
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32 | {.irq = 0, .run = false, .latch = 32, .count = 32},
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33 | {.irq = 0, .run = false, .latch = 3200, .count = 3200},
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34 | {.irq = 0, .run = false, .latch = 801, .count = 801}
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35 | };
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36 |
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37 | #define REG_CRX 0
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38 | #define REG_CR2 1
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39 | #define REG_T1H 2
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40 | #define REG_T1L 3
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41 | #define REG_T2H 4
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42 | #define REG_T2L 5
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43 | #define REG_T3H 6
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44 | #define REG_T3L 7
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45 |
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46 | int32_t tim_verbose = 0;
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47 |
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48 | void tim_init(void)
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49 | {
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50 | ver("tim init");
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51 | }
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52 |
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53 | void tim_quit(void)
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54 | {
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55 | ver("tim quit");
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56 | }
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57 |
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58 | bool tim_exec(void)
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59 | {
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60 | for (int32_t i = 0; i < ARRAY_COUNT(timers); ++i) {
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61 | if(timers[i].run == true) {
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62 | --timers[i].count;
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63 | if(timers[i].count == 0) {
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64 | timers[i].count = timers[i].latch;
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65 | timers[i].irq = 1;
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66 | }
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67 | //ver2("tim%d %u", i, timers[i].count);
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68 | }
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69 | }
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70 |
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71 | return timers[0].irq || timers[1].irq || timers[2].irq;
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72 | }
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73 |
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74 | uint32_t tim_read(uint32_t off, int32_t sz)
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75 | {
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76 | ver2("tim rd %u:%d", off, sz * 8);
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77 | uint32_t rv;
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78 | rv = 0;
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79 | switch(off) {
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80 | case REG_CRX:
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81 | break;
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82 |
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83 | case REG_CR2:
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84 | rv |= (timers[0].irq << 0);
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85 | rv |= (timers[1].irq << 1);
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86 | rv |= (timers[2].irq << 2);
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87 | ver2("tim plc %u fc %u rtc %u", timers[0].irq, timers[1].irq, timers[2].irq);
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88 | //ver2("tim rv %u", rv);
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89 | break;
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90 |
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91 | case REG_T1H:
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92 | rv = 0;
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93 | break;
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94 |
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95 | case REG_T1L:
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96 | rv = 31;
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97 | timers[0].irq = 0;
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98 | break;
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99 |
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100 | case REG_T2H:
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101 | rv = 12;
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102 | break;
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103 |
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104 | case REG_T2L:
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105 | rv = 127;
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106 | timers[1].irq = 0;
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107 | break;
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108 |
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109 | case REG_T3H:
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110 | rv = 3;
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111 | break;
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112 |
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113 | case REG_T3L:
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114 | rv = 32;
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115 | timers[2].irq = 0;
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116 | break;
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117 |
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118 | default:
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119 | break;
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120 | }
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121 |
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122 | return rv;
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123 | }
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124 |
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125 | void tim_write(uint32_t off, int32_t sz, uint32_t val)
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126 | {
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127 | ver2("tim wr %u:%d 0x%0*x", off, sz * 8, sz * 2, val);
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128 | if( off == 0 && (val & (1 << 7)) ) {
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129 | timers[0].run = true;
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130 | timers[1].run = true;
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131 | timers[2].run = true;
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132 | }
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133 | }
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