Changeset 10afc24 in buchla-68k

Timestamp:

07/02/2017 12:33:42 AM (7 years ago)

Author:

Thomas Lopatic <thomas@…>

Branches:

master

Children:

66b48e7

Parents:

0cfc372

Message:

Consistent library order.

File:

• Makefile (modified) (5 diffs)

Makefile

@@ -43 +43 @@
                                 rm -f prolog.a
                                 $(CROSS_AR) rcs prolog.a $(PROLOG_OBJ)
-
-IOLIB_C :=              dofmt.c mdump.c pause.c printf.c rawio.c sprintf.c waitcr.c
-IOLIB_S :=              hwdefs.s rtraps.s setipl.s setsr.s traps.s
-
-IOLIB_CO :=             $(IOLIB_C:.c=.o)
-IOLIB_SO :=             $(IOLIB_S:.s=.o)
-IOLIB_OBJ :=    $(IOLIB_CO:%=build/%) $(IOLIB_SO:%=build/%)
-
-build/%.o:              iolib/%.c $(HEADERS) | build
-                                $(CROSS_GCC) $(FLAGS_COM) -c -o $@ $<
-                                $(CROSS_OBJC) --redefine-syms misc/rewrite.txt $@
-
-build/%.o:              iolib/%.s $(HEADERS) | build
-                                $(CROSS_GCC) $(FLAGS_ASM) -c -o $@ $<
-
-iolib.a:                $(IOLIB_OBJ)
-                                rm -f iolib.a
-                                $(CROSS_AR) rcs iolib.a $(IOLIB_OBJ)
 
 LIBCIO_C :=             atoi.c atol.c blkrd.c blkwr.c close.c clusmap.c conin.c conwr.c \
@@ -86 +68 @@
                                 $(CROSS_AR) rcs libcio.a $(LIBCIO_OBJ)
 
+VLIB_C :=               cg2.c cg3.c glcinit.c lseg.c vbfill4.c vclrs.c vhinit.c vmput.c \
+                                vobjfns.c vputs.c vputsv.c vsetpal.c vsinit.c vspray4.c vtext.c \
+                                vwputm.c
+
+VLIB_S :=               acctrl.s glcplot.s tsplot4.s vbank.s vclrav.s vcputs.s vcputsv.s \
+                                viint.s vputa.s vputc.s vputcv.s vputp.s vsetav.s vsetcv.s vsplot4.s \
+                                vvputsv.s vwputp.s vwputs.s
+
+VLIB_CO :=              $(VLIB_C:.c=.o)
+VLIB_SO :=              $(VLIB_S:.s=.o)
+VLIB_OBJ :=             $(VLIB_CO:%=build/%) $(VLIB_SO:%=build/%)
+
+build/%.o:              vlib/%.c $(HEADERS) | build
+                                $(CROSS_GCC) $(FLAGS_COM) -c -o $@ $<
+                                $(CROSS_OBJC) --redefine-syms misc/rewrite.txt $@
+
+build/%.o:              vlib/%.s $(HEADERS) | build
+                                $(CROSS_GCC) $(FLAGS_ASM) -c -o $@ $<
+
+vlib.a:                 $(VLIB_OBJ)
+                                rm -f vlib.a
+                                $(CROSS_AR) rcs vlib.a $(VLIB_OBJ)
+
+IOLIB_C :=              dofmt.c mdump.c pause.c printf.c rawio.c sprintf.c waitcr.c
+IOLIB_S :=              hwdefs.s rtraps.s setipl.s setsr.s traps.s
+
+IOLIB_CO :=             $(IOLIB_C:.c=.o)
+IOLIB_SO :=             $(IOLIB_S:.s=.o)
+IOLIB_OBJ :=    $(IOLIB_CO:%=build/%) $(IOLIB_SO:%=build/%)
+
+build/%.o:              iolib/%.c $(HEADERS) | build
+                                $(CROSS_GCC) $(FLAGS_COM) -c -o $@ $<
+                                $(CROSS_OBJC) --redefine-syms misc/rewrite.txt $@
+
+build/%.o:              iolib/%.s $(HEADERS) | build
+                                $(CROSS_GCC) $(FLAGS_ASM) -c -o $@ $<
+
+iolib.a:                $(IOLIB_OBJ)
+                                rm -f iolib.a
+                                $(CROSS_AR) rcs iolib.a $(IOLIB_OBJ)
+
 LIBSM_C :=              index.c memccpy.c memchr.c memcmp.c memcmpu.c memcpy.c memcpyw.c \
                                 memset.c memsetw.c rindex.c str2lc.c str2uc.c strcat.c strccpy.c \
@@ -123 +146 @@
                                 $(CROSS_AR) rcs lib700.a $(LIB700_OBJ)
 
-VLIB_C :=               cg2.c cg3.c glcinit.c lseg.c vbfill4.c vclrs.c vhinit.c vmput.c \
-                                vobjfns.c vputs.c vputsv.c vsetpal.c vsinit.c vspray4.c vtext.c \
-                                vwputm.c
-
-VLIB_S :=               acctrl.s glcplot.s tsplot4.s vbank.s vclrav.s vcputs.s vcputsv.s \
-                                viint.s vputa.s vputc.s vputcv.s vputp.s vsetav.s vsetcv.s vsplot4.s \
-                                vvputsv.s vwputp.s vwputs.s
-
-VLIB_CO :=              $(VLIB_C:.c=.o)
-VLIB_SO :=              $(VLIB_S:.s=.o)
-VLIB_OBJ :=             $(VLIB_CO:%=build/%) $(VLIB_SO:%=build/%)
-
-build/%.o:              vlib/%.c $(HEADERS) | build
-                                $(CROSS_GCC) $(FLAGS_COM) -c -o $@ $<
-                                $(CROSS_OBJC) --redefine-syms misc/rewrite.txt $@
-
-build/%.o:              vlib/%.s $(HEADERS) | build
-                                $(CROSS_GCC) $(FLAGS_ASM) -c -o $@ $<
-
-vlib.a:                 $(VLIB_OBJ)
-                                rm -f vlib.a
-                                $(CROSS_AR) rcs vlib.a $(VLIB_OBJ)
-
 ROM_C :=                booter.c romp.c
 ROM_S :=                bios.s timeint.s
@@ -167 +167 @@
 
 rom.abs:                $(ROM_OBJ) \
-                                prolog.a iolib.a libcio.a libsm.a lib700.a vlib.a
+                                prolog.a libcio.a vlib.a iolib.a libsm.a lib700.a
                                 $(CROSS_GCC) $(FLAGS_LNK) -Wl,--script,misc/rom.ld,--entry,0x100000 \
                                 -o rom.abs $(ROM_OBJ) \
@@ -206 +206 @@
 
 midas.abs:              $(LOWRAM_OBJ) prolog.a $(RAM_OBJ) \
-                                iolib.a libcio.a libsm.a lib700.a vlib.a
+                                libcio.a vlib.a iolib.a libsm.a lib700.a
                                 $(CROSS_GCC) $(FLAGS_LNK) -Wl,--script,misc/ram.ld,--entry,0x10000 \
                                 -o midas.abs $(LOWRAM_OBJ) prolog.a $(RAM_OBJ) \