- Timestamp:
- 08/02/2017 10:40:36 PM (7 years ago)
- Branches:
- master
- Children:
- 9e0cd12
- Parents:
- 212bc4c
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
emu/tim.c
r212bc4c r52c8401 68 68 } 69 69 } 70 70 71 return timers[0].irq || timers[1].irq || timers[2].irq; 71 72 } … … 79 80 case REG_CRX: 80 81 break; 82 81 83 case REG_CR2: 82 84 rv |= (timers[0].irq << 0); … … 86 88 //ver2("tim rv %u", rv); 87 89 break; 90 88 91 case REG_T1H: 89 92 rv = 0; 90 93 break; 94 91 95 case REG_T1L: 92 96 rv = 31; 93 97 timers[0].irq = 0; 94 98 break; 99 95 100 case REG_T2H: 96 101 rv = 12; 97 102 break; 103 98 104 case REG_T2L: 99 105 rv = 127; 100 106 timers[1].irq = 0; 101 107 break; 108 102 109 case REG_T3H: 103 110 rv = 3; 104 111 break; 112 105 113 case REG_T3L: 106 114 rv = 32; 107 115 timers[2].irq = 0; 108 116 break; 117 109 118 default: 110 119 break; 111 120 } 121 112 122 return rv; 113 123 }
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