Index: emu/cpu.c
===================================================================
--- emu/cpu.c	(revision ff8d800308997707a2040c22e309bbd0585ee959)
+++ emu/cpu.c	(revision a06aa8be3631490d2ce602f681044034ba655137)
@@ -1,2 +1,19 @@
+/*
+ *  Copyright (C) 2017 The Contributors
+ *
+ *  This program is free software: you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation, either version 3 of the License, or (at
+ *  your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful, but
+ *  WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ *  General Public License for more details.
+ *
+ *  A copy of the GNU General Public License can be found in the file
+ *  "gpl-v3.txt" in the top directory of this repository.
+ */
+
 #include <all.h>
 
@@ -7,48 +24,154 @@
 }
 
+bool cpu_verbose = false;
+
 #define CYCLES 10
 
-#define RESET_PC 0x100000
-#define RESET_SP 0x100000
-
-bool cpu_verbose = false;
+#define RAM_START 0x0
+#define RAM_SIZE 0x100000
+
+#define ROM_START 0x100000
+#define ROM_SIZE 0x10000
+
+#define RESET_SP ROM_START
+#define RESET_PC ROM_START
+
+typedef void (*hw_init_t)(void);
+typedef void (*hw_quit_t)(void);
+typedef void (*hw_exec_t)(void);
+typedef uint32_t (*hw_read_t)(uint32_t off, int32_t sz);
+typedef void (*hw_write_t)(uint32_t off, int32_t sz, uint32_t val);
+
+typedef struct {
+	uint32_t addr_beg;
+	uint32_t addr_end;
+	hw_init_t init;
+	hw_quit_t quit;
+	hw_exec_t exec;
+	hw_read_t read;
+	hw_write_t write;
+} hw_t;
+
 static bool reset = true;
 
+static uint8_t ram_data[RAM_SIZE];
+static uint8_t rom_data[ROM_SIZE];
+
+static uint32_t ram_rd_beg;
+static uint32_t ram_rd_end;
+static uint32_t ram_wr_beg;
+static uint32_t ram_wr_end;
+
+static uint32_t rom_rd_beg;
+static uint32_t rom_rd_end;
+static uint32_t rom_wr_beg;
+static uint32_t rom_wr_end;
+
+static hw_t hw_map[] = {
+	{ 0x180000, 0x200000, fpu_init, fpu_quit, fpu_exec, fpu_read, fpu_write },
+	{ 0x200000, 0x280000, vid_init, vid_quit, vid_exec, vid_read, vid_write },
+	{ 0x3a0001, 0x3a4001, tim_init, tim_quit, tim_exec, tim_read, tim_write },
+	{ 0x3a4001, 0x3a8001, lcd_init, lcd_quit, lcd_exec, lcd_read, lcd_write },
+	{ 0x3a8001, 0x3ac001, ser_init, ser_quit, ser_exec, ser_read, ser_write },
+	{ 0x3ac001, 0x3b0001, mid_init, mid_quit, mid_exec, mid_read, mid_write },
+	{ 0x3b0001, 0x3b4001, fdd_init, fdd_quit, fdd_exec, fdd_read, fdd_write },
+	{ 0x3b4001, 0x3b8001, snd_init, snd_quit, snd_exec, snd_read, snd_write },
+	{ 0x3b8001, 0x3bc001, led_init, led_quit, led_exec, led_read, led_write },
+	{ 0x3bc001, 0x3c0001, kbd_init, kbd_quit, kbd_exec, kbd_read, kbd_write }
+};
+
+static hw_t *hw_by_addr(uint32_t addr)
+{
+	for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
+		if (addr >= hw_map[i].addr_beg && addr < hw_map[i].addr_end) {
+			return hw_map + i;
+		}
+	}
+
+	return NULL;
+}
+
+static void hw_init(void)
+{
+	for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
+		hw_map[i].init();
+	}
+}
+
+static void hw_exec(void)
+{
+	for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
+		hw_map[i].exec();
+	}
+}
+
+static uint32_t hw_off(hw_t *hw, uint32_t addr)
+{
+	if ((hw->addr_beg & 0x1) == 0) {
+		return addr - hw->addr_beg;
+	}
+
+	return (addr - hw->addr_beg) / 2;
+}
+
 uint32_t m68k_read_disassembler_8(uint32_t addr)
 {
+	return m68k_read_memory_8(addr);
+}
+
+uint32_t m68k_read_disassembler_16(uint32_t addr)
+{
+	return m68k_read_memory_16(addr);
+}
+
+uint32_t m68k_read_disassembler_32(uint32_t addr)
+{
+	return m68k_read_memory_32(addr);
+}
+
+uint32_t m68k_read_memory_8(uint32_t addr)
+{
 	ver("mem rd 0x%08x:8", addr);
-	return 0;
-}
-
-uint32_t m68k_read_disassembler_16(uint32_t addr)
+
+	if (addr >= ram_rd_beg && addr <= ram_rd_end - 1) {
+		return ram_data[addr - RAM_START];
+	}
+
+	if (addr >= rom_rd_beg && addr <= rom_rd_end - 1) {
+		return rom_data[addr - ROM_START];
+	}
+
+	hw_t *hw = hw_by_addr(addr);
+
+	if (hw != NULL) {
+		return hw->read(hw_off(hw, addr), 1);
+	}
+
+	fail("invalid read 0x%08x:8", addr);
+}
+
+uint32_t m68k_read_memory_16(uint32_t addr)
 {
 	ver("mem rd 0x%08x:16", addr);
-	return 0;
-}
-
-uint32_t m68k_read_disassembler_32(uint32_t addr)
-{
-	ver("mem rd 0x%08x:32", addr);
-	return 0;
-}
-
-uint32_t m68k_read_memory_8(uint32_t addr)
-{
-	ver("mem rd 0x%08x:8", addr);
-	return 0;
-}
-
-uint32_t m68k_read_memory_16(uint32_t addr)
-{
-	ver("mem rd 0x%08x:16", addr);
-
-	if (addr < 0x100000) {
-	}
-
-	if (addr < 0x110000) {
-		return 0x60fe;
-	}
-
-	return 0;
+
+	if (addr >= ram_rd_beg && addr <= ram_rd_end - 2) {
+		return
+				((uint32_t)ram_data[addr - RAM_START + 0] << 8) |
+				((uint32_t)ram_data[addr - RAM_START + 1] << 0);
+	}
+
+	if (addr >= rom_rd_beg && addr <= rom_rd_end - 2) {
+		return
+				((uint32_t)rom_data[addr - ROM_START + 0] << 8) |
+				((uint32_t)rom_data[addr - ROM_START + 1] << 0);
+	}
+
+	hw_t *hw = hw_by_addr(addr);
+
+	if (hw != NULL) {
+		return hw->read(hw_off(hw, addr), 2);
+	}
+
+	fail("invalid read 0x%08x:16", addr);
 }
 
@@ -70,5 +193,27 @@
 	}
 
-	return 0;
+	if (addr >= ram_rd_beg && addr <= ram_rd_end - 4) {
+		return
+				((uint32_t)ram_data[addr - RAM_START + 0] << 24) |
+				((uint32_t)ram_data[addr - RAM_START + 1] << 16) |
+				((uint32_t)ram_data[addr - RAM_START + 2] <<  8) |
+				((uint32_t)ram_data[addr - RAM_START + 3] <<  0);
+	}
+
+	if (addr >= rom_rd_beg && addr <= rom_rd_end - 4) {
+		return
+				((uint32_t)rom_data[addr - ROM_START + 0] << 24) |
+				((uint32_t)rom_data[addr - ROM_START + 1] << 16) |
+				((uint32_t)rom_data[addr - ROM_START + 2] <<  8) |
+				((uint32_t)rom_data[addr - ROM_START + 3] <<  0);
+	}
+
+	hw_t *hw = hw_by_addr(addr);
+
+	if (hw != NULL) {
+		return hw->read(hw_off(hw, addr), 4);
+	}
+
+	fail("invalid read 0x%08x:32", addr);
 }
 
@@ -76,4 +221,24 @@
 {
 	ver("mem wr 0x%08x:8 0x%02x", addr, val);
+
+	if (addr >= ram_wr_beg && addr <= ram_wr_end - 1) {
+		ram_data[addr - RAM_START] = (uint8_t)val;
+		return;
+	}
+
+	if (addr >= rom_wr_beg && addr <= rom_wr_end - 1) {
+		// ROM has its BSS section in RAM.
+		ram_data[addr - RAM_START] = (uint8_t)val;
+		return;
+	}
+
+	hw_t *hw = hw_by_addr(addr);
+
+	if (hw != NULL) {
+		hw->write(hw_off(hw, addr), 1, val);
+		return;
+	}
+
+	fail("invalid write 0x%08x:8 0x%02x", addr, val);
 }
 
@@ -81,4 +246,26 @@
 {
 	ver("mem wr 0x%08x:16 0x%04x", addr, val);
+
+	if (addr >= ram_wr_beg && addr <= ram_wr_end - 2) {
+		ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 8);
+		ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 0);
+		return;
+	}
+
+	if (addr >= rom_wr_beg && addr <= rom_wr_end - 2) {
+		// ROM has its BSS section in RAM.
+		ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 8);
+		ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 0);
+		return;
+	}
+
+	hw_t *hw = hw_by_addr(addr);
+
+	if (hw != NULL) {
+		hw->write(hw_off(hw, addr), 2, val);
+		return;
+	}
+
+	fail("invalid write 0x%08x:16 0x%04x", addr, val);
 }
 
@@ -86,16 +273,45 @@
 {
 	ver("mem wr 0x%08x:32 0x%08x", addr, val);
+
+	if (addr >= ram_wr_beg && addr <= ram_wr_end - 4) {
+		ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 24);
+		ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 16);
+		ram_data[addr - RAM_START + 2] = (uint8_t)(val >>  8);
+		ram_data[addr - RAM_START + 3] = (uint8_t)(val >>  0);
+		return;
+	}
+
+	if (addr >= rom_wr_beg && addr <= rom_wr_end - 4) {
+		// ROM has its BSS section in RAM.
+		ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 24);
+		ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 16);
+		ram_data[addr - RAM_START + 2] = (uint8_t)(val >>  8);
+		ram_data[addr - RAM_START + 3] = (uint8_t)(val >>  0);
+		return;
+	}
+
+	hw_t *hw = hw_by_addr(addr);
+
+	if (hw != NULL) {
+		hw->write(hw_off(hw, addr), 4, val);
+		return;
+	}
+
+	fail("invalid write 0x%08x:32 0x%08x", addr, val);
 }
 
 void cpu_loop(void)
 {
-	ver("entering CPU loop");
-
+	ver("initializing hardware");
+	hw_init();
+
+	ver("starting CPU");
 	m68k_init();
 	m68k_set_cpu_type(M68K_CPU_TYPE_68000);
 	m68k_pulse_reset();
 
-	for (int32_t i = 0; i < 5; ++i) {
+	for (int32_t c = 0; c < 5; ++c) {
 		m68k_execute(CYCLES);
-	}
-}
+		hw_exec();
+	}
+}
