| [4f508e6] | 1 | | ------------------------------------------------------------------------------
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| 2 | | rand24.s -- generate a 24 bit random number
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| 3 | | Version 3 -- 1988-04-29 -- D.N. Lynx Crowe
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| 4 | | ------------------------------------------------------------------------------
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| 5 | | Synopsis:
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| 6 | | long
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| 7 | | rand24()
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| 8 |
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| 9 | | Based on:
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| 10 | | Knuth, Donald E.
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| 11 | | The Art of Computer Programming,
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| 12 | | Volume 2: Semi-Numerical Algorithms
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| 13 |
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| 14 | | Computes:
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| 15 | | S = [S | C] + K
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| 16 |
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| 17 | | Where:
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| 18 | | K = 1
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| 19 | | C = 3141592621
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| 20 | | S = the seed (if zero, it gets set from the 200 Hz clock)
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| 21 |
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| 22 | | Returns:
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| 23 | | S >> 8 (a 24 bit pseudo-random number)
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| 24 |
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| 25 | | Note: this function has an LSB with an exactly 50% distribution, so using
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| 26 | | individual bits is probably not a good idea. Using more bits makes things
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| 27 | | appear more random.
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| 28 | | ------------------------------------------------------------------------------
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| [f40a309] | 29 | .text
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| [4f508e6] | 30 |
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| [f40a309] | 31 | .xdef _rand24
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| [4f508e6] | 32 |
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| [f40a309] | 33 | .xdef _rseed
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| [4f508e6] | 34 |
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| 35 | | equates for things in the BIOS
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| 36 |
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| 37 | RCLOCK = 0x49E | LONG - 200 Hz clock
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| 38 |
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| 39 | | equates for stack offsets
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| 40 |
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| 41 | ARG1 = 8 | LONG / WORD - arg1 / MS bits
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| 42 | ARG1L = 10 | WORD - arg1 LS bits
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| 43 | ARG2 = 12 | LONG / WORD - arg2 / MS bits
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| 44 | ARG2L = 14 | WORD - arg2 LS bits
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| 45 |
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| 46 | PART = -4 | LONG - partial product
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| 47 |
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| 48 | PI = 0xBB40E62D | LONG - PI as a hex value
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| 49 |
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| [f40a309] | 50 | .page
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| [4f508e6] | 51 |
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| 52 | | mult32 -- 32 bit signed multiply
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| 53 | | ------ ----------------------
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| 54 | mult32: link a6,#-4 | link stack frames
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| 55 | clr.w d2 | clear sign flags
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| 56 | tst.l ARG1(a6) | check sign of 1st argument
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| 57 | bge mult32a | ...
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| 58 |
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| 59 | neg.l ARG1(a6) | make 1st argument positive
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| 60 | addq.w #1,d2 | log its sign as negative
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| 61 |
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| 62 | mult32a: tst.l ARG2(a6) | check sign of 2nd argument
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| 63 | bge mult32b | ...
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| 64 |
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| 65 | neg.l ARG2(a6) | make 2nd argument positive
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| 66 | addq.w #1,d2 | log its sign as negative
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| 67 |
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| 68 | mult32b: move.w ARG1L(a6),d0 | generate 1st partial product
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| 69 | mulu ARG2L(a6),d0 | ...
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| 70 | move.l d0,PART(a6) | ...
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| 71 | move.w ARG1(a6),d0 | generate 2nd partial product
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| 72 | mulu ARG2L(a6),d0 | ...
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| 73 | move.w ARG2(a6),d1 | generate 3rd partial product
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| 74 | mulu ARG1L(a6),d1 | ...
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| 75 | add.w d1,d0 | add partial products
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| 76 | add.w PART(a6),d0 | ...
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| 77 | move.w d0,PART(a6) | ...
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| 78 | move.l PART(a6),d0 | ...
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| 79 | btst #0,d2 | adjust sign of result
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| 80 | beq mult32c | ...
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| 81 |
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| 82 | neg.l d0 | ...
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| 83 |
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| 84 | mult32c: unlk a6 | unlink stack frames
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| 85 | rts | return
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| 86 |
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| [f40a309] | 87 | .page
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| [4f508e6] | 88 |
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| 89 | | _rand24 -- Generate a random number
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| 90 | | ------- ------------------------
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| 91 | _rand24: link a6,#0 | Link stack frames
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| 92 | tst.l _rseed | See if the seed is zero
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| 93 | bne rand01 | Jump if not
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| 94 |
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| 95 | move.l RCLOCK,d0 | Pick up the 200 Hz clock
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| 96 | moveq.l #16,d1 | Shift it left
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| 97 | asl.l d1,d0 | ...
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| 98 | or.l RCLOCK,d0 | OR in current 200 Hz clock
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| 99 | move.l d0,_rseed | Use that as the seed
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| 100 |
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| 101 | rand01: move.l #PI,-(a7) | Put PI on the stack
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| 102 | move.l _rseed,-(a7) | ... and _rseed, too
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| 103 | bsr mult32 | Multiply them
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| 104 | addq.l #8,a7 | Cleanup stack
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| 105 | addq.l #1,d0 | Add 1 to the result
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| 106 | move.l d0,_rseed | Save as new seed
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| 107 | asr.l #8,d0 | Make it a 24 bit number
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| 108 | and.l #0x00FFFFFF,d0 | ...
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| 109 | unlk a6 | Unlink stack frames
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| 110 | rts | Return to caller
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| 111 |
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| 112 | | ------------------------------------------------------------------------------
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| [f40a309] | 113 | .bss
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| [4f508e6] | 114 | | ------------------------------------------------------------------------------
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| 115 |
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| 116 | _rseed: .ds.l 1 | random number seed
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| 117 |
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| [f40a309] | 118 | .end
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