Changeset 4f508e6 in buchla-68k
- Timestamp:
- 07/01/2017 02:34:46 PM (5 years ago)
- Branches:
- master
- Children:
- 08e1da1
- Parents:
- f40a309
- Files:
-
- 2 added
- 50 edited
Legend:
- Unmodified
- Added
- Removed
-
iolib/hwdefs.s
rf40a309 r4f508e6 1 *------------------------------------------------------------------------------2 *hwdefs.s -- External definitions of Buchla 700 I/O addresses3 *Version 14 -- 1988-08-15 -- D.N. Lynx Crowe4 *------------------------------------------------------------------------------1 | ------------------------------------------------------------------------------ 2 | hwdefs.s -- External definitions of Buchla 700 I/O addresses 3 | Version 14 -- 1988-08-15 -- D.N. Lynx Crowe 4 | ------------------------------------------------------------------------------ 5 5 .text 6 * 6 7 7 .xdef _io_time,_io_lcd,_io_ser,_io_midi 8 8 .xdef _io_disk,_io_tone,_io_leds,_io_kbrd 9 9 .xdef _io_vreg,_io_vraw,_io_vram,_io_fpu 10 10 .xdef _lcd_a0,_lcd_a1 11 * 11 12 12 .xdef _v_regs,_v_odtab,_v_actab 13 13 .xdef _v_ct0 14 14 .xdef _v_gt1 15 15 .xdef _v_score,_v_cgtab 16 * 16 17 17 .xdef _v_curs0,_v_curs1,_v_curs2,_v_curs3 18 18 .xdef _v_curs4,_v_curs5,_v_curs6,_v_curs7 … … 20 20 .xdef _v_win0 21 21 .xdef _v_cur 22 * 22 23 23 .xdef _fc_sw,_fc_val 24 * 25 *------------------------------------------------------------------------------26 * 27 *Hardware base addresses28 *-----------------------29 _io_fpu .equ $180000 *FPU base address30 * 31 VB .equ $200000 *VSDD base address32 * 33 _io_time .equ $3A0001 *Timer chip34 _io_lcd .equ $3A4001 *LCD controller35 _io_ser .equ $3A8001 *Serial ports (RS232)36 _io_midi .equ $3AC001 *MIDI ports37 _io_disk .equ $3B0001 *Disk controller38 _io_tone .equ $3B4001 *Sound generator chip39 _io_leds .equ $3B8001 *LED driver40 _io_kbrd .equ $3BC001 *Keyboard / panel processor41 * 42 _lcd_a0 .equ _io_lcd *LCD port a043 _lcd_a1 .equ _io_lcd+2 *LCD port a144 * 24 25 | ------------------------------------------------------------------------------ 26 27 | Hardware base addresses 28 | ----------------------- 29 _io_fpu = 0x180000 | FPU base address 30 31 VB = 0x200000 | VSDD base address 32 33 _io_time = 0x3A0001 | Timer chip 34 _io_lcd = 0x3A4001 | LCD controller 35 _io_ser = 0x3A8001 | Serial ports (RS232) 36 _io_midi = 0x3AC001 | MIDI ports 37 _io_disk = 0x3B0001 | Disk controller 38 _io_tone = 0x3B4001 | Sound generator chip 39 _io_leds = 0x3B8001 | LED driver 40 _io_kbrd = 0x3BC001 | Keyboard / panel processor 41 42 _lcd_a0 = _io_lcd | LCD port a0 43 _lcd_a1 = _io_lcd+2 | LCD port a1 44 45 45 .page 46 * 47 *Video definitions48 *-----------------49 _io_vreg .equ VB *Relocated video registers after setup50 _io_vraw .equ VB+$400 *Raw video registers at RESET51 _io_vram .equ VB *Video RAM base address52 * 53 *Name Offset Usage Bank54 *------- --------- ------------------------- ----55 _v_regs .equ VB *Video registers 0,156 * 57 _v_odtab .equ VB+128 *Object Descriptor Table 058 _v_actab .equ VB+256 *Access Table 059 _v_ct0 .equ VB+1024 *Character Text-0 060 _v_gt1 .equ VB+1304 *Graphics Text-1 061 _v_score .equ VB+8192 *Score object 062 _v_cgtab .equ VB+122880 *Character Generator Table 063 * 64 _v_curs0 .equ VB+1024 *Cursor object 0 (arrow ULE) 165 _v_curs1 .equ VB+1152 *Cursor object 1 (arrow ULO) 166 _v_curs2 .equ VB+1280 *Cursor object 2 (arrow URE) 167 _v_curs3 .equ VB+1408 *Cursor object 3 (arrow URO) 168 _v_curs4 .equ VB+1536 *Cursor object 4 (arrow LLE) 169 _v_curs5 .equ VB+1664 *Cursor object 5 (arrow LLO) 170 _v_curs6 .equ VB+1792 *Cursor object 6 (arrow LRE) 171 _v_curs7 .equ VB+1920 *Cursor object 7 (arrow LRO) 172 _v_tcur .equ VB+2048 *Typewriter cursor 173 _v_kbobj .equ VB+2880 *Keyboard object 174 _v_lnobj .equ VB+4672 *Line object 175 _v_cur .equ VB+6464 *Underline cursor 176 _v_win0 .equ VB+16384 *Window-0 object 177 * 78 *BIOS RAM definitions79 *--------------------80 *WARNING: the following addresses must match those of the corresponding81 *variables defined in bios.s or chaos is guaranteed.82 * 83 _fc_sw .equ $420 *word - Frame counter switch84 _fc_val .equ $422 *long - Frame counter value85 * 46 47 | Video definitions 48 | ----------------- 49 _io_vreg = VB | Relocated video registers after setup 50 _io_vraw = VB+0x400 | Raw video registers at RESET 51 _io_vram = VB | Video RAM base address 52 53 | Name Offset Usage Bank 54 | ------- --------- ------------------------- ---- 55 _v_regs = VB | Video registers 0,1 56 57 _v_odtab = VB+128 | Object Descriptor Table 0 58 _v_actab = VB+256 | Access Table 0 59 _v_ct0 = VB+1024 | Character Text-0 0 60 _v_gt1 = VB+1304 | Graphics Text-1 0 61 _v_score = VB+8192 | Score object 0 62 _v_cgtab = VB+122880 | Character Generator Table 0 63 64 _v_curs0 = VB+1024 | Cursor object 0 (arrow ULE) 1 65 _v_curs1 = VB+1152 | Cursor object 1 (arrow ULO) 1 66 _v_curs2 = VB+1280 | Cursor object 2 (arrow URE) 1 67 _v_curs3 = VB+1408 | Cursor object 3 (arrow URO) 1 68 _v_curs4 = VB+1536 | Cursor object 4 (arrow LLE) 1 69 _v_curs5 = VB+1664 | Cursor object 5 (arrow LLO) 1 70 _v_curs6 = VB+1792 | Cursor object 6 (arrow LRE) 1 71 _v_curs7 = VB+1920 | Cursor object 7 (arrow LRO) 1 72 _v_tcur = VB+2048 | Typewriter cursor 1 73 _v_kbobj = VB+2880 | Keyboard object 1 74 _v_lnobj = VB+4672 | Line object 1 75 _v_cur = VB+6464 | Underline cursor 1 76 _v_win0 = VB+16384 | Window-0 object 1 77 78 | BIOS RAM definitions 79 | -------------------- 80 | WARNING: the following addresses must match those of the corresponding 81 | variables defined in bios.s or chaos is guaranteed. 82 83 _fc_sw = 0x420 | word - Frame counter switch 84 _fc_val = 0x422 | long - Frame counter value 85 86 86 .end -
iolib/rtraps.s
rf40a309 r4f508e6 1 *------------------------------------------------------------------------------2 *rtraps.s -- define ROMP debug trap3 *Version 7 -- 1988-01-12 -- Copyright 1987, 1988 by D.N. Lynx Crowe4 *------------------------------------------------------------------------------1 | ------------------------------------------------------------------------------ 2 | rtraps.s -- define ROMP debug trap 3 | Version 7 -- 1988-01-12 -- Copyright 1987, 1988 by D.N. Lynx Crowe 4 | ------------------------------------------------------------------------------ 5 5 .text 6 * 6 7 7 .xdef _trap15 8 * 8 9 9 .xref _rompbp 10 * 10 11 11 .xref tr1sav,tr13sav,tr14sav 12 12 .xref tr1rmp,tr13rmp,tr14rmp 13 * 14 BUCHLA .equ 1 *IPL value: 0 = NASA , 1 = Buchla15 * 13 14 BUCHLA = 1 | IPL value: 0 = NASA , 1 = Buchla 15 16 16 .ifeq BUCHLA 17 IPLEVEL .equ $0400 *NASA IPL = 4 (enable 5 and above)17 IPLEVEL = 0x0400 | NASA IPL = 4 (enable 5 and above) 18 18 .endc 19 * 19 20 20 .ifne BUCHLA 21 IPLEVEL .equ $0200 *Buchla IPL = 2 (enable 3 and above)21 IPLEVEL = 0x0200 | Buchla IPL = 2 (enable 3 and above) 22 22 .endc 23 * 24 IPL7 .equ $0700 *IPL 725 * 26 *_trap15 -- ROMP debug trap (used to implement breakpoints)27 *------- ------------------------------------------------28 _trap15: ori.w #IPL7,sr *Disable interrupts29 move.w #0,-(a7) *Keep stack long aligned30 movem.l d0-d7/a0-a7,-(a7) *Save regs on stack31 move.l tr1sav,tr1rmp *Save trap save areas32 move.l tr13sav,tr13rmp *...33 move.l tr14sav,tr14rmp *...34 move.w sr,d0 *Get status register35 andi.w # $F8FF,d0 *Enable serial I/O interrupts36 ori.w #IPLEVEL,d0 *...37 move.w d0,sr *...38 jsr _rompbp *Pass control to ROMP39 * 40 ori.w #IPL7,sr *Disable interrupts41 move.l tr14rmp,tr14sav *Restore trap save areas42 move.l tr13rmp,tr13sav *...43 move.l tr1rmp,tr1sav *...44 movem.l (a7)+,d0-d7/a0-a7 *Restore regs45 addq.l #2,a7 *Discard alignment filler word46 rte *Back to what we interrupted47 * 23 24 IPL7 = 0x0700 | IPL 7 25 26 | _trap15 -- ROMP debug trap (used to implement breakpoints) 27 | ------- ------------------------------------------------ 28 _trap15: ori.w #IPL7,sr | Disable interrupts 29 move.w #0,-(a7) | Keep stack long aligned 30 movem.l d0-d7/a0-a7,-(a7) | Save regs on stack 31 move.l tr1sav,tr1rmp | Save trap save areas 32 move.l tr13sav,tr13rmp | ... 33 move.l tr14sav,tr14rmp | ... 34 move.w sr,d0 | Get status register 35 andi.w #0xF8FF,d0 | Enable serial I/O interrupts 36 ori.w #IPLEVEL,d0 | ... 37 move.w d0,sr | ... 38 jsr _rompbp | Pass control to ROMP 39 40 ori.w #IPL7,sr | Disable interrupts 41 move.l tr14rmp,tr14sav | Restore trap save areas 42 move.l tr13rmp,tr13sav | ... 43 move.l tr1rmp,tr1sav | ... 44 movem.l (a7)+,d0-d7/a0-a7 | Restore regs 45 addq.l #2,a7 | Discard alignment filler word 46 rte | Back to what we interrupted 47 48 48 .end -
iolib/setipl.s
rf40a309 r4f508e6 1 * 2 *setipl.s -- Set internal processor interrupt level3 *-------- --------------------------------------4 *Version 2 -- 1988-06-29 -- D.N. Lynx Crowe5 * 6 *short7 *setipl(arg);8 *short arg;9 * 10 *Sets processor interrupt level to arg.11 *Returns old interrupt level, or -1 if arg < 0 or > 712 * 13 *Assumes you are in supervisor mode.14 *You get a Privelege Violation TRAP if you aren't.15 * 1 2 | setipl.s -- Set internal processor interrupt level 3 | -------- -------------------------------------- 4 | Version 2 -- 1988-06-29 -- D.N. Lynx Crowe 5 6 | short 7 | setipl(arg); 8 | short arg; 9 10 | Sets processor interrupt level to arg. 11 | Returns old interrupt level, or -1 if arg < 0 or > 7 12 13 | Assumes you are in supervisor mode. 14 | You get a Privelege Violation TRAP if you aren't. 15 16 16 .text 17 * 17 18 18 .xdef _setipl 19 * 20 _setipl: link a6,#0 *Link up stack frames21 move.w 8(a6),d0 *Get argument22 tst.w d0 *Check lower limit23 bmi setipler *Jump if < 0 (error)24 * 25 cmpi.w #7,d0 *Check upper limit26 bgt setipler *Jump if > 7 (error)27 * 28 move.w sr,d1 *Get current level29 move.w d1,d2 *... save for later30 lsl.w #8,d0 *Shift argument into position31 andi.w # $F8FF,d1 *Mask out old level32 or.w d0,d1 *OR in new level33 move.w d2,d0 *Setup return of old level34 lsr.w #8,d0 *...35 andi.l # $7,d0 *...36 move.w d1,sr *Set the new interrupt level37 unlk a6 *Unlink stack frames38 rts *Return to caller39 * 40 setipler: moveq.l #-1,d0 *Setup to return error code41 unlk a6 *Unlink stack frames42 rts *Return to caller43 * 19 20 _setipl: link a6,#0 | Link up stack frames 21 move.w 8(a6),d0 | Get argument 22 tst.w d0 | Check lower limit 23 bmi setipler | Jump if < 0 (error) 24 25 cmpi.w #7,d0 | Check upper limit 26 bgt setipler | Jump if > 7 (error) 27 28 move.w sr,d1 | Get current level 29 move.w d1,d2 | ... save for later 30 lsl.w #8,d0 | Shift argument into position 31 andi.w #0xF8FF,d1 | Mask out old level 32 or.w d0,d1 | OR in new level 33 move.w d2,d0 | Setup return of old level 34 lsr.w #8,d0 | ... 35 andi.l #0x7,d0 | ... 36 move.w d1,sr | Set the new interrupt level 37 unlk a6 | Unlink stack frames 38 rts | Return to caller 39 40 setipler: moveq.l #-1,d0 | Setup to return error code 41 unlk a6 | Unlink stack frames 42 rts | Return to caller 43 44 44 .end -
iolib/setsr.s
rf40a309 r4f508e6 1 * 2 *setsr.s -- Set processor status register3 *------- -----------------------------4 *Version 1 -- 1988-06-29 -- D.N. Lynx Crowe5 * 6 *short7 *setsr(arg);8 *short arg;9 * 10 *Sets processor status register to 'arg'.11 *Returns old status register value.12 * 13 *Assumes you are in supervisor mode.14 *You get a Privelege Violation TRAP if you aren't.15 * 16 *Coded for speed -- this is as fast as you can get.17 *No error checking is done -- assumes you know what you're doing.18 * 1 2 | setsr.s -- Set processor status register 3 | ------- ----------------------------- 4 | Version 1 -- 1988-06-29 -- D.N. Lynx Crowe 5 6 | short 7 | setsr(arg); 8 | short arg; 9 10 | Sets processor status register to 'arg'. 11 | Returns old status register value. 12 13 | Assumes you are in supervisor mode. 14 | You get a Privelege Violation TRAP if you aren't. 15 16 | Coded for speed -- this is as fast as you can get. 17 | No error checking is done -- assumes you know what you're doing. 18 19 19 .text 20 * 20 21 21 .xdef _setsr 22 * 23 _setsr: move.w sr,d0 *Get current sr24 move.w 4(sp),sr *Set new sr25 rts *Return to caller26 * 22 23 _setsr: move.w sr,d0 | Get current sr 24 move.w 4(sp),sr | Set new sr 25 rts | Return to caller 26 27 27 .end -
iolib/traps.s
rf40a309 r4f508e6 1 * 2 *traps.s -- define trap linkages for C routines3 *------- -----------------------------------4 *Version 8 -- 1987-06-08 -- D.N. Lynx Crowe5 * 6 *Caution: these are serially re-useable, but NOT reentrant, so7 *don't use them in interrupt processing code.8 * 9 *An exception is made for ROMP in _trap15 for breakpoints so that the10 *debug code can be debugged.11 * 1 2 | traps.s -- define trap linkages for C routines 3 | ------- ----------------------------------- 4 | Version 8 -- 1987-06-08 -- D.N. Lynx Crowe 5 6 | Caution: these are serially re-useable, but NOT reentrant, so 7 | don't use them in interrupt processing code. 8 9 | An exception is made for ROMP in _trap15 for breakpoints so that the 10 | debug code can be debugged. 11 12 12 .text 13 * 13 14 14 .xdef _trap1 15 15 .xdef _trap13,_trap14 16 16 .xdef _xtrap15 17 * 17 18 18 .xdef tr1sav,tr13sav,tr14sav 19 19 .xdef tr1rmp,tr13rmp,tr14rmp 20 * 21 *_trap1 -- provide access to BDOS functions22 *------ --------------------------------23 _trap1: move.l (a7)+,tr1sav *Save return address24 trap #1 *Do the trap25 move.l tr1sav,-(a7) *Restore return address26 rts *Return to caller27 * 28 *_trap13 -- provide access to BIOS functions29 *------- --------------------------------30 _trap13: move.l (a7)+,tr13sav *Save return address31 trap #13 *Do the trap32 move.l tr13sav,-(a7) *Restore return address33 rts *Return to caller34 * 35 *_trap14 -- provide access to extended BIOS functions36 *------- -----------------------------------------37 _trap14: move.l (a7)+,tr14sav *Save return address38 trap #14 *Do the trap39 move.l tr14sav,-(a7) *Restore return address40 rts *Return to caller41 * 42 *_xtrap15 -- Setup initial register trap for ROMP43 *-------- ------------------------------------44 _xtrap15: trap #15 *TRAP into ROMP45 rts *Return (usually won't happen)46 * 20 21 | _trap1 -- provide access to BDOS functions 22 | ------ -------------------------------- 23 _trap1: move.l (a7)+,tr1sav | Save return address 24 trap #1 | Do the trap 25 move.l tr1sav,-(a7) | Restore return address 26 rts | Return to caller 27 28 | _trap13 -- provide access to BIOS functions 29 | ------- -------------------------------- 30 _trap13: move.l (a7)+,tr13sav | Save return address 31 trap #13 | Do the trap 32 move.l tr13sav,-(a7) | Restore return address 33 rts | Return to caller 34 35 | _trap14 -- provide access to extended BIOS functions 36 | ------- ----------------------------------------- 37 _trap14: move.l (a7)+,tr14sav | Save return address 38 trap #14 | Do the trap 39 move.l tr14sav,-(a7) | Restore return address 40 rts | Return to caller 41 42 | _xtrap15 -- Setup initial register trap for ROMP 43 | -------- ------------------------------------ 44 _xtrap15: trap #15 | TRAP into ROMP 45 rts | Return (usually won't happen) 46 47 47 .page 48 * 49 *RAM storage areas50 *-----------------48 49 | RAM storage areas 50 | ----------------- 51 51 .bss 52 52 .even 53 * 54 tr1sav: ds.l 1 *Return address for trap155 tr13sav: ds.l 1 *Return address for trap1356 tr14sav: ds.l 1 *Return address for trap1457 * 58 tr1rmp: ds.l 1 *Save area for tr1sav for ROMP59 tr13rmp: ds.l 1 *Save area for tr13sav for ROMP60 tr14rmp: ds.l 1 *Save area for tr14sav for ROMP61 * 53 54 tr1sav: ds.l 1 | Return address for trap1 55 tr13sav: ds.l 1 | Return address for trap13 56 tr14sav: ds.l 1 | Return address for trap14 57 58 tr1rmp: ds.l 1 | Save area for tr1sav for ROMP 59 tr13rmp: ds.l 1 | Save area for tr13sav for ROMP 60 tr14rmp: ds.l 1 | Save area for tr14sav for ROMP 61 62 62 .end -
lib700/aldiv.s
rf40a309 r4f508e6 1 * 2 *aldiv.s -- indirect long divide3 *Version 1 -- 1989-01-24 -- D.N. Lynx Crowe4 * 1 2 | aldiv.s -- indirect long divide 3 | Version 1 -- 1989-01-24 -- D.N. Lynx Crowe 4 5 5 .text 6 * 6 7 7 .xdef aldiv 8 8 .xdef _aldiv 9 * 9 10 10 .xref _ldiv 11 * 11 12 12 aldiv: 13 13 _aldiv: 14 * 14 15 15 link a6,#-2 16 16 move.l 12(a6),-(a7) … … 23 23 unlk a6 24 24 rts 25 * 25 26 26 .end -
lib700/almul.s
rf40a309 r4f508e6 1 * 2 *almul.s -- indirect long multiply3 *Version 1 -- 1989-01-24 -- D.N. Lynx Crowe4 * 1 2 | almul.s -- indirect long multiply 3 | Version 1 -- 1989-01-24 -- D.N. Lynx Crowe 4 5 5 .text 6 * 6 7 7 .xdef almul 8 * 8 9 9 .xref lmul 10 * 10 11 11 almul: move.l a5,-(a7) 12 12 movea.l 8(a7),a5 … … 18 18 movea.l (a7)+,a5 19 19 rts 20 * 20 21 21 .end -
lib700/alrem.s
rf40a309 r4f508e6 1 * 2 *alrem.s -- indirect long modulus3 *Version 1 -- 1989-01-24 -- D.N. Lynx Crowe4 * 1 2 | alrem.s -- indirect long modulus 3 | Version 1 -- 1989-01-24 -- D.N. Lynx Crowe 4 5 5 .text 6 * 6 7 7 .xdef alrem 8 8 .xdef _alrem 9 * 9 10 10 .xref _ldiv 11 11 .xref _ldivr 12 * 12 13 13 alrem: 14 14 _alrem: 15 * 15 16 16 link a6,#-2 17 17 move.l 12(a6),-(a7) … … 25 25 unlk a6 26 26 rts 27 * 27 28 28 .end -
lib700/blkfill.s
rf40a309 r4f508e6 1 *------------------------------------------------------------------------------2 *blkfill.s -- block fill function3 *Version 1 -- 1987-08-28 -- D.N. Lynx Crowe4 * 5 *void6 *blkfill(where, what, count)7 * char *where;8 *char what;9 *short count;10 * 11 *Fills 'count' bytes at 'where' with 'what'.12 *------------------------------------------------------------------------------1 | ------------------------------------------------------------------------------ 2 | blkfill.s -- block fill function 3 | Version 1 -- 1987-08-28 -- D.N. Lynx Crowe 4 5 | void 6 | blkfill(where, what, count) 7 | char |where; 8 | char what; 9 | short count; 10 11 | Fills 'count' bytes at 'where' with 'what'. 12 | ------------------------------------------------------------------------------ 13 13 .text 14 * 14 15 15 .xdef _blkfill 16 * 16 17 17 _blkfill: link a6,#0 18 18 movem.l d5-d7/a5-a5,-(a7) … … 21 21 move.w 14(a6),d6 22 22 bra blkf2 23 * 23 24 24 blkf1: move.b d7,(a5)+ 25 * 25 26 26 blkf2: move.w d6,d0 27 27 subq.w #1,d6 28 28 tst.w d0 29 29 bgt blkf1 30 * 30 31 31 tst (a7)+ 32 32 movem.l (a7)+,d6-d7/a5-a5 33 33 unlk a6 34 34 rts 35 * 35 36 36 .end -
lib700/blkmove.s
rf40a309 r4f508e6 1 *------------------------------------------------------------------------------2 *blkmove.s -- block move function3 *Version 1 -- 1987-08-28 -- D.N. Lynx Crowe4 * 5 *void6 *blkmove(to, from, n)7 * char *to, *from;8 *short n;9 * 10 *Copies 'n' bytes from address 'from' to address 'to'.11 *Treats overlaps of from and to areas intelligently.12 *------------------------------------------------------------------------------1 | ------------------------------------------------------------------------------ 2 | blkmove.s -- block move function 3 | Version 1 -- 1987-08-28 -- D.N. Lynx Crowe 4 5 | void 6 | blkmove(to, from, n) 7 | char |to, |from; 8 | short n; 9 10 | Copies 'n' bytes from address 'from' to address 'to'. 11 | Treats overlaps of from and to areas intelligently. 12 | ------------------------------------------------------------------------------ 13 13 .text 14 * 14 15 15 .xdef _blkmove 16 * 17 _blkmove: link a6,# $FFFC16 17 _blkmove: link a6,#-4 18 18 move.l 8(a6),d0 19 19 cmp.l 12(a6),d0 20 20 bcc blkm3 21 * 21 22 22 bra blkm2 23 * 23 24 24 blkm1: movea.l 8(a6),a0 25 25 movea.l 12(a6),a1 … … 27 27 addq.l #1,8(a6) 28 28 addq.l #1,12(a6) 29 * 29 30 30 blkm2: move.w 16(a6),d0 31 31 subq.w #1,16(a6) 32 32 tst.w d0 33 33 bne blkm1 34 * 34 35 35 bra blkm6 36 * 36 37 37 blkm3: move.w 16(a6),d0 38 38 ext.l d0 … … 40 40 add.l d0,12(a6) 41 41 bra blkm5 42 * 42 43 43 blkm4: subq.l #1,8(a6) 44 44 subq.l #1,12(a6) … … 46 46 movea.l 12(a6),a1 47 47 move.b (a1),(a0) 48 * 48 49 49 blkm5: move.w 16(a6),d0 50 50 subq.w #1,16(a6) 51 51 tst.w d0 52 52 bne blkm4 53 * 53 54 54 blkm6: unlk a6 55 55 rts 56 * 56 57 57 .end -
lib700/finalone.s
rf40a309 r4f508e6 1 *------------------------------------------------------------------------------2 *finalone.s -- the last stuff to get loaded3 *Version 4 -- 1987-06-30 -- D.N. Lynx Crowe4 * 5 *This is so we can figure out where things got loaded.6 *------------------------------------------------------------------------------7 * 1 | ------------------------------------------------------------------------------ 2 | finalone.s -- the last stuff to get loaded 3 | Version 4 -- 1987-06-30 -- D.N. Lynx Crowe 4 5 | This is so we can figure out where things got loaded. 6 | ------------------------------------------------------------------------------ 7 8 8 .text 9 * 9 10 10 .xdef FinalOne 11 11 .xdef The_Fini 12 12 .xdef Text_End 13 * 14 * 15 *This is the last piece of code in the 'text' segment.16 * 17 FinalOne: rts *we just need the address here18 * 19 Text_End: rts *we just need the address here20 * 21 *------------------------------------------------------------------------------22 * 13 14 15 | This is the last piece of code in the 'text' segment. 16 17 FinalOne: rts | we just need the address here 18 19 Text_End: rts | we just need the address here 20 21 | ------------------------------------------------------------------------------ 22 23 23 .data 24 24 .even 25 * 26 The_Fini: dc.w $FFFF *last thing in the 'data' segment27 * 28 *------------------------------------------------------------------------------29 * 25 26 The_Fini: dc.w 0xFFFF | last thing in the 'data' segment 27 28 | ------------------------------------------------------------------------------ 29 30 30 .end -
lib700/jumpto.s
rf40a309 r4f508e6 1 *------------------------------------------------------------------------------2 *jumpto.s -- miscellaneous ROMP support functions3 *Version 4 -- 1987-10-14 -- D.N. Lynx Crowe4 * 5 *WARNING:6 *--------7 *These functions, in general, assume supervisor mode and8 *'sane' arguments, so no error checking is done.9 * 10 *halt()11 * 12 *Brings the processor to a grinding halt. Requires external13 *reset to restart things. Use only for catastrophic hard halts.14 * 15 *jumpto(addr)16 *long addr;17 * 18 *Jumps to 'addr'. No error check is done on 'addr'.19 * 20 *rjumpto(addr)21 *long addr;22 * 23 *Performs the 68000 'RESET' command, then jumps to 'addr'.24 *No error check is made on 'addr'.25 * 26 *sjumpto(addr, stack)27 *long addr, stack;28 * 29 *Sets a7 to 'stack', then jumps to 'addr'.30 *No error check is done on 'addr'.31 * 32 *xreset()33 * 34 *Performs the 68000 'RESET' command. This is very dangerous,35 *and should be used with extreme care regarding such36 *things as interrupts, device initialization, vectors,37 *and sundry other reset-related things.38 * 39 *------------------------------------------------------------------------------1 | ------------------------------------------------------------------------------ 2 | jumpto.s -- miscellaneous ROMP support functions 3 | Version 4 -- 1987-10-14 -- D.N. Lynx Crowe 4 5 | WARNING: 6 | -------- 7 | These functions, in general, assume supervisor mode and 8 | 'sane' arguments, so no error checking is done. 9 10 | halt() 11 12 | Brings the processor to a grinding halt. Requires external 13 | reset to restart things. Use only for catastrophic hard halts. 14 15 | jumpto(addr) 16 | long addr; 17 18 | Jumps to 'addr'. No error check is done on 'addr'. 19 20 | rjumpto(addr) 21 | long addr; 22 23 | Performs the 68000 'RESET' command, then jumps to 'addr'. 24 | No error check is made on 'addr'. 25 26 | sjumpto(addr, stack) 27 | long addr, stack; 28 29 | Sets a7 to 'stack', then jumps to 'addr'. 30 | No error check is done on 'addr'. 31 32 | xreset() 33 34 | Performs the 68000 'RESET' command. This is very dangerous, 35 | and should be used with extreme care regarding such 36 | things as interrupts, device initialization, vectors, 37 | and sundry other reset-related things. 38 39 | ------------------------------------------------------------------------------ 40 40 .text 41 * 41 42 42 .xdef _halt,_jumpto,_rjumpto,_sjumpto,_xreset 43 * 43 44 44 .page 45 * 46 _halt: stop # $2700 *stop dead, interrupts disabled47 jmp _halt *stay stopped if stepped thru48 * 49 _jumpto: movea.l 4(a7),a0 *get jump address50 jmp (a0) *go to the jump address51 * 52 _rjumpto: reset *reset external devices53 movea.l 4(a7),a0 *get jump address54 jmp (a0) *go to the jump address55 * 56 _sjumpto: movea.l 4(a7),a0 *get jump address57 movea.l 8(a7),a7 *set stack pointer58 jmp (a0) *go to the jump address59 * 60 _xreset: reset *reset external devices61 rts *return to caller62 * 45 46 _halt: stop #0x2700 | stop dead, interrupts disabled 47 jmp _halt | stay stopped if stepped thru 48 49 _jumpto: movea.l 4(a7),a0 | get jump address 50 jmp (a0) | go to the jump address 51 52 _rjumpto: reset | reset external devices 53 movea.l 4(a7),a0 | get jump address 54 jmp (a0) | go to the jump address 55 56 _sjumpto: movea.l 4(a7),a0 | get jump address 57 movea.l 8(a7),a7 | set stack pointer 58 jmp (a0) | go to the jump address 59 60 _xreset: reset | reset external devices 61 rts | return to caller 62 63 63 .end -
lib700/ldiv.s
rf40a309 r4f508e6 1 *------------------------------------------------------------------------------2 *ldiv.s -- long division3 *Version 1 -- 1988-01-224 *------------------------------------------------------------------------------1 | ------------------------------------------------------------------------------ 2 | ldiv.s -- long division 3 | Version 1 -- 1988-01-22 4 | ------------------------------------------------------------------------------ 5 5 .text 6 * 6 7 7 .xdef _ldiv 8 8 .xdef ldiv 9 * 9 10 10 .xdef _ldivr 11 * 12 ARG1 .equ813 ARG2 .equ1214 * 11 12 ARG1 = 8 13 ARG2 = 12 14 15 15 _ldiv: 16 16 ldiv: link a6,#-2 … … 21 21 move.l ARG2(a6),d6 22 22 bne ldiv1 23 * 24 move.l # $80000000,_ldivr25 move.l # $80000000,d023 24 move.l #0x80000000,_ldivr 25 move.l #0x80000000,d0 26 26 divs #0,d0 27 27 bra ldiv11 28 * 28 29 29 ldiv1: bge ldiv2 30 * 30 31 31 neg.l d6 32 32 addq.w #1,d3 33 * 33 34 34 ldiv2: tst.l d7 35 35 bge ldiv3 36 * 36 37 37 neg.l d7 38 38 addq.w #1,d3 39 * 39 40 40 ldiv3: cmp.l d7,d6 41 41 bgt ldiv9 42 * 42 43 43 bne ldiv4 44 * 44 45 45 moveq.l #1,d5 46 46 clr.l d7 47 47 bra ldiv9 48 * 49 ldiv4: cmp.l # $10000,d748 49 ldiv4: cmp.l #0x10000,d7 50 50 bge ldiv5 51 * 51 52 52 divu d6,d7 53 53 move.w d7,d5 … … 55 55 ext.l d7 56 56 bra ldiv9 57 * 57 58 58 ldiv5: moveq.l #1,d4 59 * 59 60 60 ldiv6: cmp.l d6,d7 61 61 bcs ldiv7 62 * 62 63 63 asl.l #1,d6 64 64 asl.l #1,d7 65 65 bra ldiv6 66 * 66 67 67 ldiv7: tst.l d4 68 68 beq ldiv9 69 * 69 70 70 cmp.l d6,d7 71 71 bcs ldiv8 72 * 72 73 73 or.l d4,d5 74 74 sub.l d6,d7 75 * 75 76 76 ldiv8: lsr.l #1,d4 77 77 lsr.l #1,d6 78 78 bra ldiv7 79 * 79 80 80 ldiv9: cmp.w #1,d3 81 81 bne ldiv10 82 * 82 83 83 neg.l d7 84 84 move.l d7,_ldivr … … 86 86 neg.l d0 87 87 bra ldiv11 88 * 88 89 89 ldiv10: move.l d7,_ldivr 90 90 move.l d5,d0 91 * 91 92 92 ldiv11: tst.l (a7)+ 93 93 movem.l (a7)+,d3-d7 94 94 unlk a6 95 95 rts 96 * 96 97 97 .bss 98 * 98 99 99 _ldivr: .ds.l 1 100 * 100 101 101 .end -
lib700/lmul.s
rf40a309 r4f508e6 1 *------------------------------------------------------------------------------2 *lmul.s -- long multiply3 *Version 2 -- 1989-07-184 *------------------------------------------------------------------------------1 | ------------------------------------------------------------------------------ 2 | lmul.s -- long multiply 3 | Version 2 -- 1989-07-18 4 | ------------------------------------------------------------------------------ 5 5 .text 6 * 6 7 7 .xdef lmul 8 * 9 ARG1 .equ810 ARG2 .equ1211 * 12 TEMP .equ-413 * 8 9 ARG1 = 8 10 ARG2 = 12 11 12 TEMP = -4 13 14 14 lmul: link a6,#-4 15 15 clr.w d2 16 16 tst.l ARG1(a6) 17 17 bge lmul1 18 * 18 19 19 neg.l ARG1(a6) 20 20 addq.w #1,d2 21 * 21 22 22 lmul1: tst.l ARG2(a6) 23 23 bge lmul2 24 * 24 25 25 neg.l ARG2(a6) 26 26 addq.w #1,d2 27 * 27 28 28 lmul2: move.w ARG1+2(a6),d0 29 29 mulu ARG2+2(a6),d0 … … 39 39 btst #0,d2 40 40 beq lmul3 41 * 41 42 42 neg.l d0 43 * 43 44 44 lmul3: unlk a6 45 45 rts 46 * 46 47 47 .end -
lib700/lrem.s
rf40a309 r4f508e6 1 *------------------------------------------------------------------------------2 *lrem.s -- long modulo3 *Version 1 -- 1988-01-224 *------------------------------------------------------------------------------1 | ------------------------------------------------------------------------------ 2 | lrem.s -- long modulo 3 | Version 1 -- 1988-01-22 4 | ------------------------------------------------------------------------------ 5 5 .text 6 * 6 7 7 .xdef _lrem 8 8 .xdef lrem 9 * 9 10 10 .xref ldiv 11 11 .xref _ldivr 12 * 13 ARG1 .equ814 ARG2 .equ1215 * 12 13 ARG1 = 8 14 ARG2 = 12 15 16 16 _lrem: 17 17 lrem: link a6,#-2 … … 23 23 unlk a6 24 24 rts 25 * 25 26 26 .end -
lib700/rand24.s
rf40a309 r4f508e6 1 *------------------------------------------------------------------------------2 *rand24.s -- generate a 24 bit random number3 *Version 3 -- 1988-04-29 -- D.N. Lynx Crowe4 *------------------------------------------------------------------------------5 *Synopsis:6 *long7 *rand24()8 * 9 *Based on:10 *Knuth, Donald E.11 *The Art of Computer Programming,12 *Volume 2: Semi-Numerical Algorithms13 * 14 *Computes:15 * S = [S *C] + K16 * 17 *Where:18 *K = 119 *C = 314159262120 *S = the seed (if zero, it gets set from the 200 Hz clock)21 * 22 *Returns:23 *S >> 8 (a 24 bit pseudo-random number)24 * 25 *Note: this function has an LSB with an exactly 50% distribution, so using26 *individual bits is probably not a good idea. Using more bits makes things27 *appear more random.28 *------------------------------------------------------------------------------1 | ------------------------------------------------------------------------------ 2 | rand24.s -- generate a 24 bit random number 3 | Version 3 -- 1988-04-29 -- D.N. Lynx Crowe 4 | ------------------------------------------------------------------------------ 5 | Synopsis: 6 | long 7 | rand24() 8 9 | Based on: 10 | Knuth, Donald E. 11 | The Art of Computer Programming, 12 | Volume 2: Semi-Numerical Algorithms 13 14 | Computes: 15 | S = [S | C] + K 16 17 | Where: 18 | K = 1 19 | C = 3141592621 20 | S = the seed (if zero, it gets set from the 200 Hz clock) 21 22 | Returns: 23 | S >> 8 (a 24 bit pseudo-random number) 24 25 | Note: this function has an LSB with an exactly 50% distribution, so using 26 | individual bits is probably not a good idea. Using more bits makes things 27 | appear more random. 28 | ------------------------------------------------------------------------------ 29 29 .text 30 * 30 31 31 .xdef _rand24 32 * 32 33 33 .xdef _rseed 34 * 35 *equates for things in the BIOS36 * 37 RCLOCK .equ $49E *LONG - 200 Hz clock38 * 39 *equates for stack offsets40 * 41 ARG1 .equ 8 *LONG / WORD - arg1 / MS bits42 ARG1L .equ 10 *WORD - arg1 LS bits43 ARG2 .equ 12 *LONG / WORD - arg2 / MS bits44 ARG2L .equ 14 *WORD - arg2 LS bits45 * 46 PART .equ -4 *LONG - partial product47 * 48 PI .equ $BB40E62D *LONG - PI as a hex value49 * 34 35 | equates for things in the BIOS 36 37 RCLOCK = 0x49E | LONG - 200 Hz clock 38 39 | equates for stack offsets 40 41 ARG1 = 8 | LONG / WORD - arg1 / MS bits 42 ARG1L = 10 | WORD - arg1 LS bits 43 ARG2 = 12 | LONG / WORD - arg2 / MS bits 44 ARG2L = 14 | WORD - arg2 LS bits 45 46 PART = -4 | LONG - partial product 47 48 PI = 0xBB40E62D | LONG - PI as a hex value 49 50 50 .page 51 * 52 *mult32 -- 32 bit signed multiply53 *------ ----------------------54 mult32: link a6,#-4 *link stack frames55 clr.w d2 *clear sign flags56 tst.l ARG1(a6) *check sign of 1st argument57 bge mult32a *...58 * 59 neg.l ARG1(a6) *make 1st argument positive60 addq.w #1,d2 *log its sign as negative61 * 62 mult32a: tst.l ARG2(a6) *check sign of 2nd argument63 bge mult32b *...64 * 65 neg.l ARG2(a6) *make 2nd argument positive66 addq.w #1,d2 *log its sign as negative67 * 68 mult32b: move.w ARG1L(a6),d0 *generate 1st partial product69 mulu ARG2L(a6),d0 *...70 move.l d0,PART(a6) *...71 move.w ARG1(a6),d0 *generate 2nd partial product72 mulu ARG2L(a6),d0 *...73 move.w ARG2(a6),d1 *generate 3rd partial product74 mulu ARG1L(a6),d1 *...75 add.w d1,d0 *add partial products76 add.w PART(a6),d0 *...77 move.w d0,PART(a6) *...78 move.l PART(a6),d0 *...79 btst #0,d2 *adjust sign of result80 beq mult32c *...81 * 82 neg.l d0 *...83 * 84 mult32c: unlk a6 *unlink stack frames85 rts *return86 * 51 52 | mult32 -- 32 bit signed multiply 53 | ------ ---------------------- 54 mult32: link a6,#-4 | link stack frames 55 clr.w d2 | clear sign flags 56 tst.l ARG1(a6) | check sign of 1st argument 57 bge mult32a | ... 58 59 neg.l ARG1(a6) | make 1st argument positive 60 addq.w #1,d2 | log its sign as negative 61 62 mult32a: tst.l ARG2(a6) | check sign of 2nd argument 63 bge mult32b | ... 64 65 neg.l ARG2(a6) | make 2nd argument positive 66 addq.w #1,d2 | log its sign as negative 67 68 mult32b: move.w ARG1L(a6),d0 | generate 1st partial product 69 mulu ARG2L(a6),d0 | ... 70 move.l d0,PART(a6) | ... 71 move.w ARG1(a6),d0 | generate 2nd partial product 72 mulu ARG2L(a6),d0 | ... 73 move.w ARG2(a6),d1 | generate 3rd partial product 74 mulu ARG1L(a6),d1 | ... 75 add.w d1,d0 | add partial products 76 add.w PART(a6),d0 | ... 77 move.w d0,PART(a6) | ... 78 move.l PART(a6),d0 | ... 79 btst #0,d2 | adjust sign of result 80 beq mult32c | ... 81 82 neg.l d0 | ... 83 84 mult32c: unlk a6 | unlink stack frames 85 rts | return 86 87 87 .page 88 * 89 *_rand24 -- Generate a random number90 *------- ------------------------91 _rand24: link a6,#0 *Link stack frames92 tst.l _rseed *See if the seed is zero93 bne rand01 *Jump if not94 * 95 move.l RCLOCK,d0 *Pick up the 200 Hz clock96 moveq.l #16,d1 *Shift it left97 asl.l d1,d0 *...98 or.l RCLOCK,d0 *OR in current 200 Hz clock99 move.l d0,_rseed *Use that as the seed100 * 101 rand01: move.l #PI,-(a7) *Put PI on the stack102 move.l _rseed,-(a7) *... and _rseed, too103 bsr mult32 *Multiply them104 addq.l #8,a7 *Cleanup stack105 addq.l #1,d0 *Add 1 to the result106 move.l d0,_rseed *Save as new seed107 asr.l #8,d0 *Make it a 24 bit number108 and.l # $00FFFFFF,d0 *...109 unlk a6 *Unlink stack frames110 rts *Return to caller111 * 112 *------------------------------------------------------------------------------88 89 | _rand24 -- Generate a random number 90 | ------- ------------------------ 91 _rand24: link a6,#0 | Link stack frames 92 tst.l _rseed | See if the seed is zero 93 bne rand01 | Jump if not 94 95 move.l RCLOCK,d0 | Pick up the 200 Hz clock 96 moveq.l #16,d1 | Shift it left 97 asl.l d1,d0 | ... 98 or.l RCLOCK,d0 | OR in current 200 Hz clock 99 move.l d0,_rseed | Use that as the seed 100 101 rand01: move.l #PI,-(a7) | Put PI on the stack 102 move.l _rseed,-(a7) | ... and _rseed, too 103 bsr mult32 | Multiply them 104 addq.l #8,a7 | Cleanup stack 105 addq.l #1,d0 | Add 1 to the result 106 move.l d0,_rseed | Save as new seed 107 asr.l #8,d0 | Make it a 24 bit number 108 and.l #0x00FFFFFF,d0 | ... 109 unlk a6 | Unlink stack frames 110 rts | Return to caller 111 112 | ------------------------------------------------------------------------------ 113 113 .bss 114 *------------------------------------------------------------------------------115 * 116 _rseed: .ds.l 1 *random number seed117 * 114 | ------------------------------------------------------------------------------ 115 116 _rseed: .ds.l 1 | random number seed 117 118 118 .end -
lib700/setjmp.s
rf40a309 r4f508e6 1 *------------------------------------------------------------------------------2 *setjmp.s -- Unix(tm) compatible setjmp(env) and longjmp(env,ret)3 *Version 3 -- 1987-06-16 -- D.N. Lynx Crowe4 *------------------------------------------------------------------------------5 * 1 | ------------------------------------------------------------------------------ 2 | setjmp.s -- Unix(tm) compatible setjmp(env) and longjmp(env,ret) 3 | Version 3 -- 1987-06-16 -- D.N. Lynx Crowe 4 | ------------------------------------------------------------------------------ 5 6 6 .text 7 * 7 8 8 .xdef _setjmp,_longjmp 9 * 10 _setjmp: movea.l 4(a7),a0 *Get env pointer11 move.l (a7),(a0) *Put return address in env12 movem.l d1-d7/a1-a7,4(a0) *Save registers in env13 moveq.l #0,d0 *Set return value to 014 rts *Return to caller15 * 16 _longjmp: move.w 8(a7),d0 *Get ret value17 bne lj1 *Jump if non-zero18 * 19 moveq.l #1,d0 *Force return value to 120 * 21 lj1: movea.l 4(a7),a0 *Get env pointer22 movem.l 4(a0),d1-d7/a1-a7 *Restore registers from env23 move.l (a0),(a7) *Get return address from env24 rts *Return to caller25 * 9 10 _setjmp: movea.l 4(a7),a0 | Get env pointer 11 move.l (a7),(a0) | Put return address in env 12 movem.l d1-d7/a1-a7,4(a0) | Save registers in env 13 moveq.l #0,d0 | Set return value to 0 14 rts | Return to caller 15 16 _longjmp: move.w 8(a7),d0 | Get ret value 17 bne lj1 | Jump if non-zero 18 19 moveq.l #1,d0 | Force return value to 1 20 21 lj1: movea.l 4(a7),a0 | Get env pointer 22 movem.l 4(a0),d1-d7/a1-a7 | Restore registers from env 23 move.l (a0),(a7) | Get return address from env 24 rts | Return to caller 25 26 26 .end -
lib700/uldiv.s
rf40a309 r4f508e6 1 *------------------------------------------------------------------------------2 *uldiv.s -- unsigned long division, with remainder3 *Version 2 -- 1987-06-08 -- D.N. Lynx Crowe4 *Lifted from the Alcyon C library by disassembly so I could fix a bug -5 *_uldivr must be in the bss segment so the code will work in PROM.6 * 7 *long8 *uldiv(dividnd, divisor)9 *long dividnd, divisor;10 * 11 *extern long uldivr;12 * 13 *Divides 'dividnd' by 'divisor', treating both as unsigned14 *long integers. Returns the quotient and leaves the15 *remainder in 'uldivr'. Produces a divide check on division16 * by zero, with $80000000 returned for both quotient and17 *remainder.18 *------------------------------------------------------------------------------1 | ------------------------------------------------------------------------------ 2 | uldiv.s -- unsigned long division, with remainder 3 | Version 2 -- 1987-06-08 -- D.N. Lynx Crowe 4 | Lifted from the Alcyon C library by disassembly so I could fix a bug - 5 | _uldivr must be in the bss segment so the code will work in PROM. 6 7 | long 8 | uldiv(dividnd, divisor) 9 | long dividnd, divisor; 10 11 | extern long uldivr; 12 13 | Divides 'dividnd' by 'divisor', treating both as unsigned 14 | long integers. Returns the quotient and leaves the 15 | remainder in 'uldivr'. Produces a divide check on division 16 | by zero, with 0x80000000 returned for both quotient and 17 | remainder. 18 | ------------------------------------------------------------------------------ 19 19 .text 20 * 20 21 21 .xdef _uldiv,_uldivr 22 * 23 DIVIDEND .equ824 DIVISOR .equ1225 * 26 _uldiv: link a6,#0 *Link stack frames27 movem.l d3-d7,-(a7) *Save registers28 move.l DIVIDEND(a6),d7 *d7 = DIVIDEND29 move.l DIVISOR(a6),d6 *d6 = DIVISOR30 tst.l d6 *Divide by zero ?31 bne notdzero *Jump if not32 * 33 move.l # $80000000,_uldivr *Force error result34 move.l # $80000000,d0 *... by dividing35 divu #0,d0 *... by zero36 bra ulexit *... then exit37 * 38 notdzero: cmp.l d7,d6 *Divide underflow ?39 bls notunflo *Jump if not40 * 41 move.l d7,_uldivr *Remainder = dividend42 clr.l d0 *Quotient = 043 bra ulexit *Exit44 * 45 notunflo: cmp.l d6,d7 *Is dividend = divisor ?46 bne startdiv *Go start dividing if not47 * 48 moveq.l #1,d5 *Quotient = 149 clr.l d7 *Remainder = 050 bra setreslt *Go set result51 * 22 23 DIVIDEND = 8 24 DIVISOR = 12 25 26 _uldiv: link a6,#0 | Link stack frames 27 movem.l d3-d7,-(a7) | Save registers 28 move.l DIVIDEND(a6),d7 | d7 = DIVIDEND 29 move.l DIVISOR(a6),d6 | d6 = DIVISOR 30 tst.l d6 | Divide by zero ? 31 bne notdzero | Jump if not 32 33 move.l #0x80000000,_uldivr | Force error result 34 move.l #0x80000000,d0 | ... by dividing 35 divu #0,d0 | ... by zero 36 bra ulexit | ... then exit 37 38 notdzero: cmp.l d7,d6 | Divide underflow ? 39 bls notunflo | Jump if not 40 41 move.l d7,_uldivr | Remainder = dividend 42 clr.l d0 | Quotient = 0 43 bra ulexit | Exit 44 45 notunflo: cmp.l d6,d7 | Is dividend = divisor ? 46 bne startdiv | Go start dividing if not 47 48 moveq.l #1,d5 | Quotient = 1 49 clr.l d7 | Remainder = 0 50 bra setreslt | Go set result 51 52 52 .page 53 * 54 startdiv: moveq.l #1,d4 *Set result bit in d455 * 56 divloop1: cmp.l d6,d7 *Divisor aligned OK ?57 bcs divloop2 *Jump if so58 * 59 move.l d6,d0 *Can we align things better ?60 asl.l #1,d0 *...61 cmp.l d0,d6 *...62 bhi divloop2 *Jump if not63 * 64 asl.l #1,d6 *Shift the divisor65 asl.l #1,d4 *Shift the result bit66 bra divloop1 *Loop for next bit67 * 68 divloop2: clr.l d5 *Clear quotient69 * 70 divloop3: tst.l d4 *More bits to do ?71 beq setreslt *Go set result if not72 * 73 cmp.l d6,d7 *Can we subtract ?74 bcs divloop4 *Jump if not75 * 76 or.l d4,d5 *Set a bit in the quotient77 sub.l d6,d7 *Subtract divisor from dividend78 * 79 divloop4: lsr.l #1,d4 *Shift the result bit80 lsr.l #1,d6 *Shift the divisor81 bra divloop3 *Loop for next bit82 * 83 setreslt: move.l d7,_uldivr *Store remainder84 move.l d5,d0 *Put quotient in d085 * 86 ulexit: tst.l (a7)+ *Discard top of stack87 movem.l (a7)+,d4-d7 *Restore registers88 unlk a6 *Unlink stack frames89 rts *Return to caller90 * 53 54 startdiv: moveq.l #1,d4 | Set result bit in d4 55 56 divloop1: cmp.l d6,d7 | Divisor aligned OK ? 57 bcs divloop2 | Jump if so 58 59 move.l d6,d0 | Can we align things better ? 60 asl.l #1,d0 | ... 61 cmp.l d0,d6 | ... 62 bhi divloop2 | Jump if not 63 64 asl.l #1,d6 | Shift the divisor 65 asl.l #1,d4 | Shift the result bit 66 bra divloop1 | Loop for next bit 67 68 divloop2: clr.l d5 | Clear quotient 69 70 divloop3: tst.l d4 | More bits to do ? 71 beq setreslt | Go set result if not 72 73 cmp.l d6,d7 | Can we subtract ? 74 bcs divloop4 | Jump if not 75 76 or.l d4,d5 | Set a bit in the quotient 77 sub.l d6,d7 | Subtract divisor from dividend 78 79 divloop4: lsr.l #1,d4 | Shift the result bit 80 lsr.l #1,d6 | Shift the divisor 81 bra divloop3 | Loop for next bit 82 83 setreslt: move.l d7,_uldivr | Store remainder 84 move.l d5,d0 | Put quotient in d0 85 86 ulexit: tst.l (a7)+ | Discard top of stack 87 movem.l (a7)+,d4-d7 | Restore registers 88 unlk a6 | Unlink stack frames 89 rts | Return to caller 90 91 91 .bss 92 92 .even 93 * 93 94 94 _uldivr: ds.l 1 95 * 95 96 96 .end -
libcio/ptcl12.s
rf40a309 r4f508e6 1 *------------------------------------------------------------------------------2 *ptcl12.s -- store a cluster entry into the FAT3 *Version 2 -- 1987-10-27 -- D.N. Lynx Crowe4 *------------------------------------------------------------------------------1 | ------------------------------------------------------------------------------ 2 | ptcl12.s -- store a cluster entry into the FAT 3 | Version 2 -- 1987-10-27 -- D.N. Lynx Crowe 4 | ------------------------------------------------------------------------------ 5 5 .text 6 6 .xdef __ptcl12 7 * 8 CL .equ129 VAL .equ1410 CLA .equd711 CLP .equd612 CLT .equd513 FAT .equa514 * 7 8 CL = 12 9 VAL = 14 10 CLA = d7 11 CLP = d6 12 CLT = d5 13 FAT = a5 14 15 15 __ptcl12: link A6,#0 16 16 movem.l CLT-CLA/FAT-FAT,-(sp) 17 17 move.l 8(A6),FAT 18 18 move.w CL(A6),CLA 19 lsr.w CLA19 lsr.w #1,CLA 20 20 add.w CL(A6),CLA 21 21 move.b 1(FAT,CLA.W),CLP … … 24 24 btst #0,CL+1(A6) 25 25 beq L2 26 * 26 27 27 move.w CLP,CLT 28 and.w # $000F,CLT28 and.w #0x000F,CLT 29 29 move.w VAL(A6),D0 30 30 lsl.w #4,D0 31 31 or.w D0,CLT 32 32 bra L3 33 * 33 34 34 L2: move.w CLP,CLT 35 and.w # $F000,CLT35 and.w #0xF000,CLT 36 36 move.w VAL(A6),D0 37 and.w # $0FFF,D037 and.w #0x0FFF,D0 38 38 or.w D0,CLT 39 * 39 40 40 L3: move.b CLT,0(FAT,CLA.W) 41 41 move.w CLT,D0 42 42 lsr.w #8,D0 43 43 move.b D0,1(FAT,CLA.W) 44 * 44 45 45 L1: movem.l (sp)+,CLT-CLA/FAT-FAT 46 46 unlk A6 47 47 rts 48 * 48 49 49 .end -
prolog/fsmain.s
rf40a309 r4f508e6 1 *------------------------------------------------------------------------------2 *fsmain.s -- startup code for the Buchla 700 standalone C runtime library3 *Version 3 -- 1987-06-29 -- D.N. Lynx Crowe4 * 5 *This code clears 'bss' space, sets up some global variables,6 *and calls Croot(), which sets up the file system and calls main().7 * 8 *This routine should be entered with the address of the basepage9 *as its parameter.10 *------------------------------------------------------------------------------1 | ------------------------------------------------------------------------------ 2 | fsmain.s -- startup code for the Buchla 700 standalone C runtime library 3 | Version 3 -- 1987-06-29 -- D.N. Lynx Crowe 4 5 | This code clears 'bss' space, sets up some global variables, 6 | and calls Croot(), which sets up the file system and calls main(). 7 8 | This routine should be entered with the address of the basepage 9 | as its parameter. 10 | ------------------------------------------------------------------------------ 11 11 .text 12 * 12 13 13 .xdef start_ 14 * 14 15 15 .xref _Croot 16 * 16 17 17 .xdef _panic 18 18 .xdef _brk 19 * 19 20 20 .xdef __heap 21 21 .xdef __break 22 22 .xdef __pmesg 23 * 23 24 24 .xdef _errno 25 * 26 p_bbase .equ $18 *bss base27 p_blen .equ $1C *bss length28 * 25 26 p_bbase = 0x18 | bss base 27 p_blen = 0x1C | bss length 28 29 29 .page 30 * 31 *start_ -- Initial entry point -- Must be first object file in link statement32 *------ ------------------------------------------------------------------33 * 34 *WARNING: Hazardous assumptions35 * 36 * We assume that: 37 * 38 *the system has set the stack pointer for us.39 *the system passed us a pointer to a valid basepage.40 *the stack is above the heap.41 *BSS is located in RAM.42 * 43 *If any of these assumptions is in error, we're in for serious trouble.44 * 45 start_: clr.l a6 *Clear frame pointer46 movea.l 4(a7),a1 *Set pointer to base page47 movea.l p_bbase(a1),a0 *Setup to clear bss space48 * 49 start1: clr.w (a0)+ *Clear a word50 cmpa.l a0,a7 *See if we're done51 bne start1 *Loop if not done yet52 * 53 move.l p_bbase(a1),d0 *Calculate break address54 add.l p_blen(a1),d0 *...55 move.l d0,__break *Set initial break56 move.l d0,__heap *Set heap start57 * 58 move.l #0,-(a7) *Pass NULL to Croot (no command line)59 jsr _Croot *call Croot() routine60 addq.l #4,a7 *...61 * 62 move.l #pmsg1,-(a7) *panic(pmsg1);63 jsr _panic *...64 addq.l #4,a7 *...65 * 66 hstop: stop # $2000 *"Die, sucker!"30 31 | start_ -- Initial entry point -- Must be first object file in link statement 32 | ------ ------------------------------------------------------------------ 33 34 | WARNING: Hazardous assumptions 35 36 | We assume that: 37 38 | the system has set the stack pointer for us. 39 | the system passed us a pointer to a valid basepage. 40 | the stack is above the heap. 41 | BSS is located in RAM. 42 43 | If any of these assumptions is in error, we're in for serious trouble. 44 45 start_: movea.l #0,a6 | Clear frame pointer 46 movea.l 4(a7),a1 | Set pointer to base page 47 movea.l p_bbase(a1),a0 | Setup to clear bss space 48 49 start1: clr.w (a0)+ | Clear a word 50 cmpa.l a0,a7 | See if we're done 51 bne start1 | Loop if not done yet 52 53 move.l p_bbase(a1),d0 | Calculate break address 54 add.l p_blen(a1),d0 | ... 55 move.l d0,__break | Set initial break 56 move.l d0,__heap | Set heap start 57 58 move.l #0,-(a7) | Pass NULL to Croot (no command line) 59 jsr _Croot | call Croot() routine 60 addq.l #4,a7 | ... 61 62 move.l #pmsg1,-(a7) | panic(pmsg1); 63 jsr _panic | ... 64 addq.l #4,a7 | ... 65 66 hstop: stop #0x2000 | "Die, sucker!" 67 67 bra hstop 68 * 68 69 69 .page 70 * 71 *_panic -- hard halt for fatal errors72 *------ --------------------------73 _panic: movea.l 4(a7),a0 *Save panic message address74 move.l a0,__pmesg *...75 * 76 trap #15 *Invoke ROMP (we hope ...)77 * 78 pstop: stop # $2700 *HARD HALT70 71 | _panic -- hard halt for fatal errors 72 | ------ -------------------------- 73 _panic: movea.l 4(a7),a0 | Save panic message address 74 move.l a0,__pmesg | ... 75 76 trap #15 | Invoke ROMP (we hope ...) 77 78 pstop: stop #0x2700 | HARD HALT 79 79 bra pstop 80 * 80 81 81 .page 82 * 83 *_brk -- set break value84 *---- ---------------85 *WARNING: This only works if the stack is above the heap.86 * 87 _brk: cmpa.l __break,a7 *compare current break with stack88 bcs pstop *actual stack overflow!89 * 90 movea.l 4(sp),a0 *get new break91 move.l a0,d0 *compare with current stack,92 adda.l # $100,a0 *... including 256-byte slop factor93 cmpa.l a0,a7 *if (sp < a0+256)94 bcs badbrk *bad break;95 * 96 move.l d0,__break *OK break: save the break97 clr.l d0 *Set OK return98 rts *return99 * 100 badbrk: moveq.l #-1,d0 *Load return reg101 rts *Return102 * 82 83 | _brk -- set break value 84 | ---- --------------- 85 | WARNING: This only works if the stack is above the heap. 86 87 _brk: cmpa.l __break,a7 | compare current break with stack 88 bcs pstop | actual stack overflow! 89 90 movea.l 4(sp),a0 | get new break 91 move.l a0,d0 | compare with current stack, 92 adda.l #0x100,a0 | ... including 256-byte slop factor 93 cmpa.l a0,a7 | if (sp < a0+256) 94 bcs badbrk | bad break; 95 96 move.l d0,__break | OK break: save the break 97 clr.l d0 | Set OK return 98 rts | return 99 100 badbrk: moveq.l #-1,d0 | Load return reg 101 rts | Return 102 103 103 .page 104 * 105 ************************************************************************* 106 * Data Area * 107 ************************************************************************* 108 * 104 105 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 106 | Data Area | 107 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 108 109 109 .data 110 * 111 pmsg1: dc.b ' returned from Croot() ',0112 * 113 ************************************************************************* 114 * BSS Area * 115 ************************************************************************* 116 * 110 111 pmsg1: dc.b " returned from Croot() ",0 112 113 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 114 | BSS Area | 115 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 116 117 117 .bss 118 118 .even 119 * 120 __pmesg: ds.l 1 *panic() message string address121 __heap: ds.l 1 *Heap start (initial break)122 __break: ds.l 1 *Current break location123 _errno: ds.w 1 *System error number124 * 119 120 __pmesg: ds.l 1 | panic() message string address 121 __heap: ds.l 1 | Heap start (initial break) 122 __break: ds.l 1 | Current break location 123 _errno: ds.w 1 | System error number 124 125 125 .end -
ram/execins.s
rf40a309 r4f508e6 1 *------------------------------------------------------------------------------2 *execins.s -- execute an instrument selection3 *Version 9 -- 1988-09-09 -- D.N. Lynx Crowe4 * 5 *Hand optimized C object code from: execins.c -- ver 2 -- 1988-06-296 *------------------------------------------------------------------------------7 * 1 | ------------------------------------------------------------------------------ 2 | execins.s -- execute an instrument selection 3 | Version 9 -- 1988-09-09 -- D.N. Lynx Crowe 4 5 | Hand optimized C object code from: execins.c -- ver 2 -- 1988-06-29 6 | ------------------------------------------------------------------------------ 7 8 8 .text 9 * 10 DOUBLED .equ 1 *double output to WS table11 * 9 10 DOUBLED = 1 | double output to WS table 11 12 12 .xdef _execins 13 * 13 14 14 .xref _clrvce 15 15 .xref _execkey 16 * 16 17 17 .xref _io_fpu 18 18 .xref _instmod … … 20 20 .xref _idefs 21 21 .xref _vbufs 22 * 23 *register equates24 *----------------25 SYNC .equD426 OLDSR .equD527 VCE .equD728 * 29 IP .equA530 P1 .equA431 P2 .equA332 * 33 P3 .equA234 P4 .equA135 * 36 *parameter offsets37 *-----------------38 VOICE .equ839 INS .equ1040 TAG .equ1241 * 42 .page 43 * 44 _execins: link A6,#0 *link stack frames45 movem.l D3-VCE/P2-IP,-(sp) *preserve registers46 move.w VOICE(A6),VCE *get voice number47 move.w VCE,D0 *calculate IP48 add.w D0,D0 *...49 add.w D0,D0 *...50 lea vibtabl,A0 *...51 movea.l 0(A0,D0.W),IP *...52 add.l #_vbufs,IP *...53 move.w VCE,(sp) *clrvce(vce)54 jsr _clrvce *...55 tst.w TAG(A6) *if (tag) {56 beq L2 *...57 * 58 move.l IP,P1 *p1 = ip;59 move.w INS(A6),D0 *p2 = &idefs[ins]60 add.w D0,D0 *...61 add.w D0,D0 *...62 lea vibtabl,A0 *...63 movea.l 0(A0,D0.W),P2 *...64 add.l #_idefs,P2 *...65 move.w #1968,D0 *set move count66 * 67 L6: move.w (P2)+,(P1)+ *load voice buffer68 dbra D0,L6 *...69 * 70 .page 71 * 72 move.w VCE,D0 *calculate FPU offset for voice73 move.w #9,D1 *...74 asl.w D1,D0 *...75 asl.w #1,D0 *...76 ext.l D0 *...77 move.l D0,P1 *...78 move.l D0,P3 *...79 add.l #_io_fpu,P1 *point P1 at FPU WS A80 add.l # $202,P1 *...81 lea 1778(IP),P2 *point P2 at instdef WS A82 add.l #_io_fpu,P3 *point P3 at FPU WS B83 add.l #2,P3 *...84 lea 2858(IP),P4 *point P4 at instdef WS B85 move.w #253,D0 *setup move count86 * 22 23 | register equates 24 | ---------------- 25 SYNC = D4 26 OLDSR = D5 27 VCE = D7 28 29 IP = A5 30 P1 = A4 31 P2 = A3 32 33 P3 = A2 34 P4 = A1 35 36 | parameter offsets 37 | ----------------- 38 VOICE = 8 39 INS = 10 40 TAG = 12 41 42 .page 43 44 _execins: link A6,#0 | link stack frames 45 movem.l D3-VCE/P2-IP,-(sp) | preserve registers 46 move.w VOICE(A6),VCE | get voice number 47 move.w VCE,D0 | calculate IP 48 add.w D0,D0 | ... 49 add.w D0,D0 | ... 50 lea vibtabl,A0 | ... 51 movea.l 0(A0,D0.W),IP | ... 52 add.l #_vbufs,IP | ... 53 move.w VCE,(sp) | clrvce(vce) 54 jsr _clrvce | ... 55 tst.w TAG(A6) | if (tag) { 56 beq L2 | ... 57 58 move.l IP,P1 | p1 = ip; 59 move.w INS(A6),D0 | p2 = &idefs[ins] 60 add.w D0,D0 | ... 61 add.w D0,D0 | ... 62 lea vibtabl,A0 | ... 63 movea.l 0(A0,D0.W),P2 | ... 64 add.l #_idefs,P2 | ... 65 move.w #1968,D0 | set move count 66 67 L6: move.w (P2)+,(P1)+ | load voice buffer 68 dbra D0,L6 | ... 69 70 .page 71 72 move.w VCE,D0 | calculate FPU offset for voice 73 move.w #9,D1 | ... 74 asl.w D1,D0 | ... 75 asl.w #1,D0 | ... 76 ext.l D0 | ... 77 move.l D0,P1 | ... 78 move.l D0,P3 | ... 79 add.l #_io_fpu,P1 | point P1 at FPU WS A 80 add.l #0x202,P1 | ... 81 lea 1778(IP),P2 | point P2 at instdef WS A 82 add.l #_io_fpu,P3 | point P3 at FPU WS B 83 add.l #2,P3 | ... 84 lea 2858(IP),P4 | point P4 at instdef WS B 85 move.w #253,D0 | setup move count 86 87 87 .ifne DOUBLED 88 move.l P1,-(a7) *save P1 on stack89 move.l P2,-(a7) *save P2 on stack90 move.l P3,-(a7) *save P3 on stack91 move.l P4,-(a7) *save P4 on stack92 move.w D0,-(a7) *save D0 on stack88 move.l P1,-(a7) | save P1 on stack 89 move.l P2,-(a7) | save P2 on stack 90 move.l P3,-(a7) | save P3 on stack 91 move.l P4,-(a7) | save P4 on stack 92 move.w D0,-(a7) | save D0 on stack 93 93 .endc 94 * 95 move.w SR,OLDSR *turn off FPU interrupts96 move.w # $2200,SR *...97 * 98 L10: move.w (P2)+,(P1)+ *set FPU WS A from instdef99 nop *delay for FPU timing100 nop *...101 nop *...102 move.w (P4)+,(P3)+ *set FPU WS B from instdef103 nop *delay for FPU timing104 nop *...105 dbra D0,L10 *loop until done106 * 94 95 move.w SR,OLDSR | turn off FPU interrupts 96 move.w #0x2200,SR | ... 97 98 L10: move.w (P2)+,(P1)+ | set FPU WS A from instdef 99 nop | delay for FPU timing 100 nop | ... 101 nop | ... 102 move.w (P4)+,(P3)+ | set FPU WS B from instdef 103 nop | delay for FPU timing 104 nop | ... 105 dbra D0,L10 | loop until done 106 107 107 .ifne DOUBLED 108 move.w (a7)+,D0 *restore D0 from stack109 movea.l (a7)+,P4 *restore P4 from stack110 movea.l (a7)+,P3 *restore P3 from stack111 movea.l (a7)+,P2 *restore P2 from stack112 movea.l (a7)+,P1 *restore P1 from stack113 * 114 L10A: move.w (P2)+,(P1)+ *set FPU WS A from instdef115 nop *delay for FPU timing116 nop *...117 nop *...118 move.w (P4)+,(P3)+ *set FPU WS B from instdef119 nop *delay for FPU timing120 nop *...121 dbra D0,L10A *loop until done122 * 108 move.w (a7)+,D0 | restore D0 from stack 109 movea.l (a7)+,P4 | restore P4 from stack 110 movea.l (a7)+,P3 | restore P3 from stack 111 movea.l (a7)+,P2 | restore P2 from stack 112 movea.l (a7)+,P1 | restore P1 from stack 113 114 L10A: move.w (P2)+,(P1)+ | set FPU WS A from instdef 115 nop | delay for FPU timing 116 nop | ... 117 nop | ... 118 move.w (P4)+,(P3)+ | set FPU WS B from instdef 119 nop | delay for FPU timing 120 nop | ... 121 dbra D0,L10A | loop until done 122 123 123 .endc 124 * 125 move.w OLDSR,SR *enable FPU interrupts126 * 127 .page 128 * 129 move.w VCE,A0 *instmod[vce] = FALSE130 add.l A0,A0 *...131 add.l #_instmod,A0 *...132 clr.w (A0) *...133 move.w VCE,A0 *s_inst[vce] = ins134 add.l A0,A0 *...135 add.l #_s_inst,A0 *...136 move.w INS(A6),(A0) *...137 move.b 70(IP),SYNC *get config bits138 ext.w SYNC *...139 asl.w #8,SYNC *...140 btst #2,74(IP) *sync 2nd osc141 beq L15 *...142 * 143 ori.w # $2000,SYNC *...144 * 145 L15: btst #2,75(IP) *sync 3rd osc146 beq L16 *...147 * 148 ori.w # $4000,SYNC *...149 * 150 L16: btst #2,76(IP) *sync 4th osc151 beq L17 *...152 * 153 ori.w # $8000,SYNC *...154 * 155 L17: move.w VCE,A0 *send sync to FPU156 add.l A0,A0 *...157 add.l #_io_fpu,A0 *...158 add.l # $5FE0,A0 *...159 move.w SYNC,(A0) *...160 * 161 L2: move.w #1,(sp) *execkey(-1, 0, vce, 1)162 move.w VCE,-(sp) *...163 clr.w -(sp) *...164 move.w #-1,-(sp) *...165 jsr _execkey *...166 addq.l #6,sp *...167 tst.l (sp)+ *clean up stack168 movem.l (sp)+,SYNC-VCE/P2-IP *restore registers169 unlk A6 *unlink stack frames170 rts *return171 * 172 .page 173 * 124 125 move.w OLDSR,SR | enable FPU interrupts 126 127 .page 128 129 move.w VCE,A0 | instmod[vce] = FALSE 130 add.l A0,A0 | ... 131 add.l #_instmod,A0 | ... 132 clr.w (A0) | ... 133 move.w VCE,A0 | s_inst[vce] = ins 134 add.l A0,A0 | ... 135 add.l #_s_inst,A0 | ... 136 move.w INS(A6),(A0) | ... 137 move.b 70(IP),SYNC | get config bits 138 ext.w SYNC | ... 139 asl.w #8,SYNC | ... 140 btst #2,74(IP) | sync 2nd osc 141 beq L15 | ... 142 143 ori.w #0x2000,SYNC | ... 144 145 L15: btst #2,75(IP) | sync 3rd osc 146 beq L16 | ... 147 148 ori.w #0x4000,SYNC | ... 149 150 L16: btst #2,76(IP) | sync 4th osc 151 beq L17 | ... 152 153 ori.w #0x8000,SYNC | ... 154 155 L17: move.w VCE,A0 | send sync to FPU 156 add.l A0,A0 | ... 157 add.l #_io_fpu,A0 | ... 158 add.l #0x5FE0,A0 | ... 159 move.w SYNC,(A0) | ... 160 161 L2: move.w #1,(sp) | execkey(-1, 0, vce, 1) 162 move.w VCE,-(sp) | ... 163 clr.w -(sp) | ... 164 move.w #-1,-(sp) | ... 165 jsr _execkey | ... 166 addq.l #6,sp | ... 167 tst.l (sp)+ | clean up stack 168 movem.l (sp)+,SYNC-VCE/P2-IP | restore registers 169 unlk A6 | unlink stack frames 170 rts | return 171 172 .page 173 174 174 .data 175 * 176 *vibtabl -- voice and instrument buffer offset table177 *------- ----------------------------------------178 vibtabl: .dc.l 0 *0179 .dc.l 3938 *1180 .dc.l 7876 *2181 .dc.l 11814 *3182 .dc.l 15752 *4183 .dc.l 19690 *5184 .dc.l 23628 *6185 .dc.l 27566 *7186 .dc.l 31504 *8187 .dc.l 35442 *9188 .dc.l 39380 *10189 .dc.l 43318 *11190 .dc.l 47256 *12191 .dc.l 51194 *13192 .dc.l 55132 *14193 .dc.l 59070 *15194 .dc.l 63008 *16195 .dc.l 66946 *17196 .dc.l 70884 *18197 .dc.l 74822 *19198 .dc.l 78760 *20199 .dc.l 82698 *21200 .dc.l 86636 *22201 .dc.l 90574 *23202 .dc.l 94512 *24203 .dc.l 98450 *25204 .dc.l 102388 *26205 .dc.l 106326 *27206 .dc.l 110264 *28207 .dc.l 114202 *29208 .dc.l 118140 *30209 .dc.l 122078 *31210 .dc.l 126016 *32211 .dc.l 129954 *33212 .dc.l 133892 *34213 .dc.l 137830 *35214 .dc.l 141768 *36215 .dc.l 145706 *37216 .dc.l 149644 *38217 .dc.l 153582 *39218 .dc.l 157520 *40219 * 175 176 | vibtabl -- voice and instrument buffer offset table 177 | ------- ---------------------------------------- 178 vibtabl: .dc.l 0 | 0 179 .dc.l 3938 | 1 180 .dc.l 7876 | 2 181 .dc.l 11814 | 3 182 .dc.l 15752 | 4 183 .dc.l 19690 | 5 184 .dc.l 23628 | 6 185 .dc.l 27566 | 7 186 .dc.l 31504 | 8 187 .dc.l 35442 | 9 188 .dc.l 39380 | 10 189 .dc.l 43318 | 11 190 .dc.l 47256 | 12 191 .dc.l 51194 | 13 192 .dc.l 55132 | 14 193 .dc.l 59070 | 15 194 .dc.l 63008 | 16 195 .dc.l 66946 | 17 196 .dc.l 70884 | 18 197 .dc.l 74822 | 19 198 .dc.l 78760 | 20 199 .dc.l 82698 | 21 200 .dc.l 86636 | 22 201 .dc.l 90574 | 23 202 .dc.l 94512 | 24 203 .dc.l 98450 | 25 204 .dc.l 102388 | 26 205 .dc.l 106326 | 27 206 .dc.l 110264 | 28 207 .dc.l 114202 | 29 208 .dc.l 118140 | 30 209 .dc.l 122078 | 31 210 .dc.l 126016 | 32 211 .dc.l 129954 | 33 212 .dc.l 133892 | 34 213 .dc.l 137830 | 35 214 .dc.l 141768 | 36 215 .dc.l 145706 | 37 216 .dc.l 149644 | 38 217 .dc.l 153582 | 39 218 .dc.l 157520 | 40 219 220 220 .end -
ram/execkey.s
rf40a309 r4f508e6 1 *------------------------------------------------------------------------------2 *execkey.s -- execute key -- FPU function start subroutine3 *Version 15 -- 1988-08-29 -- D.N. Lynx Crowe4 *Hand optimized version of execkey() and fnstart() from C compiler output5 *------------------------------------------------------------------------------1 | ------------------------------------------------------------------------------ 2 | execkey.s -- execute key -- FPU function start subroutine 3 | Version 15 -- 1988-08-29 -- D.N. Lynx Crowe 4 | Hand optimized version of execkey() and fnstart() from C compiler output 5 | ------------------------------------------------------------------------------ 6 6 .text 7 * 8 LOC_EOR .equ09 LOC_SUB .equ110 * 7 8 LOC_EOR = 0 9 LOC_SUB = 1 10 11 11 .xdef _execkey 12 * 12 13 13 .xref _xgetran 14 * 14 15 15 .xref _rsntab 16 16 .xref _expbit … … 26 26 .xref _veltab 27 27 .xref _vpsms 28 * 29 .page 30 * 31 *Offsets for execkey() parameters32 * -------------------------------- 33 TRG .equ 8 *WORD -- trigger34 PCH .equ 10 *WORD -- pitch35 VCE .equ 12 *WORD -- voice (0..11)36 TAG .equ 14 *WORD -- I_TM_... inversion tag37 * 38 *Register variables39 *------------------40 A_FP .equ A5 * LONG -- struct idfnhdr *41 A_FPU .equ A4 *LONG -- FPU base address42 A_SMP .equ A3 * LONG -- struct sment *43 * 44 R_FPMANT .equ D7 *WORD -- FPU time mantissa45 R_FPEXP .equ D6 *WORD -- FPU time exponent46 R_FPCTL .equ D5 *WORD -- FPU control word47 R_I .equ D4 *WORD -- loop index48 R_FPVAL .equ D3 *WORD -- FPU value49 * 50 *Local (stack) variables51 *-----------------------52 PT .equ -4 * LONG -- instpnt *53 VEP .equ -8 * LONG -- struct valent *54 OLDI .equ -10 *WORD -- old IPL (sr)55 OCTYPE .equ -12 *WORD -- oscillator 1 mode / scratch56 VP .equ -14 *WORD -- voice # + function # index57 SRCNUM .equ -16 *WORD -- general source #58 SRCVAL .equ -18 *WORD -- general source value59 TSRCVAL .equ -20 *WORD -- temporary general source value60 MLTVAL .equ -22 *WORD -- general source multiplier61 TFPVAL .equ -24 *WORD -- temporary FPU value62 LTMP .equ -28 *LONG -- long temporary63 IP .equ -32 * LONG -- struct instdef *64 GROUP .equ -34 *WORD -- group number << 465 * 66 *Symbolic constants67 *------------------68 LASTLOCL .equ GROUP *last local on the stack69 * 70 FPU_DI .equ $2200 *sr value for disabling FPU interrupts71 PITCHMAX .equ 21920 *maximum pitch value72 VALMAX .equ $00007D00 *maximum FPU value73 VALMIN .equ $FFFF8300 *minimum FPU value74 VBLEN .equ 3938 *length of a voice buffer75 LSPCH .equ 2 *left shift for pitch sources76 * 77 .page 78 * 79 *execkey(trg, pch, vce)80 *short trg, pch, vce;81 *{82 * 28 29 .page 30 31 | Offsets for execkey() parameters 32 | -------------------------------- 33 TRG = 8 | WORD -- trigger 34 PCH = 10 | WORD -- pitch 35 VCE = 12 | WORD -- voice (0..11) 36 TAG = 14 | WORD -- I_TM_... inversion tag 37 38 | Register variables 39 | ------------------ 40 A_FP = A5 | LONG -- struct idfnhdr | 41 A_FPU = A4 | LONG -- FPU base address 42 A_SMP = A3 | LONG -- struct sment | 43 44 R_FPMANT = D7 | WORD -- FPU time mantissa 45 R_FPEXP = D6 | WORD -- FPU time exponent 46 R_FPCTL = D5 | WORD -- FPU control word 47 R_I = D4 | WORD -- loop index 48 R_FPVAL = D3 | WORD -- FPU value 49 50 | Local (stack) variables 51 | ----------------------- 52 PT = -4 | LONG -- instpnt | 53 VEP = -8 | LONG -- struct valent | 54 OLDI = -10 | WORD -- old IPL (sr) 55 OCTYPE = -12 | WORD -- oscillator 1 mode / scratch 56 VP = -14 | WORD -- voice # + function # index 57 SRCNUM = -16 | WORD -- general source # 58 SRCVAL = -18 | WORD -- general source value 59 TSRCVAL = -20 | WORD -- temporary general source value 60 MLTVAL = -22 | WORD -- general source multiplier 61 TFPVAL = -24 | WORD -- temporary FPU value 62 LTMP = -28 | LONG -- long temporary 63 IP = -32 | LONG -- struct instdef | 64 GROUP = -34 | WORD -- group number << 4 65 66 | Symbolic constants 67 | ------------------ 68 LASTLOCL = GROUP | last local on the stack 69 70 FPU_DI = 0x2200 | sr value for disabling FPU interrupts 71 PITCHMAX = 21920 | maximum pitch value 72 VALMAX = 0x00007D00 | maximum FPU value 73 VALMIN = 0xFFFF8300 | minimum FPU value 74 VBLEN = 3938 | length of a voice buffer 75 LSPCH = 2 | left shift for pitch sources 76 77 .page 78 79 | execkey(trg, pch, vce) 80 | short trg, pch, vce; 81 | { 82 83 83 _execkey: link A6,#LASTLOCL 84 84 movem.l D2-R_FPMANT/A_SMP-A_FP,-(sp) 85 * 86 *ip = &vbufs[vce];87 * 85 86 | ip = &vbufs[vce]; 87 88 88 move.w VCE(A6),D0 89 89 asl.w #2,D0 90 90 lea vbtab,A0 91 91 move.l 0(A0,D0.W),IP(A6) 92 * 93 *vce2trg[vce] = trg;94 * 92 93 | vce2trg[vce] = trg; 94 95 95 lsr.w #1,D0 96 96 lea _vce2trg,A0 97 97 move.w TRG(A6),0(A0,D0.W) 98 * 99 *group = (vce2grp[vce] - 1) << 4;100 * 98 99 | group = (vce2grp[vce] - 1) << 4; 100 101 101 move.w VCE(A6),A0 102 102 add.l A0,A0 … … 107 107 asl.w #4,D0 108 108 move.w D0,GROUP(A6) 109 * 110 .page 111 *------------------------------------------------------------------------------112 *Start function 0 -- Frq 1113 *------------------------------------------------------------------------------114 * 115 *if (ip->idhfnc[0].idftmd & I_TM_KEY) {116 * 109 110 .page 111 | ------------------------------------------------------------------------------ 112 | Start function 0 -- Frq 1 113 | ------------------------------------------------------------------------------ 114 115 | if (ip->idhfnc[0].idftmd & I_TM_KEY) { 116 117 117 move.l IP(A6),A0 118 118 move.b 93(A0),D0 … … 121 121 btst #0,D0 122 122 bne FN00A 123 * 123 124 124 jmp FN01 125 * 126 *vp = (vce << 4) + 1;127 * 125 126 | vp = (vce << 4) + 1; 127 128 128 FN00A: move VCE(A6),D0 129 129 asl #4,D0 130 130 add.w #1,D0 131 131 move D0,VP(A6) 132 * 133 *fpu = io_fpu + FPU_OFNC + (vp << 4);134 * 132 133 | fpu = io_fpu + FPU_OFNC + (vp << 4); 134 135 135 asl #5,D0 136 136 ext.l D0 137 137 move.l D0,A_FPU 138 add.l #_io_fpu+ $4000,A_FPU139 * 140 *fp = &ip->idhfnc[0];141 * 138 add.l #_io_fpu+0x4000,A_FPU 139 140 | fp = &ip->idhfnc[0]; 141 142 142 move.l IP(A6),A_FP 143 143 add.l #86,A_FP 144 * 145 *pt = &ip->idhpnt[fp->idfpt1];146 * 144 145 | pt = &ip->idhpnt[fp->idfpt1]; 146 147 147 clr.l D0 148 148 move.b 6(A_FP),D0 … … 154 154 add.l #242,D0 155 155 move.l D0,PT(A6) 156 * 157 .page 158 * 159 *srcnum = group | fp->idfsrc;160 * 156 157 .page 158 159 | srcnum = group | fp->idfsrc; 160 161 161 move.w GROUP(A6),D0 162 162 ext.l D0 … … 165 165 or D1,D0 166 166 move D0,SRCNUM(A6) 167 * 168 *vep = &valents[srcnum];169 * 167 168 | vep = &valents[srcnum]; 169 170 170 add.l D0,D0 171 171 move.l D0,D1 … … 174 174 add.l #_valents,D0 175 175 move.l D0,VEP(A6) 176 * 177 *smp = vpsms[vp];178 * 176 177 | smp = vpsms[vp]; 178 179 179 move VP(A6),A0 180 180 add.l A0,A0 … … 182 182 add.l #_vpsms,A0 183 183 move.l (A0),A_SMP 184 * 185 *if (srcnum NE smp->sm) {186 * 184 185 | if (srcnum NE smp->sm) { 186 187 187 clr D0 188 188 move 10(A_SMP),D0 189 189 cmp SRCNUM(A6),D0 190 190 beq F00L113 191 * 192 *(smp->prv)->nxt = smp->nxt;193 * 191 192 | (smp->prv)->nxt = smp->nxt; 193 194 194 move.l 4(A_SMP),A0 195 195 move.l (A_SMP),(A0) 196 * 197 *(smp->nxt)->prv = smp->prv;198 * 196 197 | (smp->nxt)->prv = smp->prv; 198 199 199 move.l (A_SMP),A0 200 200 move.l 4(A_SMP),4(A0) 201 * 202 * smp->prv = (struct sment *)vep;203 * 201 202 | smp->prv = (struct sment |)vep; 203 204 204 move.l VEP(A6),4(A_SMP) 205 * 206 *smp->nxt = vep->nxt;207 * 205 206 | smp->nxt = vep->nxt; 207 208 208 move.l VEP(A6),A0 209 209 move.l (A0),(A_SMP) 210 * 211 *(vep->nxt)->prv = smp;212 * 210 211 | (vep->nxt)->prv = smp; 212 213 213 move.l VEP(A6),A0 214 214 move.l (A0),A0 215 215 move.l A_SMP,4(A0) 216 * 217 *vep->nxt = smp;218 * 216 217 | vep->nxt = smp; 218 219 219 move.l VEP(A6),A0 220 220 move.l A_SMP,(A0) 221 * 222 *smp->sm = srcnum;223 * 221 222 | smp->sm = srcnum; 223 224 224 move SRCNUM(A6),10(A_SMP) 225 * 226 *}227 * 228 *mltval = fp->idfmlt;229 * 225 226 | } 227 228 | mltval = fp->idfmlt; 229 230 230 F00L113: move 2(A_FP),MLTVAL(A6) 231 * 232 .page 233 * 234 *switch (fp->idfsrc) {235 * 231 232 .page 233 234 | switch (fp->idfsrc) { 235 236 236 move.b 4(A_FP),D0 237 237 ext.w d0 238 238 cmp #10,D0 239 239 bhi F00L122 240 * 240 241 241 asl #2,D0 242 242 lea F00L123,A0 243 243 movea.l 0(A0,D0.W),A0 244 244 jmp (A0) 245 * 246 *case SM_NONE:247 *mltval = 0;248 * 245 246 | case SM_NONE: 247 | mltval = 0; 248 249 249 F00L116: clr MLTVAL(A6) 250 * 251 *tsrcval = 0;252 * 250 251 | tsrcval = 0; 252 253 253 clr TSRCVAL(A6) 254 * 255 *break;256 * 254 255 | break; 256 257 257 bra F00L114 258 * 259 *case SM_RAND:260 *tsrcval = xgetran(mltval);261 * 258 259 | case SM_RAND: 260 | tsrcval = xgetran(mltval); 261 262 262 F00L117: move MLTVAL(A6),(sp) 263 263 jsr _xgetran 264 264 move D0,TSRCVAL(A6) 265 * 266 *break;267 * 265 266 | break; 267 268 268 bra F00L114 269 * 270 *case SM_PTCH:271 *tsrcval = pch;272 * 269 270 | case SM_PTCH: 271 | tsrcval = pch; 272 273 273 F00L118: move PCH(A6),TSRCVAL(A6) 274 * 275 *break;276 * 274 275 | break; 276 277 277 bra F00L114 278 * 279 .page 280 * 281 *case SM_FREQ:282 *tsrcval = ptoftab[(pch >> 7) & 0x00FF];283 * 278 279 .page 280 281 | case SM_FREQ: 282 | tsrcval = ptoftab[(pch >> 7) & 0x00FF]; 283 284 284 F00L119: move.w PCH(A6),D0 285 285 asr.w #7,D0 286 and.w # $00FF,D0286 and.w #0x00FF,D0 287 287 move.w D0,A0 288 288 add.l A0,A0 289 289 add.l #_ptoftab,A0 290 290 move.w (A0),TSRCVAL(A6) 291 * 292 *break;293 * 291 292 | break; 293 294 294 bra F00L114 295 * 296 *case SM_KVEL:297 *tsrcval = veltab[trg];298 * 295 296 | case SM_KVEL: 297 | tsrcval = veltab[trg]; 298 299 299 F00L120: move.w TRG(A6),A0 300 300 add.l A0,A0 301 301 add.l #_veltab,A0 302 302 move.w (A0),TSRCVAL(A6) 303 * 304 *break;305 * 303 304 | break; 305 306 306 bra F00L114 307 * 308 *case SM_KPRS:309 *tsrcval = prstab[trg];310 * 307 308 | case SM_KPRS: 309 | tsrcval = prstab[trg]; 310 311 311 F00L121: move.w TRG(A6),A0 312 312 add.l A0,A0 313 313 add.l #_prstab,A0 314 314 move.w (A0),TSRCVAL(A6) 315 * 316 *break;317 * 315 316 | break; 317 318 318 bra F00L114 319 * 320 *default:321 *tsrcval = vep->val;322 * 319 320 | default: 321 | tsrcval = vep->val; 322 323 323 F00L122: move.l VEP(A6),A0 324 324 move.w 8(A0),TSRCVAL(A6) 325 * 326 *}327 * 328 .page 329 * 330 *srcval = addpch(tsrcval, 0);331 * 325 326 | } 327 328 .page 329 330 | srcval = addpch(tsrcval, 0); 331 332 332 F00L114: move.w TSRCVAL(A6),D0 333 333 ext.l D0 334 334 asr.l #5,D0 335 *sub.l #500,D0335 | sub.l #500,D0 336 336 asl.l #LSPCH,D0 337 337 cmp.l #PITCHMAX,D0 338 338 ble F00L129A 339 * 339 340 340 move.l #PITCHMAX,D0 341 * 341 342 342 F00L129A: move D0,SRCVAL(A6) 343 * 344 .page 345 * 346 *if (pt->ipvsrc) {347 * 343 344 .page 345 346 | if (pt->ipvsrc) { 347 348 348 F00L124: move.l PT(A6),A0 349 349 tst.b 6(A0) 350 350 beq F00L136 351 * 352 *switch (pt->ipvsrc) {353 * 351 352 | switch (pt->ipvsrc) { 353 354 354 move.l PT(A6),A0 355 355 move.b 6(A0),D0 … … 358 358 cmp #9,D0 359 359 bhi F00L144 360 * 360 361 361 asl #2,D0 362 362 lea F00L145,A0 363 363 move.l 0(A0,D0.W),A0 364 364 jmp (A0) 365 * 366 *case SM_RAND:367 *ltmp = xgetran(pt_>ipvmlt);368 * 365 366 | case SM_RAND: 367 | ltmp = xgetran(pt_>ipvmlt); 368 369 369 F00L139: move.l PT(A6),A0 370 370 move 4(A0),(sp) … … 372 372 ext.l D0 373 373 move.l D0,LTMP(A6) 374 * 375 *break;376 * 374 375 | break; 376 377 377 bra F00L137 378 * 379 *case SM_PTCH:380 *ltmp = pch;381 * 378 379 | case SM_PTCH: 380 | ltmp = pch; 381 382 382 F00L140: move PCH(A6),A0 383 383 move.l A0,LTMP(A6) 384 * 385 *break;386 * 384 385 | break; 386 387 387 bra F00L137 388 * 389 .page 390 * 391 *case SM_FREQ:392 *ltmp = ptoftab[(pch >> 7) & 0x00FF];393 * 388 389 .page 390 391 | case SM_FREQ: 392 | ltmp = ptoftab[(pch >> 7) & 0x00FF]; 393 394 394 F00L141: move PCH(A6),D0 395 395 asr #7,D0 … … 401 401 ext.l D0 402 402 move.l D0,LTMP(A6) 403 * 404 *break;405 * 403 404 | break; 405 406 406 bra F00L137 407 * 408 *case SM_KVEL:409 *ltmp = veltab[trg];410 * 407 408 | case SM_KVEL: 409 | ltmp = veltab[trg]; 410 411 411 F00L142: move TRG(A6),A0 412 412 add.l A0,A0 … … 415 415 ext.l D0 416 416 move.l D0,LTMP(A6) 417 * 418 *break;419 * 417 418 | break; 419 420 420 bra F00L137 421 * 422 .page 423 * 424 *case SM_KPRS:425 *ltmp = prstab[trg];426 * 421 422 .page 423 424 | case SM_KPRS: 425 | ltmp = prstab[trg]; 426 427 427 F00L143: move TRG(A6),A0 428 428 add.l A0,A0 … … 431 431 ext.l D0 432 432 move.l D0,LTMP(A6) 433 * 434 *break;435 * 433 434 | break; 435 436 436 bra F00L137 437 * 438 .page 439 * 440 *default:441 *ltmp = valents[group | pt->ipvsrc].val;442 * 437 438 .page 439 440 | default: 441 | ltmp = valents[group | pt->ipvsrc].val; 442 443 443 F00L144: move.l PT(A6),A0 444 444 clr.l D0 … … 454 454 move 8(A0,A1.l),D0 455 455 move.l D0,LTMP(A6) 456 * 457 *}458 * 459 * 460 .page 461 * 462 * ltmp = (ltmp *pt->ipvmlt) >> 15;463 * 456 457 | } 458 459 460 .page 461 462 | ltmp = (ltmp | pt->ipvmlt) >> 15; 463 464 464 F00L137: move.l PT(A6),A0 465 465 move.w 4(A0),D0 … … 469 469 asr.l D1,D0 470 470 move.l D0,LTMP(A6) 471 * 472 *ltmp += (long)pt->ipval;473 * 471 472 | ltmp += (long)pt->ipval; 473 474 474 move.l PT(A6),A0 475 475 move 2(A0),D0 476 476 ext.l D0 477 477 add.l D0,LTMP(A6) 478 * 479 *if (ltmp GT (long)VALMAX)480 *ltmp = (long)VALMAX;481 * 478 479 | if (ltmp GT (long)VALMAX) 480 | ltmp = (long)VALMAX; 481 482 482 cmp.l #VALMAX,LTMP(A6) 483 483 ble F00L146 484 * 484 485 485 move.l #VALMAX,LTMP(A6) 486 486 bra F00L147 487 * 488 *else if (ltmp LT (long)VALMIN)489 *ltmp = (long)VALMIN;490 * 487 488 | else if (ltmp LT (long)VALMIN) 489 | ltmp = (long)VALMIN; 490 491 491 F00L146: cmp.l #VALMIN,LTMP(A6) 492 492 bge F00L147 493 * 493 494 494 move.l #VALMIN,LTMP(A6) 495 * 496 *tfpval = (short)ltmp;497 * 495 496 | tfpval = (short)ltmp; 497 498 498 F00L147: move.w LTMP+2(A6),TFPVAL(A6) 499 499 bra F00L149 500 * 501 *} else {502 * 503 *tfpval = pt->ipval;504 * 500 501 | } else { 502 503 | tfpval = pt->ipval; 504 505 505 F00L136: move.l PT(A6),A0 506 506 move 2(A0),TFPVAL(A6) 507 * 508 *}509 * 510 .page 511 * 512 *fpmant = (((long)pt->iptim & 0x0000FFF0L)513 * *((long)timemlt & 0x0000FFFFL)) >> 15;514 * 507 508 | } 509 510 .page 511 512 | fpmant = (((long)pt->iptim & 0x0000FFF0L) 513 | | ((long)timemlt & 0x0000FFFFL)) >> 15; 514 515 515 F00L149: move.l PT(A6),A0 516 516 move.w (A0),D0 517 517 move.w D0,D2 518 andi.w # $FFF0,D0518 andi.w #0xFFF0,D0 519 519 move.w _timemlt,D1 520 520 muls D1,D0 … … 522 522 asr.l D1,D0 523 523 move D0,R_FPMANT 524 * 525 *fpexp = expbit[pt->iptim & 0x000F];526 * 527 and # $000F,D2524 525 | fpexp = expbit[pt->iptim & 0x000F]; 526 527 and #0x000F,D2 528 528 move D2,A0 529 529 add.l A0,A0 530 530 add.l #_expbit,A0 531 531 move (A0),R_FPEXP 532 * 533 .page 534 * 535 *octype = ip->idhos1c & OC_MOD;536 * 532 533 .page 534 535 | octype = ip->idhos1c & OC_MOD; 536 537 537 F00L152: move.l IP(A6),A0 538 538 move.b 74(A0),D0 539 539 and #3,D0 540 * 541 *if ((octype EQ OC_FRQ) OR (octype EQ OC_PCH))542 * 540 541 | if ((octype EQ OC_FRQ) OR (octype EQ OC_PCH)) 542 543 543 cmp #2,D0 544 544 beq F00L1001 545 * 545 546 546 cmp #3,D0 547 547 bne F00L153 548 * 549 *fp->idfpch = ip->idhos1v;550 * 548 549 | fp->idfpch = ip->idhos1v; 550 551 551 F00L1001: move.l IP(A6),A0 552 552 move 78(A0),(A_FP) 553 553 bra F00L154 554 * 555 *else556 *fp->idfpch = pch + ip->idhos1v;557 * 554 555 | else 556 | fp->idfpch = pch + ip->idhos1v; 557 558 558 F00L153: move.w PCH(A6),D0 559 559 ext.l D0 … … 561 561 ext.l D1 562 562 add.l d1,d0 563 * 564 *if (fp->idfpch > PITCHMAX)565 *fp->idfpch = PITCHMAX;566 * 563 564 | if (fp->idfpch > PITCHMAX) 565 | fp->idfpch = PITCHMAX; 566 567 567 cmp.l #PITCHMAX,d0 568 568 ble F00153A 569 * 569 570 570 move.l #PITCHMAX,d0 571 * 571 572 572 F00153A: move.w d0,(A_FP) 573 * 574 *fpval = addpch(tfpval, fp->idfpch);575 * 573 574 | fpval = addpch(tfpval, fp->idfpch); 575 576 576 F00L154: move.w TFPVAL(A6),D1 577 577 ext.l D1 … … 584 584 cmp.l #PITCHMAX,D0 585 585 ble F00L154A 586 * 586 587 587 move.l #PITCHMAX,D0 588 * 588 589 589 F00L154A: move D0,R_FPVAL 590 * 591 .page 592 * 590 591 .page 592 593 593 move.b 5(A_FP),D0 594 594 ext.w D0 595 595 sub.w #1,D0 596 596 movea.l PT(A6),A0 597 * 598 *oldi = setipl(FPU_DI);599 * 597 598 | oldi = setipl(FPU_DI); 599 600 600 move sr,OLDI(A6) 601 601 move #FPU_DI,sr 602 * 602 603 603 F00L168: clr.b 10(A0) 604 604 add.l #12,A0 605 605 dbra D0,F00L168 606 * 607 .page 608 * 609 *fp->idftmd ^= I_NVBITS;610 * 606 607 .page 608 609 | fp->idftmd ^= I_NVBITS; 610 611 611 F00L165: eor.b #24,7(A_FP) 612 * 613 *fpctl = (fp->idftmd & (I_NRATIO | I_NVBITS)) | 0x0003;614 * 612 613 | fpctl = (fp->idftmd & (I_NRATIO | I_NVBITS)) | 0x0003; 614 615 615 move.b 7(A_FP),R_FPCTL 616 616 and #28,R_FPCTL 617 617 or #3,R_FPCTL 618 * 619 *fp->idfcpt = fp->idfpt1;620 * 618 619 | fp->idfcpt = fp->idfpt1; 620 621 621 move.b 6(A_FP),8(A_FP) 622 * 623 *fp->idftmd |= I_ACTIVE;624 * 622 623 | fp->idftmd |= I_ACTIVE; 624 625 625 or.b #2,7(A_FP) 626 * 627 *fp->idftrf = trg;628 * 626 627 | fp->idftrf = trg; 628 629 629 move TRG(A6),10(A_FP) 630 * 631 * *(fpu + (long)FPU_TCV1) = srcval;632 * 633 move SRCVAL(A6), $8(A_FPU)634 * 635 *++octype;636 * 630 631 | |(fpu + (long)FPU_TCV1) = srcval; 632 633 move SRCVAL(A6),0x8(A_FPU) 634 635 | ++octype; 636 637 637 add #1,OCTYPE(A6) 638 * 639 * *(fpu + (long)FPU_TSF1) = mltval;640 * 641 move MLTVAL(A6), $A(A_FPU)642 * 643 *++octype;644 * 638 639 | |(fpu + (long)FPU_TSF1) = mltval; 640 641 move MLTVAL(A6),0xA(A_FPU) 642 643 | ++octype; 644 645 645 add #1,OCTYPE(A6) 646 * 647 * *(fpu + (long)FPU_TMNT) = fpmant;648 * 649 move R_FPMANT, $14(A_FPU)650 * 651 *++octype;652 * 646 647 | |(fpu + (long)FPU_TMNT) = fpmant; 648 649 move R_FPMANT,0x14(A_FPU) 650 651 | ++octype; 652 653 653 add #1,OCTYPE(A6) 654 * 655 * *(fpu + (long)FPU_TEXP) = fpexp;656 * 657 move R_FPEXP, $16(A_FPU)658 * 659 *++octype;660 * 654 655 | |(fpu + (long)FPU_TEXP) = fpexp; 656 657 move R_FPEXP,0x16(A_FPU) 658 659 | ++octype; 660 661 661 add #1,OCTYPE(A6) 662 * 663 .page 664 * 665 *if (fp->idftmd & I_VNSUBN)666 * 662 663 .page 664 665 | if (fp->idftmd & I_VNSUBN) 666 667 667 btst #3,7(A_FP) 668 668 beq F00L169 669 * 670 * *(fpu + (long)FPU_TNV1) = fpval;671 * 672 move R_FPVAL, $1C(A_FPU)669 670 | |(fpu + (long)FPU_TNV1) = fpval; 671 672 move R_FPVAL,0x1C(A_FPU) 673 673 bra F00L170 674 * 675 *else676 * *(fpu + (long)FPU_TNV0) = fpval;677 * 674 675 | else 676 | |(fpu + (long)FPU_TNV0) = fpval; 677 678 678 F00L169: move R_FPVAL,2(A_FPU) 679 * 680 *++octype;681 * 679 680 | ++octype; 681 682 682 F00L170: add #1,OCTYPE(A6) 683 * 684 * *(fpu + (long)FPU_TCTL) = fpctl;685 * 683 684 | |(fpu + (long)FPU_TCTL) = fpctl; 685 686 686 move R_FPCTL,(A_FPU) 687 * 688 *setipl(oldi);689 * 687 688 | setipl(oldi); 689 690 690 move OLDI(A6),sr 691 *}692 * 693 .page 694 *------------------------------------------------------------------------------695 *Start function 1 -- Frq 2696 *------------------------------------------------------------------------------697 *if (legato) {698 * 699 *legato = 0;700 *return;701 *}691 | } 692 693 .page 694 | ------------------------------------------------------------------------------ 695 | Start function 1 -- Frq 2 696 | ------------------------------------------------------------------------------ 697 | if (legato) { 698 699 | legato = 0; 700 | return; 701 | } 702 702 FN01: tst.w _legato 703 703 beq FN01AA 704 * 704 705 705 clr.w _legato 706 706 bra FNEXIT 707 * 708 *if (ip->idhfnc[1].idftmd & I_TM_KEY) {709 * 707 708 | if (ip->idhfnc[1].idftmd & I_TM_KEY) { 709 710 710 FN01AA: move.l IP(A6),A0 711 711 move.b 105(A0),D0 … … 714 714 btst #0,D0 715 715 bne FN01A 716 * 716 717 717 jmp FN02 718 * 719 *vp = (vce << 4) + 3;720 * 718 719 | vp = (vce << 4) + 3; 720 721 721 FN01A: move VCE(A6),D0 722 722 asl #4,D0 723 723 add.w #3,D0 724 724 move D0,VP(A6) 725 * 726 *fpu = io_fpu + FPU_OFNC + (vp << 4);727 * 725 726 | fpu = io_fpu + FPU_OFNC + (vp << 4); 727 728 728 asl #5,D0 729 729 ext.l D0 730 730 move.l D0,A_FPU 731 add.l #_io_fpu+ $4000,A_FPU732 * 733 *fp = &ip->idhfnc[1];734 * 731 add.l #_io_fpu+0x4000,A_FPU 732 733 | fp = &ip->idhfnc[1]; 734 735 735 move.l #12,A_FP 736 736 add.l IP(A6),A_FP 737 737 add.l #86,A_FP 738 * 739 *pt = &ip->idhpnt[fp->idfpt1];740 * 738 739 | pt = &ip->idhpnt[fp->idfpt1]; 740 741 741 clr.l D0 742 742 move.b 6(A_FP),D0 … … 748 748 add.l #242,D0 749 749 move.l D0,PT(A6) 750 * 751 .page 752 * 753 *srcnum = group | fp->idfsrc;754 * 750 751 .page 752 753 | srcnum = group | fp->idfsrc; 754 755 755 move.w GROUP(A6),D0 756 756 ext.l D0 … … 759 759 or D1,D0 760 760 move D0,SRCNUM(A6) 761 * 762 *vep = &valents[srcnum];763 * 761 762 | vep = &valents[srcnum]; 763 764 764 add.l D0,D0 765 765 move.l D0,D1 … … 768 768 add.l #_valents,D0 769 769 move.l D0,VEP(A6) 770 * 771 *smp = vpsms[vp];772 * 770 771 | smp = vpsms[vp]; 772 773 773 move VP(A6),A0 774 774 add.l A0,A0 … … 776 776 add.l #_vpsms,A0 777 777 move.l (A0),A_SMP 778 * 779 *if (srcnum NE smp->sm) {780 * 778 779 | if (srcnum NE smp->sm) { 780 781 781 clr D0 782 782 move 10(A_SMP),D0 783 783 cmp SRCNUM(A6),D0 784 784 beq F01L113 785 * 786 *(smp->prv)->nxt = smp->nxt;787 * 785 786 | (smp->prv)->nxt = smp->nxt; 787 788 788 move.l 4(A_SMP),A0 789 789 move.l (A_SMP),(A0) 790 * 791 *(smp->nxt)->prv = smp->prv;792 * 790 791 | (smp->nxt)->prv = smp->prv; 792 793 793 move.l (A_SMP),A0 794 794 move.l 4(A_SMP),4(A0) 795 * 796 * smp->prv = (struct sment *)vep;797 * 795 796 | smp->prv = (struct sment |)vep; 797 798 798 move.l VEP(A6),4(A_SMP) 799 * 800 *smp->nxt = vep->nxt;801 * 799 800 | smp->nxt = vep->nxt; 801 802 802 move.l VEP(A6),A0 803 803 move.l (A0),(A_SMP) 804 * 805 *(vep->nxt)->prv = smp;806 * 804 805 | (vep->nxt)->prv = smp; 806 807 807 move.l VEP(A6),A0 808 808 move.l (A0),A0 809 809 move.l A_SMP,4(A0) 810 * 811 *vep->nxt = smp;812 * 810 811 | vep->nxt = smp; 812 813 813 move.l VEP(A6),A0 814 814 move.l A_SMP,(A0) 815 * 816 *smp->sm = srcnum;817 * 815 816 | smp->sm = srcnum; 817 818 818 move SRCNUM(A6),10(A_SMP) 819 * 820 *}821 * 822 *mltval = fp->idfmlt;823 * 819 820 | } 821 822 | mltval = fp->idfmlt; 823 824 824 F01L113: move 2(A_FP),MLTVAL(A6) 825 * 826 .page 827 * 828 *switch (fp->idfsrc) {829 * 825 826 .page 827 828 | switch (fp->idfsrc) { 829 830 830 move.b 4(A_FP),D0 831 831 ext.w d0 832 832 cmp #10,D0 833 833 bhi F01L122 834 * 834 835 835 asl #2,D0 836 836 lea F01L123,A0 837 837 movea.l 0(A0,D0.W),A0 838 838 jmp (A0) 839 * 840 *case SM_NONE:841 *mltval = 0;842 * 839 840 | case SM_NONE: 841 | mltval = 0; 842 843 843 F01L116: clr MLTVAL(A6) 844 * 845 *tsrcval = 0;846 * 844 845 | tsrcval = 0; 846 847 847 clr TSRCVAL(A6) 848 * 849 *break;850 * 848 849 | break; 850 851 851 bra F01L114 852 * 853 *case SM_RAND:854 *tsrcval = xgetran(mltval);855 * 852 853 | case SM_RAND: 854 | tsrcval = xgetran(mltval); 855 856 856 F01L117: move MLTVAL(A6),(sp) 857 857 jsr _xgetran 858 858 move D0,TSRCVAL(A6) 859 * 860 *break;861 * 859 860 | break; 861 862 862 bra F01L114 863 * 864 *case SM_PTCH:865 *tsrcval = pch;866 * 863 864 | case SM_PTCH: 865 | tsrcval = pch; 866 867 867 F01L118: move PCH(A6),TSRCVAL(A6) 868 * 869 *break;870 * 868 869 | break; 870 871 871 bra F01L114 872 * 873 .page 874 * 875 *case SM_FREQ:876 *tsrcval = ptoftab[(pch >> 7) & 0x00FF];877 * 872 873 .page 874 875 | case SM_FREQ: 876 | tsrcval = ptoftab[(pch >> 7) & 0x00FF]; 877 878 878 F01L119: move PCH(A6),D0 879 879 asr #7,D0 … … 883 883 add.l #_ptoftab,A0 884 884 move (A0),TSRCVAL(A6) 885 * 886 *break;887 * 885 886 | break; 887 888 888 bra F01L114 889 * 890 *case SM_KVEL:891 *tsrcval = veltab[trg];892 * 889 890 | case SM_KVEL: 891 | tsrcval = veltab[trg]; 892 893 893 F01L120: move TRG(A6),A0 894 894 add.l A0,A0 895 895 add.l #_veltab,A0 896 896 move (A0),TSRCVAL(A6) 897 * 898 *break;899 * 897 898 | break; 899 900 900 bra F01L114 901 * 902 *case SM_KPRS:903 *tsrcval = prstab[trg];904 * 901 902 | case SM_KPRS: 903 | tsrcval = prstab[trg]; 904 905 905 F01L121: move TRG(A6),A0 906 906 add.l A0,A0 907 907 add.l #_prstab,A0 908 908 move (A0),TSRCVAL(A6) 909 * 910 *break;911 * 909 910 | break; 911 912 912 bra F01L114 913 * 914 *default:915 *tsrcval = vep->val;916 * 913 914 | default: 915 | tsrcval = vep->val; 916 917 917 F01L122: move.l VEP(A6),A0 918 918 move 8(A0),TSRCVAL(A6) 919 * 920 *}921 * 922 .page 923 * 924 *srcval = addpch(tsrcval, 0);925 * 919 920 | } 921 922 .page 923 924 | srcval = addpch(tsrcval, 0); 925 926 926 F01L114: move.w TSRCVAL(A6),D0 927 927 ext.l D0 928 928 asr.l #5,D0 929 *sub.l #500,D0929 | sub.l #500,D0 930 930 asl.l #LSPCH,D0 931 931 cmp.l #PITCHMAX,D0 932 932 ble F01L129A 933 * 933 934 934 move.l #PITCHMAX,D0 935 * 935 936 936 F01L129A: move D0,SRCVAL(A6) 937 * 938 .page 939 * 940 *if (pt->ipvsrc) {941 * 937 938 .page 939 940 | if (pt->ipvsrc) { 941 942 942 F01L124: move.l PT(A6),A0 943 943 tst.b 6(A0) 944 944 beq F01L136 945 * 946 *switch (pt->ipvsrc) {947 * 945 946 | switch (pt->ipvsrc) { 947 948 948 move.l PT(A6),A0 949 949 move.b 6(A0),D0 … … 952 952 cmp #9,D0 953 953 bhi F01L144 954 * 954 955 955 asl #2,D0 956 956 lea F01L145,A0 957 957 move.l 0(A0,D0.W),A0 958 958 jmp (A0) 959 * 960 *case SM_RAND:961 *ltmp = xgetran(pt_>ipvmlt);962 * 959 960 | case SM_RAND: 961 | ltmp = xgetran(pt_>ipvmlt); 962 963 963 F01L139: move.l PT(A6),A0 964 964 move 4(A0),(sp) … … 966 966 ext.l D0 967 967 move.l D0,LTMP(A6) 968 * 969 *break;970 * 968 969 | break; 970 971 971 bra F01L137 972 * 973 *case SM_PTCH:974 *ltmp = pch;975 * 972 973 | case SM_PTCH: 974 | ltmp = pch; 975 976 976 F01L140: move PCH(A6),A0 977 977 move.l A0,LTMP(A6) 978 * 979 *break;980 * 978 979 | break; 980 981 981 bra F01L137 982 * 983 .page 984 * 985 *case SM_FREQ:986 *ltmp = ptoftab[(pch >> 7) & 0x00FF];987 * 982 983 .page 984 985 | case SM_FREQ: 986 | ltmp = ptoftab[(pch >> 7) & 0x00FF]; 987 988 988 F01L141: move PCH(A6),D0 989 989 asr #7,D0 … … 995 995 ext.l D0 996 996 move.l D0,LTMP(A6) 997 * 998 *break;999 * 997 998 | break; 999 1000 1000 bra F01L137 1001 * 1002 *case SM_KVEL:1003 *ltmp = veltab[trg];1004 * 1001 1002 | case SM_KVEL: 1003 | ltmp = veltab[trg]; 1004 1005 1005 F01L142: move TRG(A6),A0 1006 1006 add.l A0,A0 … … 1009 1009 ext.l D0 1010 1010 move.l D0,LTMP(A6) 1011 * 1012 *break;1013 * 1011 1012 | break; 1013 1014 1014 bra F01L137 1015 * 1016 .page 1017 * 1018 *case SM_KPRS:1019 *ltmp = prstab[trg];1020 * 1015 1016 .page 1017 1018 | case SM_KPRS: 1019 | ltmp = prstab[trg]; 1020 1021 1021 F01L143: move TRG(A6),A0 1022 1022 add.l A0,A0 … … 1025 1025 ext.l D0 1026 1026 move.l D0,LTMP(A6) 1027 * 1028 *break;1029 * 1027 1028 | break; 1029 1030 1030 bra F01L137 1031 * 1032 .page 1033 * 1034 *default:1035 *ltmp = valents[group | pt->ipvsrc].val;1036 * 1031 1032 .page 1033 1034 | default: 1035 | ltmp = valents[group | pt->ipvsrc].val; 1036 1037 1037 F01L144: move.l PT(A6),A0 1038 1038 clr.l D0 … … 1048 1048 move 8(A0,A1.l),D0 1049 1049 move.l D0,LTMP(A6) 1050 * 1051 *}1052 * 1053 * 1054 .page 1055 * 1056 * ltmp = (ltmp *pt->ipvmlt) >> 15;1057 * 1050 1051 | } 1052 1053 1054 .page 1055 1056 | ltmp = (ltmp | pt->ipvmlt) >> 15; 1057 1058 1058 F01L137: move.l PT(A6),A0 1059 1059 move.w 4(A0),D0 … … 1063 1063 asr.l D1,D0 1064 1064 move.l D0,LTMP(A6) 1065 * 1066 *ltmp += (long)pt->ipval;1067 * 1065 1066 | ltmp += (long)pt->ipval; 1067 1068 1068 move.l PT(A6),A0 1069 1069 move 2(A0),D0 1070 1070 ext.l D0 1071 1071 add.l D0,LTMP(A6) 1072 * 1073 *if (ltmp GT (long)VALMAX)1074 *ltmp = (long)VALMAX;1075 * 1072 1073 | if (ltmp GT (long)VALMAX) 1074 | ltmp = (long)VALMAX; 1075 1076 1076 cmp.l #VALMAX,LTMP(A6) 1077 1077 ble F01L146 1078 * 1078 1079 1079 move.l #VALMAX,LTMP(A6) 1080 1080 bra F01L147 1081 * 1082 *else if (ltmp LT (long)VALMIN)1083 *ltmp = (long)VALMIN;1084 * 1081 1082 | else if (ltmp LT (long)VALMIN) 1083 | ltmp = (long)VALMIN; 1084 1085 1085 F01L146: cmp.l #VALMIN,LTMP(A6) 1086 1086 bge F01L147 1087 * 1087 1088 1088 move.l #VALMIN,LTMP(A6) 1089 * 1090 *tfpval = (short)ltmp;1091 * 1089 1090 | tfpval = (short)ltmp; 1091 1092 1092 F01L147: move.w LTMP+2(A6),TFPVAL(A6) 1093 1093 bra F01L149 1094 * 1095 *} else {1096 * 1097 *tfpval = pt->ipval;1098 * 1094 1095 | } else { 1096 1097 | tfpval = pt->ipval; 1098 1099 1099 F01L136: move.l PT(A6),A0 1100 1100 move 2(A0),TFPVAL(A6) 1101 * 1102 *}1103 * 1104 .page 1105 * 1106 *fpmant = (((long)pt->iptom & 0x0000FFF0L)1107 * *((long)timemlt & 0x0000FFFFL)) >> 15;1108 * 1101 1102 | } 1103 1104 .page 1105 1106 | fpmant = (((long)pt->iptom & 0x0000FFF0L) 1107 | | ((long)timemlt & 0x0000FFFFL)) >> 15; 1108 1109 1109 F01L149: move.l PT(A6),A0 1110 1110 move.w (A0),D0 1111 1111 move.w D0,D2 1112 andi.w # $FFF0,D01112 andi.w #0xFFF0,D0 1113 1113 move.w _timemlt,D1 1114 1114 muls D1,D0 … … 1116 1116 asr.l D1,D0 1117 1117 move D0,R_FPMANT 1118 * 1119 *fpexp = expbit[pt->iptim & 0x000F];1120 * 1121 and # $000F,D21118 1119 | fpexp = expbit[pt->iptim & 0x000F]; 1120 1121 and #0x000F,D2 1122 1122 move D2,A0 1123 1123 add.l A0,A0 1124 1124 add.l #_expbit,A0 1125 1125 move (A0),R_FPEXP 1126 * 1127 .page 1128 * 1129 *fp->idfpch = ip->idhos2v;1130 * 1126 1127 .page 1128 1129 | fp->idfpch = ip->idhos2v; 1130 1131 1131 F01L155: move.l IP(A6),A0 1132 1132 move.w 80(A0),(A_FP) 1133 * 1134 *fpval = addpch(tfpval, fp_>idfpch);1135 * 1133 1134 | fpval = addpch(tfpval, fp_>idfpch); 1135 1136 1136 move.w TFPVAL(A6),D1 1137 1137 ext.l D1 … … 1144 1144 cmp.l #PITCHMAX,D0 1145 1145 ble F01L155A 1146 * 1146 1147 1147 move.l #PITCHMAX,D0 1148 * 1148 1149 1149 F01L155A: move D0,R_FPVAL 1150 * 1151 .page 1152 * 1150 1151 .page 1152 1153 1153 move.b 5(A_FP),D0 1154 1154 ext.w D0 1155 1155 sub.w #1,D0 1156 1156 movea.l PT(A6),A0 1157 * 1158 *oldi = setipl(FPU_DI);1159 * 1157 1158 | oldi = setipl(FPU_DI); 1159 1160 1160 move sr,OLDI(A6) 1161 1161 move #FPU_DI,sr 1162 * 1162 1163 1163 F01L168: clr.b 10(A0) 1164 1164 add.l #12,a0 1165 1165 dbra D0,F01L168 1166 * 1167 .page 1168 * 1169 *fp->idftmd ^= I_NVBITS;1170 * 1166 1167 .page 1168 1169 | fp->idftmd ^= I_NVBITS; 1170 1171 1171 F01L165: eor.b #24,7(A_FP) 1172 * 1173 *fpctl = (fp->idftmd & (I_NRATIO | I_NVBITS)) | 0x0003;1174 * 1172 1173 | fpctl = (fp->idftmd & (I_NRATIO | I_NVBITS)) | 0x0003; 1174 1175 1175 move.b 7(A_FP),R_FPCTL 1176 1176 and #28,R_FPCTL 1177 1177 or #3,R_FPCTL 1178 * 1179 *fp->idfcpt = fp->idfpt1;1180 * 1178 1179 | fp->idfcpt = fp->idfpt1; 1180 1181 1181 move.b 6(A_FP),8(A_FP) 1182 * 1183 *fp->idftmd |= I_ACTIVE;1184 * 1182 1183 | fp->idftmd |= I_ACTIVE; 1184 1185 1185 or.b #2,7(A_FP) 1186 * 1187 *fp->idftrf = trg;1188 * 1186 1187 | fp->idftrf = trg; 1188 1189 1189 move TRG(A6),10(A_FP) 1190 * 1191 * *(fpu + (long)FPU_TCV1) = srcval;1192 * 1193 move SRCVAL(A6), $8(A_FPU)1194 * 1195 *++octype;1196 * 1190 1191 | |(fpu + (long)FPU_TCV1) = srcval; 1192 1193 move SRCVAL(A6),0x8(A_FPU) 1194 1195 | ++octype; 1196 1197 1197 add #1,OCTYPE(A6) 1198 * 1199 * *(fpu + (long)FPU_TSF1) = mltval;1200 * 1201 move MLTVAL(A6), $A(A_FPU)1202 * 1203 *++octype;1204 * 1198 1199 | |(fpu + (long)FPU_TSF1) = mltval; 1200 1201 move MLTVAL(A6),0xA(A_FPU) 1202 1203 | ++octype; 1204 1205 1205 add #1,OCTYPE(A6) 1206 * 1207 * *(fpu + (long)FPU_TMNT) = fpmant;1208 * 1209 move R_FPMANT, $14(A_FPU)1210 * 1211 *++octype;1212 * 1206 1207 | |(fpu + (long)FPU_TMNT) = fpmant; 1208 1209 move R_FPMANT,0x14(A_FPU) 1210 1211 | ++octype; 1212 1213 1213 add #1,OCTYPE(A6) 1214 * 1215 * *(fpu + (long)FPU_TEXP) = fpexp;1216 * 1217 move R_FPEXP, $16(A_FPU)1218 * 1219 *++octype;1220 * 1214 1215 | |(fpu + (long)FPU_TEXP) = fpexp; 1216 1217 move R_FPEXP,0x16(A_FPU) 1218 1219 | ++octype; 1220 1221 1221 add #1,OCTYPE(A6) 1222 * 1223 .page 1224 * 1225 *if (fp->idftmd & I_VNSUBN)1226 * 1222 1223 .page 1224 1225 | if (fp->idftmd & I_VNSUBN) 1226 1227 1227 btst #3,7(A_FP) 1228 1228 beq F01L169 1229 * 1230 * *(fpu + (long)FPU_TNV1) = fpval;1231 * 1232 move R_FPVAL, $1C(A_FPU)1229 1230 | |(fpu + (long)FPU_TNV1) = fpval; 1231 1232 move R_FPVAL,0x1C(A_FPU) 1233 1233 bra F01L170 1234 * 1235 *else1236 * *(fpu + (long)FPU_TNV0) = fpval;1237 * 1234 1235 | else 1236 | |(fpu + (long)FPU_TNV0) = fpval; 1237 1238 1238 F01L169: move R_FPVAL,2(A_FPU) 1239 * 1240 *++octype;1241 * 1239 1240 | ++octype; 1241 1242 1242 F01L170: add #1,OCTYPE(A6) 1243 * 1244 * *(fpu + (long)FPU_TCTL) = fpctl;1245 * 1243 1244 | |(fpu + (long)FPU_TCTL) = fpctl; 1245 1246 1246 move R_FPCTL,(A_FPU) 1247 * 1248 *setipl(oldi);1249 * 1247 1248 | setipl(oldi); 1249 1250 1250 move OLDI(A6),sr 1251 * 1252 .page 1253 *------------------------------------------------------------------------------1254 *Start function 2 -- Frq 31255 *------------------------------------------------------------------------------1256 * 1257 *if (ip->idhfnc[2].idftmd & I_TM_KEY) {1258 * 1251 1252 .page 1253 | ------------------------------------------------------------------------------ 1254 | Start function 2 -- Frq 3 1255 | ------------------------------------------------------------------------------ 1256 1257 | if (ip->idhfnc[2].idftmd & I_TM_KEY) { 1258 1259 1259 FN02: move.l IP(A6),A0 1260 1260 move.b 117(A0),D0 … … 1263 1263 btst #0,D0 1264 1264 bne FN02A 1265 * 1265 1266 1266 jmp FN03 1267 * 1268 *vp = (vce << 4) + 5;1269 * 1267 1268 | vp = (vce << 4) + 5; 1269 1270 1270 FN02A: move VCE(A6),D0 1271 1271 asl #4,D0 1272 1272 add.w #5,D0 1273 1273 move D0,VP(A6) 1274 * 1275 *fpu = io_fpu + FPU_OFNC + (vp << 4);1276 * 1274 1275 | fpu = io_fpu + FPU_OFNC + (vp << 4); 1276 1277 1277 asl #5,D0 1278 1278 ext.l D0 1279 1279 move.l D0,A_FPU 1280 add.l #_io_fpu+ $4000,A_FPU1281 * 1282 *fp = &ip->idhfnc[2];1283 * 1280 add.l #_io_fpu+0x4000,A_FPU 1281 1282 | fp = &ip->idhfnc[2]; 1283 1284 1284 move.l #24,A_FP 1285 1285 add.l IP(A6),A_FP 1286 1286 add.l #86,A_FP 1287 * 1288 *pt = &ip->idhpnt[fp->idfpt1];1289 * 1287 1288 | pt = &ip->idhpnt[fp->idfpt1]; 1289 1290 1290 clr.l D0 1291 1291 move.b 6(A_FP),D0 … … 1297 1297 add.l #242,D0 1298 1298 move.l D0,PT(A6) 1299 * 1300 .page 1301 * 1302 *srcnum = group | fp->idfsrc;1303 * 1299 1300 .page 1301 1302 | srcnum = group | fp->idfsrc; 1303 1304 1304 move.w GROUP(A6),D0 1305 1305 ext.l D0 … … 1308 1308 or D1,D0 1309 1309 move D0,SRCNUM(A6) 1310 * 1311 *vep = &valents[srcnum];1312 * 1310 1311 | vep = &valents[srcnum]; 1312 1313 1313 add.l D0,D0 1314 1314 move.l D0,D1 … … 1317 1317 add.l #_valents,D0 1318 1318 move.l D0,VEP(A6) 1319 * 1320 *smp = vpsms[vp];1321 * 1319 1320 | smp = vpsms[vp]; 1321 1322 1322 move VP(A6),A0 1323 1323 add.l A0,A0 … … 1325 1325 add.l #_vpsms,A0 1326 1326 move.l (A0),A_SMP 1327 * 1328 *if (srcnum NE smp->sm) {1329 * 1327 1328 | if (srcnum NE smp->sm) { 1329 1330 1330 clr D0 1331 1331 move 10(A_SMP),D0 1332 1332 cmp SRCNUM(A6),D0 1333 1333 beq F02L113 1334 * 1335 *(smp->prv)->nxt = smp->nxt;1336 * 1334 1335 | (smp->prv)->nxt = smp->nxt; 1336 1337 1337 move.l 4(A_SMP),A0 1338 1338 move.l (A_SMP),(A0) 1339 * 1340 *(smp->nxt)->prv = smp->prv;1341 * 1339 1340 | (smp->nxt)->prv = smp->prv; 1341 1342 1342 move.l (A_SMP),A0 1343 1343 move.l 4(A_SMP),4(A0) 1344 * 1345 * smp->prv = (struct sment *)vep;1346 * 1344 1345 | smp->prv = (struct sment |)vep; 1346 1347 1347 move.l VEP(A6),4(A_SMP) 1348 * 1349 *smp->nxt = vep->nxt;1350 * 1348 1349 | smp->nxt = vep->nxt; 1350 1351 1351 move.l VEP(A6),A0 1352 1352 move.l (A0),(A_SMP) 1353 * 1354 *(vep->nxt)->prv = smp;1355 * 1353 1354 | (vep->nxt)->prv = smp; 1355 1356 1356 move.l VEP(A6),A0 1357 1357 move.l (A0),A0 1358 1358 move.l A_SMP,4(A0) 1359 * 1360 *vep->nxt = smp;1361 * 1359 1360 | vep->nxt = smp; 1361 1362 1362 move.l VEP(A6),A0 1363 1363 move.l A_SMP,(A0) 1364 * 1365 *smp->sm = srcnum;1366 * 1364 1365 | smp->sm = srcnum; 1366 1367 1367 move SRCNUM(A6),10(A_SMP) 1368 * 1369 *}1370 * 1371 *mltval = fp->idfmlt;1372 * 1368 1369 | } 1370 1371 | mltval = fp->idfmlt; 1372 1373 1373 F02L113: move 2(A_FP),MLTVAL(A6) 1374 * 1375 .page 1376 * 1377 *switch (fp->idfsrc) {1378 * 1374 1375 .page 1376 1377 | switch (fp->idfsrc) { 1378 1379 1379 move.b 4(A_FP),D0 1380 1380 ext.w d0 1381 1381 cmp #10,D0 1382 1382 bhi F02L122 1383 * 1383 1384 1384 asl #2,D0 1385 1385 lea F02L123,A0 1386 1386 movea.l 0(A0,D0.W),A0 1387 1387 jmp (A0) 1388 * 1389 *case SM_NONE:1390 *mltval = 0;1391 * 1388 1389 | case SM_NONE: 1390 | mltval = 0; 1391 1392 1392 F02L116: clr MLTVAL(A6) 1393 * 1394 *tsrcval = 0;1395 * 1393 1394 | tsrcval = 0; 1395 1396 1396 clr TSRCVAL(A6) 1397 * 1398 *break;1399 * 1397 1398 | break; 1399 1400 1400 bra F02L114 1401 * 1402 *case SM_RAND:1403 *tsrcval = xgetran(mltval);1404 * 1401 1402 | case SM_RAND: 1403 | tsrcval = xgetran(mltval); 1404 1405 1405 F02L117: move MLTVAL(A6),(sp) 1406 1406 jsr _xgetran 1407 1407 move D0,TSRCVAL(A6) 1408 * 1409 *break;1410 * 1408 1409 | break; 1410 1411 1411 bra F02L114 1412 * 1413 *case SM_PTCH:1414 *tsrcval = pch;1415 * 1412 1413 | case SM_PTCH: 1414 | tsrcval = pch; 1415 1416 1416 F02L118: move PCH(A6),TSRCVAL(A6) 1417 * 1418 *break;1419 * 1417 1418 | break; 1419 1420 1420 bra F02L114 1421 * 1422 .page 1423 * 1424 *case SM_FREQ:1425 *tsrcval = ptoftab[(pch >> 7) & 0x00FF];1426 * 1421 1422 .page 1423 1424 | case SM_FREQ: 1425 | tsrcval = ptoftab[(pch >> 7) & 0x00FF]; 1426 1427 1427 F02L119: move PCH(A6),D0 1428 1428 asr #7,D0 … … 1432 1432 add.l #_ptoftab,A0 1433 1433 move (A0),TSRCVAL(A6) 1434 * 1435 *break;1436 * 1434 1435 | break; 1436 1437 1437 bra F02L114 1438 * 1439 *case SM_KVEL:1440 *tsrcval = veltab[trg];1441 * 1438 1439 | case SM_KVEL: 1440 | tsrcval = veltab[trg]; 1441 1442 1442 F02L120: move TRG(A6),A0 1443 1443 add.l A0,A0 1444 1444 add.l #_veltab,A0 1445 1445 move (A0),TSRCVAL(A6) 1446 * 1447 *break;1448 * 1446 1447 | break; 1448 1449 1449 bra F02L114 1450 * 1451 *case SM_KPRS:1452 *tsrcval = prstab[trg];1453 * 1450 1451 | case SM_KPRS: 1452 | tsrcval = prstab[trg]; 1453 1454 1454 F02L121: move TRG(A6),A0 1455 1455 add.l A0,A0 1456 1456 add.l #_prstab,A0 1457 1457 move (A0),TSRCVAL(A6) 1458 * 1459 *break;1460 * 1458 1459 | break; 1460 1461 1461 bra F02L114 1462 * 1463 *default:1464 *tsrcval = vep->val;1465 * 1462 1463 | default: 1464 | tsrcval = vep->val; 1465 1466 1466 F02L122: move.l VEP(A6),A0 1467 1467 move 8(A0),TSRCVAL(A6) 1468 * 1469 *}1470 * 1471 .page 1472 * 1473 *srcval = addpch(tsrcval, 0);1474 * 1468 1469 | } 1470 1471 .page 1472 1473 | srcval = addpch(tsrcval, 0); 1474 1475 1475 F02L114: move.w TSRCVAL(A6),D0 1476 1476 ext.l D0 1477 1477 asr.l #5,D0 1478 *sub.l #500,D01478 | sub.l #500,D0 1479 1479 asl.l #LSPCH,D0 1480 1480 cmp.l #PITCHMAX,D0 1481 1481 ble F02L129A 1482 * 1482 1483 1483 move.l #PITCHMAX,D0 1484 * 1484 1485 1485 F02L129A: move D0,SRCVAL(A6) 1486 * 1487 .page 1488 * 1489 *if (pt->ipvsrc) {1490 * 1486 1487 .page 1488 1489 | if (pt->ipvsrc) { 1490 1491 1491 F02L124: move.l PT(A6),A0 1492 1492 tst.b 6(A0) 1493 1493 beq F02L136 1494 * 1495 *switch (pt->ipvsrc) {1496 * 1494 1495 | switch (pt->ipvsrc) { 1496 1497 1497 move.l PT(A6),A0 1498 1498 move.b 6(A0),D0 … … 1501 1501 cmp #9,D0 1502 1502 bhi F02L144 1503 * 1503 1504 1504 asl #2,D0 1505 1505 lea F02L145,A0 1506 1506 move.l 0(A0,D0.W),A0 1507 1507 jmp (A0) 1508 * 1509 *case SM_RAND:1510 *ltmp = xgetran(pt_>ipvmlt);1511 * 1508 1509 | case SM_RAND: 1510 | ltmp = xgetran(pt_>ipvmlt); 1511 1512 1512 F02L139: move.l PT(A6),A0 1513 1513 move 4(A0),(sp) … … 1515 1515 ext.l D0 1516 1516 move.l D0,LTMP(A6) 1517 * 1518 *break;1519 * 1517 1518 | break; 1519 1520 1520 bra F02L137 1521 * 1522 *case SM_PTCH:1523 *ltmp = pch;1524 * 1521 1522 | case SM_PTCH: 1523 | ltmp = pch; 1524 1525 1525 F02L140: move PCH(A6),A0 1526 1526 move.l A0,LTMP(A6) 1527 * 1528 *break;1529 * 1527 1528 | break; 1529 1530 1530 bra F02L137 1531 * 1532 .page 1533 * 1534 *case SM_FREQ:1535 *ltmp = ptoftab[(pch >> 7) & 0x00FF];1536 * 1531 1532 .page 1533 1534 | case SM_FREQ: 1535 | ltmp = ptoftab[(pch >> 7) & 0x00FF]; 1536 1537 1537 F02L141: move PCH(A6),D0 1538 1538 asr #7,D0 … … 1544 1544 ext.l D0 1545 1545 move.l D0,LTMP(A6) 1546 * 1547 *break;1548 * 1546 1547 | break; 1548 1549 1549 bra F02L137 1550 * 1551 *case SM_KVEL:1552 *ltmp = veltab[trg];1553 * 1550 1551 | case SM_KVEL: 1552 | ltmp = veltab[trg]; 1553 1554 1554 F02L142: move TRG(A6),A0 1555 1555 add.l A0,A0 … … 1558 1558 ext.l D0 1559 1559 move.l D0,LTMP(A6) 1560 * 1561 *break;1562 * 1560 1561 | break; 1562 1563 1563 bra F02L137 1564 * 1565 .page 1566 * 1567 *case SM_KPRS:1568 *ltmp = prstab[trg];1569 * 1564 1565 .page 1566 1567 | case SM_KPRS: 1568 | ltmp = prstab[trg]; 1569 1570 1570 F02L143: move TRG(A6),A0 1571 1571 add.l A0,A0 … … 1574 1574 ext.l D0 1575 1575 move.l D0,LTMP(A6) 1576 * 1577 *break;1578 * 1576 1577 | break; 1578 1579 1579 bra F02L137 1580 * 1581 .page 1582 * 1583 *default:1584 *ltmp = valents[group | pt->ipvsrc].val;1585 * 1580 1581 .page 1582 1583 | default: 1584 | ltmp = valents[group | pt->ipvsrc].val; 1585 1586 1586 F02L144: move.l PT(A6),A0 1587 1587 clr.l D0 … … 1597 1597 move 8(A0,A1.l),D0 1598 1598 move.l D0,LTMP(A6) 1599 * 1600 *}1601 * 1602 * 1603 .page 1604 * 1605 * ltmp = (ltmp *pt->ipvmlt) >> 15;1606 * 1599 1600 | } 1601 1602 1603 .page 1604 1605 | ltmp = (ltmp | pt->ipvmlt) >> 15; 1606 1607 1607 F02L137: move.l PT(A6),A0 1608 1608 move.w 4(A0),D0 … … 1612 1612 asr.l D1,D0 1613 1613 move.l D0,LTMP(A6) 1614 * 1615 *ltmp += (long)pt->ipval;1616 * 1614 1615 | ltmp += (long)pt->ipval; 1616 1617 1617 move.l PT(A6),A0 1618 1618 move 2(A0),D0 1619 1619 ext.l D0 1620 1620 add.l D0,LTMP(A6) 1621 * 1622 *if (ltmp GT (long)VALMAX)1623 *ltmp = (long)VALMAX;1624 * 1621 1622 | if (ltmp GT (long)VALMAX) 1623 | ltmp = (long)VALMAX; 1624 1625 1625 cmp.l #VALMAX,LTMP(A6) 1626 1626 ble F02L146 1627 * 1627 1628 1628 move.l #VALMAX,LTMP(A6) 1629 1629 bra F02L147 1630 * 1631 *else if (ltmp LT (long)VALMIN)1632 *ltmp = (long)VALMIN;1633 * 1630 1631 | else if (ltmp LT (long)VALMIN) 1632 | ltmp = (long)VALMIN; 1633 1634 1634 F02L146: cmp.l #VALMIN,LTMP(A6) 1635 1635 bge F02L147 1636 * 1636 1637 1637 move.l #VALMIN,LTMP(A6) 1638 * 1639 *tfpval = (short)ltmp;1640 * 1638 1639 | tfpval = (short)ltmp; 1640 1641 1641 F02L147: move.w LTMP+2(A6),TFPVAL(A6) 1642 1642 bra F02L149 1643 * 1644 *} else {1645 * 1646 *tfpval = pt->ipval;1647 * 1643 1644 | } else { 1645 1646 | tfpval = pt->ipval; 1647 1648 1648 F02L136: move.l PT(A6),A0 1649 1649 move 2(A0),TFPVAL(A6) 1650 * 1651 *}1652 * 1653 .page 1654 * 1655 *fpmant = (((long)pt->iptom & 0x0000FFF0L)1656 * *((long)timemlt & 0x0000FFFFL)) >> 15;1657 * 1650 1651 | } 1652 1653 .page 1654 1655 | fpmant = (((long)pt->iptom & 0x0000FFF0L) 1656 | | ((long)timemlt & 0x0000FFFFL)) >> 15; 1657 1658 1658 F02L149: move.l PT(A6),A0 1659 1659 move.w (A0),D0 1660 1660 move.w D0,D2 1661 andi.w # $FFF0,D01661 andi.w #0xFFF0,D0 1662 1662 move.w _timemlt,D1 1663 1663 muls D1,D0 … … 1665 1665 asr.l D1,D0 1666 1666 move D0,R_FPMANT 1667 * 1668 *fpexp = expbit[pt->iptim & 0x000F];1669 * 1670 and # $000F,D21667 1668 | fpexp = expbit[pt->iptim & 0x000F]; 1669 1670 and #0x000F,D2 1671 1671 move D2,A0 1672 1672 add.l A0,A0 1673 1673 add.l #_expbit,A0 1674 1674 move (A0),R_FPEXP 1675 * 1676 .page 1677 * 1678 *fp->idfpch = ip->idhos3v;1679 * 1675 1676 .page 1677 1678 | fp->idfpch = ip->idhos3v; 1679 1680 1680 F02L156: move.l IP(A6),A0 1681 1681 move.w 82(A0),(A_FP) 1682 * 1683 *fpval = addpch(tfpval, fp->idfpch);1684 * 1682 1683 | fpval = addpch(tfpval, fp->idfpch); 1684 1685 1685 move.w TFPVAL(A6),D1 1686 1686 ext.l D1 … … 1693 1693 cmp.l #PITCHMAX,D0 1694 1694 ble F02L156A 1695 * 1695 1696 1696 move.l #PITCHMAX,D0 1697 * 1697 1698 1698 F02L156A: move D0,R_FPVAL 1699 * 1700 .page 1701 * 1699 1700 .page 1701 1702 1702 move.b 5(A_FP),D0 1703 1703 ext.w D0 1704 1704 sub.w #1,D0 1705 1705 movea.l PT(A6),A0 1706 * 1707 *oldi = setipl(FPU_DI);1708 * 1706 1707 | oldi = setipl(FPU_DI); 1708 1709 1709 move sr,OLDI(A6) 1710 1710 move #FPU_DI,sr 1711 * 1711 1712 1712 F02L168: clr.b 10(A0) 1713 1713 add.l #12,a0 1714 1714 dbra D0,F02L168 1715 * 1716 .page 1717 * 1718 *fp->idftmd ^= I_NVBITS;1719 * 1715 1716 .page 1717 1718 | fp->idftmd ^= I_NVBITS; 1719 1720 1720 F02L165: eor.b #24,7(A_FP) 1721 * 1722 *fpctl = (fp->idftmd & (I_NRATIO | I_NVBITS)) | 0x0003;1723 * 1721 1722 | fpctl = (fp->idftmd & (I_NRATIO | I_NVBITS)) | 0x0003; 1723 1724 1724 move.b 7(A_FP),R_FPCTL 1725 1725 and #28,R_FPCTL 1726 1726 or #3,R_FPCTL 1727 * 1728 *fp->idfcpt = fp->idfpt1;1729 * 1727 1728 | fp->idfcpt = fp->idfpt1; 1729 1730 1730 move.b 6(A_FP),8(A_FP) 1731 * 1732 *fp->idftmd |= I_ACTIVE;1733 * 1731 1732 | fp->idftmd |= I_ACTIVE; 1733 1734 1734 or.b #2,7(A_FP) 1735 * 1736 *fp->idftrf = trg;1737 * 1735 1736 | fp->idftrf = trg; 1737 1738 1738 move TRG(A6),10(A_FP) 1739 * 1740 * *(fpu + (long)FPU_TCV1) = srcval;1741 * 1742 move SRCVAL(A6), $8(A_FPU)1743 * 1744 *++octype;1745 * 1739 1740 | |(fpu + (long)FPU_TCV1) = srcval; 1741 1742 move SRCVAL(A6),0x8(A_FPU) 1743 1744 | ++octype; 1745 1746 1746 add #1,OCTYPE(A6) 1747 * 1748 * *(fpu + (long)FPU_TSF1) = mltval;1749 * 1750 move MLTVAL(A6), $A(A_FPU)1751 * 1752 *++octype;1753 * 1747 1748 | |(fpu + (long)FPU_TSF1) = mltval; 1749 1750 move MLTVAL(A6),0xA(A_FPU) 1751 1752 | ++octype; 1753 1754 1754 add #1,OCTYPE(A6) 1755 * 1756 * *(fpu + (long)FPU_TMNT) = fpmant;1757 * 1758 move R_FPMANT, $14(A_FPU)1759 * 1760 *++octype;1761 * 1755 1756 | |(fpu + (long)FPU_TMNT) = fpmant; 1757 1758 move R_FPMANT,0x14(A_FPU) 1759 1760 | ++octype; 1761 1762 1762 add #1,OCTYPE(A6) 1763 * 1764 * *(fpu + (long)FPU_TEXP) = fpexp;1765 * 1766 move R_FPEXP, $16(A_FPU)1767 * 1768 *++octype;1769 * 1763 1764 | |(fpu + (long)FPU_TEXP) = fpexp; 1765 1766 move R_FPEXP,0x16(A_FPU) 1767 1768 | ++octype; 1769 1770 1770 add #1,OCTYPE(A6) 1771 * 1772 .page 1773 * 1774 *if (fp->idftmd & I_VNSUBN)1775 * 1771 1772 .page 1773 1774 | if (fp->idftmd & I_VNSUBN) 1775 1776 1776 btst #3,7(A_FP) 1777 1777 beq F02L169 1778 * 1779 * *(fpu + (long)FPU_TNV1) = fpval;1780 * 1781 move R_FPVAL, $1C(A_FPU)1778 1779 | |(fpu + (long)FPU_TNV1) = fpval; 1780 1781 move R_FPVAL,0x1C(A_FPU) 1782 1782 bra F02L170 1783 * 1784 *else1785 * *(fpu + (long)FPU_TNV0) = fpval;1786 * 1783 1784 | else 1785 | |(fpu + (long)FPU_TNV0) = fpval; 1786 1787 1787 F02L169: move R_FPVAL,2(A_FPU) 1788 * 1789 *++octype;1790 * 1788 1789 | ++octype; 1790 1791 1791 F02L170: add #1,OCTYPE(A6) 1792 * 1793 * *(fpu + (long)FPU_TCTL) = fpctl;1794 * 1792 1793 | |(fpu + (long)FPU_TCTL) = fpctl; 1794 1795 1795 move R_FPCTL,(A_FPU) 1796 * 1797 *setipl(oldi);1798 * 1796 1797 | setipl(oldi); 1798 1799 1799 move OLDI(A6),sr 1800 * 1801 .page 1802 *------------------------------------------------------------------------------1803 *Start function 3 -- Frq 41804 *------------------------------------------------------------------------------1805 * 1806 *if (ip->idhfnc[3].idftmd & I_TM_KEY) {1807 * 1800 1801 .page 1802 | ------------------------------------------------------------------------------ 1803 | Start function 3 -- Frq 4 1804 | ------------------------------------------------------------------------------ 1805 1806 | if (ip->idhfnc[3].idftmd & I_TM_KEY) { 1807 1808 1808 FN03: move.l IP(A6),A0 1809 1809 move.b 129(A0),D0 … … 1812 1812 btst #0,D0 1813 1813 bne FN03A 1814 * 1814 1815 1815 jmp FN04 1816 * 1817 *vp = (vce << 4) + 7;1818 * 1816 1817 | vp = (vce << 4) + 7; 1818 1819 1819 FN03A: move VCE(A6),D0 1820 1820 asl #4,D0 1821 1821 add.w #7,D0 1822 1822 move D0,VP(A6) 1823 * 1824 *fpu = io_fpu + FPU_OFNC + (vp << 4);1825 * 1823 1824 | fpu = io_fpu + FPU_OFNC + (vp << 4); 1825 1826 1826 asl #5,D0 1827 1827 ext.l D0 1828 1828 move.l D0,A_FPU 1829 add.l #_io_fpu+ $4000,A_FPU1830 * 1831 *fp = &ip->idhfnc[3];1832 * 1829 add.l #_io_fpu+0x4000,A_FPU 1830 1831 | fp = &ip->idhfnc[3]; 1832 1833 1833 move.l #36,A_FP 1834 1834 add.l IP(A6),A_FP 1835 1835 add.l #86,A_FP 1836 * 1837 *pt = &ip->idhpnt[fp->idfpt1];1838 * 1836 1837 | pt = &ip->idhpnt[fp->idfpt1]; 1838 1839 1839 clr.l D0 1840 1840 move.b 6(A_FP),D0 … … 1846 1846 add.l #242,D0 1847 1847 move.l D0,PT(A6) 1848 * 1849 .page 1850 * 1851 *srcnum = group | fp->idfsrc;1852 * 1848 1849 .page 1850 1851 | srcnum = group | fp->idfsrc; 1852 1853 1853 move.w GROUP(A6),D0 1854 1854 ext.l D0 … … 1857 1857 or D1,D0 1858 1858 move D0,SRCNUM(A6) 1859 * 1860 *vep = &valents[srcnum];1861 * 1859 1860 | vep = &valents[srcnum]; 1861 1862 1862 add.l D0,D0 1863 1863 move.l D0,D1 … … 1866 1866 add.l #_valents,D0 1867 1867 move.l D0,VEP(A6) 1868 * 1869 *smp = vpsms[vp];1870 * 1868 1869 | smp = vpsms[vp]; 1870 1871 1871 move VP(A6),A0 1872 1872 add.l A0,A0 … … 1874 1874 add.l #_vpsms,A0 1875 1875 move.l (A0),A_SMP 1876 * 1877 *if (srcnum NE smp->sm) {1878 * 1876 1877 | if (srcnum NE smp->sm) { 1878 1879 1879 clr D0 1880 1880 move 10(A_SMP),D0 1881 1881 cmp SRCNUM(A6),D0 1882 1882 beq F03L113 1883 * 1884 *(smp->prv)->nxt = smp->nxt;1885 * 1883 1884 | (smp->prv)->nxt = smp->nxt; 1885 1886 1886 move.l 4(A_SMP),A0 1887 1887 move.l (A_SMP),(A0) 1888 * 1889 *(smp->nxt)->prv = smp->prv;1890 * 1888 1889 | (smp->nxt)->prv = smp->prv; 1890 1891 1891 move.l (A_SMP),A0 1892 1892 move.l 4(A_SMP),4(A0) 1893 * 1894 * smp->prv = (struct sment *)vep;1895 * 1893 1894 | smp->prv = (struct sment |)vep; 1895 1896 1896 move.l VEP(A6),4(A_SMP) 1897 * 1898 *smp->nxt = vep->nxt;1899 * 1897 1898 | smp->nxt = vep->nxt; 1899 1900 1900 move.l VEP(A6),A0 1901 1901 move.l (A0),(A_SMP) 1902 * 1903 *(vep->nxt)->prv = smp;1904 * 1902 1903 | (vep->nxt)->prv = smp; 1904 1905 1905 move.l VEP(A6),A0 1906 1906 move.l (A0),A0 1907 1907 move.l A_SMP,4(A0) 1908 * 1909 *vep->nxt = smp;1910 * 1908 1909 | vep->nxt = smp; 1910 1911 1911 move.l VEP(A6),A0 1912 1912 move.l A_SMP,(A0) 1913 * 1914 *smp->sm = srcnum;1915 * 1913 1914 | smp->sm = srcnum; 1915 1916 1916 move SRCNUM(A6),10(A_SMP) 1917 * 1918 *}1919 * 1920 *mltval = fp->idfmlt;1921 * 1917 1918 | } 1919 1920 | mltval = fp->idfmlt; 1921 1922 1922 F03L113: move 2(A_FP),MLTVAL(A6) 1923 * 1924 .page 1925 * 1926 *switch (fp->idfsrc) {1927 * 1923 1924 .page 1925 1926 | switch (fp->idfsrc) { 1927 1928 1928 move.b 4(A_FP),D0 1929 1929 ext.w d0 1930 1930 cmp #10,D0 1931 1931 bhi F03L122 1932 * 1932 1933 1933 asl #2,D0 1934 1934 lea F03L123,A0 1935 1935 movea.l 0(A0,D0.W),A0 1936 1936 jmp (A0) 1937 * 1938 *case SM_NONE:1939 *mltval = 0;1940 * 1937 1938 | case SM_NONE: 1939 | mltval = 0; 1940 1941 1941 F03L116: clr MLTVAL(A6) 1942 * 1943 *tsrcval = 0;1944 * 1942 1943 | tsrcval = 0; 1944 1945 1945 clr TSRCVAL(A6) 1946 * 1947 *break;1948 * 1946 1947 | break; 1948 1949 1949 bra F03L114 1950 * 1951 *case SM_RAND:1952 *tsrcval = xgetran(mltval);1953 * 1950 1951 | case SM_RAND: 1952 | tsrcval = xgetran(mltval); 1953 1954 1954 F03L117: move MLTVAL(A6),(sp) 1955 1955 jsr _xgetran 1956 1956 move D0,TSRCVAL(A6) 1957 * 1958 *break;1959 * 1957 1958 | break; 1959 1960 1960 bra F03L114 1961 * 1962 *case SM_PTCH:1963 *tsrcval = pch;1964 * 1961 1962 | case SM_PTCH: 1963 | tsrcval = pch; 1964 1965 1965 F03L118: move PCH(A6),TSRCVAL(A6) 1966 * 1967 *break;1968 * 1966 1967 | break; 1968 1969 1969 bra F03L114 1970 * 1971 .page 1972 * 1973 *case SM_FREQ:1974 *tsrcval = ptoftab[(pch >> 7) & 0x00FF];1975 * 1970 1971 .page 1972 1973 | case SM_FREQ: 1974 | tsrcval = ptoftab[(pch >> 7) & 0x00FF]; 1975 1976 1976 F03L119: move PCH(A6),D0 1977 1977 asr #7,D0 … … 1981 1981 add.l #_ptoftab,A0 1982 1982 move (A0),TSRCVAL(A6) 1983 * 1984 *break;1985 * 1983 1984 | break; 1985 1986 1986 bra F03L114 1987 * 1988 *case SM_KVEL:1989 *tsrcval = veltab[trg];1990 * 1987 1988 | case SM_KVEL: 1989 | tsrcval = veltab[trg]; 1990 1991 1991 F03L120: move TRG(A6),A0 1992 1992 add.l A0,A0 1993 1993 add.l #_veltab,A0 1994 1994 move (A0),TSRCVAL(A6) 1995 * 1996 *break;1997 * 1995 1996 | break; 1997 1998 1998 bra F03L114 1999 * 2000 *case SM_KPRS:2001 *tsrcval = prstab[trg];2002 * 1999 2000 | case SM_KPRS: 2001 | tsrcval = prstab[trg]; 2002 2003 2003 F03L121: move TRG(A6),A0 2004 2004 add.l A0,A0 2005 2005 add.l #_prstab,A0 2006 2006 move (A0),TSRCVAL(A6) 2007 * 2008 *break;2009 * 2007 2008 | break; 2009 2010 2010 bra F03L114 2011 * 2012 *default:2013 *tsrcval = vep->val;2014 * 2011 2012 | default: 2013 | tsrcval = vep->val; 2014 2015 2015 F03L122: move.l VEP(A6),A0 2016 2016 move 8(A0),TSRCVAL(A6) 2017 * 2018 *}2019 * 2020 .page 2021 * 2022 *srcval = addpch(tsrcval, 0);2023 * 2017 2018 | } 2019 2020 .page 2021 2022 | srcval = addpch(tsrcval, 0); 2023 2024 2024 F03L114: move.w TSRCVAL(A6),D0 2025 2025 ext.l D0 2026 2026 asr.l #5,D0 2027 *sub.l #500,D02027 | sub.l #500,D0 2028 2028 asl.l #LSPCH,D0 2029 2029 cmp.l #PITCHMAX,D0 2030 2030 ble F03L129A 2031 * 2031 2032 2032 move.l #PITCHMAX,D0 2033 2033 2034 2034 F03L129A: move D0,SRCVAL(A6) 2035 * 2036 .page 2037 * 2038 *if (pt->ipvsrc) {2039 * 2035 2036 .page 2037 2038 | if (pt->ipvsrc) { 2039 2040 2040 F03L124: move.l PT(A6),A0 2041 2041 tst.b 6(A0) 2042 2042 beq F03L136 2043 * 2044 *switch (pt->ipvsrc) {2045 * 2043 2044 | switch (pt->ipvsrc) { 2045 2046 2046 move.l PT(A6),A0 2047 2047 move.b 6(A0),D0 … … 2050 2050 cmp #9,D0 2051 2051 bhi F03L144 2052 * 2052 2053 2053 asl #2,D0 2054 2054 lea F03L145,A0 2055 2055 move.l 0(A0,D0.W),A0 2056 2056 jmp (A0) 2057 * 2058 *case SM_RAND:2059 *ltmp = xgetran(pt_>ipvmlt);2060 * 2057 2058 | case SM_RAND: 2059 | ltmp = xgetran(pt_>ipvmlt); 2060 2061 2061 F03L139: move.l PT(A6),A0 2062 2062 move 4(A0),(sp) … … 2064 2064 ext.l D0 2065 2065 move.l D0,LTMP(A6) 2066 * 2067 *break;2068 * 2066 2067 | break; 2068 2069 2069 bra F03L137 2070 * 2071 *case SM_PTCH:2072 *ltmp = pch;2073 * 2070 2071 | case SM_PTCH: 2072 | ltmp = pch; 2073 2074 2074 F03L140: move PCH(A6),A0 2075 2075 move.l A0,LTMP(A6) 2076 * 2077 *break;2078 * 2076 2077 | break; 2078 2079 2079 bra F03L137 2080 * 2081 .page 2082 * 2083 *case SM_FREQ:2084 *ltmp = ptoftab[(pch >> 7) & 0x00FF];2085 * 2080 2081 .page 2082 2083 | case SM_FREQ: 2084 | ltmp = ptoftab[(pch >> 7) & 0x00FF]; 2085 2086 2086 F03L141: move PCH(A6),D0 2087 2087 asr #7,D0 … … 2093 2093 ext.l D0 2094 2094 move.l D0,LTMP(A6) 2095 * 2096 *break;2097 * 2095 2096 | break; 2097 2098 2098 bra F03L137 2099 * 2100 *case SM_KVEL:2101 *ltmp = veltab[trg];2102 * 2099 2100 | case SM_KVEL: 2101 | ltmp = veltab[trg]; 2102 2103 2103 F03L142: move TRG(A6),A0 2104 2104 add.l A0,A0 … … 2107 2107 ext.l D0 2108 2108 move.l D0,LTMP(A6) 2109 * 2110 *break;2111 * 2109 2110 | break; 2111 2112 2112 bra F03L137 2113 * 2114 .page 2115 * 2116 *case SM_KPRS:2117 *ltmp = prstab[trg];2118 * 2113 2114 .page 2115 2116 | case SM_KPRS: 2117 | ltmp = prstab[trg]; 2118 2119 2119 F03L143: move TRG(A6),A0 2120 2120 add.l A0,A0 … … 2123 2123 ext.l D0 2124 2124 move.l D0,LTMP(A6) 2125 * 2126 *break;2127 * 2125 2126 | break; 2127 2128 2128 bra F03L137 2129 * 2130 .page 2131 * 2132 *default:2133 *ltmp = valents[group | pt->ipvsrc].val;2134 * 2129 2130 .page 2131 2132 | default: 2133 | ltmp = valents[group | pt->ipvsrc].val; 2134 2135 2135 F03L144: move.l PT(A6),A0 2136 2136 clr.l D0 … … 2146 2146 move 8(A0,A1.l),D0 2147 2147 move.l D0,LTMP(A6) 2148 * 2149 *}2150 * 2151 * 2152 .page 2153 * 2154 * ltmp = (ltmp *pt->ipvmlt) >> 15;2155 * 2148 2149 | } 2150 2151 2152 .page 2153 2154 | ltmp = (ltmp | pt->ipvmlt) >> 15; 2155 2156 2156 F03L137: move.l PT(A6),A0 2157 2157 move.w 4(A0),D0 … … 2161 2161 asr.l D1,D0 2162 2162 move.l D0,LTMP(A6) 2163 * 2164 *ltmp += (long)pt->ipval;2165 * 2163 2164 | ltmp += (long)pt->ipval; 2165 2166 2166 move.l PT(A6),A0 2167 2167 move 2(A0),D0 2168 2168 ext.l D0 2169 2169 add.l D0,LTMP(A6) 2170 * 2171 *if (ltmp GT (long)VALMAX)2172 *ltmp = (long)VALMAX;2173 * 2170 2171 | if (ltmp GT (long)VALMAX) 2172 | ltmp = (long)VALMAX; 2173 2174 2174 cmp.l #VALMAX,LTMP(A6) 2175 2175 ble F03L146 2176 * 2176 2177 2177 move.l #VALMAX,LTMP(A6) 2178 2178 bra F03L147 2179 * 2180 *else if (ltmp LT (long)VALMIN)2181 *ltmp = (long)VALMIN;2182 * 2179 2180 | else if (ltmp LT (long)VALMIN) 2181 | ltmp = (long)VALMIN; 2182 2183 2183 F03L146: cmp.l #VALMIN,LTMP(A6) 2184 2184 bge F03L147 2185 * 2185