[a06aa8b] | 1 | /*
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| 2 | * Copyright (C) 2017 The Contributors
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| 3 | *
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| 4 | * This program is free software: you can redistribute it and/or modify
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| 5 | * it under the terms of the GNU General Public License as published by
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| 6 | * the Free Software Foundation, either version 3 of the License, or (at
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| 7 | * your option) any later version.
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| 8 | *
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| 9 | * This program is distributed in the hope that it will be useful, but
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| 10 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 12 | * General Public License for more details.
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| 13 | *
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| 14 | * A copy of the GNU General Public License can be found in the file
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[2147e53] | 15 | * "gpl.txt" in the top directory of this repository.
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[a06aa8b] | 16 | */
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| 17 |
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[ff8d800] | 18 | #include <all.h>
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| 19 |
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[4c71d39] | 20 | #define ver(...) _ver(cpu_verbose, 0, __VA_ARGS__)
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| 21 | #define ver2(...) _ver(cpu_verbose, 1, __VA_ARGS__)
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| 22 | #define ver3(...) _ver(cpu_verbose, 2, __VA_ARGS__)
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[ff8d800] | 23 |
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[4c71d39] | 24 | int32_t cpu_verbose = 0;
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[a06aa8b] | 25 |
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[0d83ce8] | 26 | #define MIDAS_ABS "midas.abs"
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| 27 |
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[ebc8f69] | 28 | #define CPU_FREQ 7000000
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| 29 | #define PER_SEC 100000
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[ff8d800] | 30 |
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[555b171] | 31 | #define APP_START 0x10000
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[ba36b71] | 32 |
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[a06aa8b] | 33 | #define RAM_START 0x0
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| 34 | #define RAM_SIZE 0x100000
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| 35 |
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| 36 | #define ROM_START 0x100000
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| 37 | #define ROM_SIZE 0x10000
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| 38 |
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| 39 | typedef void (*hw_init_t)(void);
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| 40 | typedef void (*hw_quit_t)(void);
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[3c30832] | 41 | typedef bool (*hw_exec_t)(void);
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[a06aa8b] | 42 | typedef uint32_t (*hw_read_t)(uint32_t off, int32_t sz);
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| 43 | typedef void (*hw_write_t)(uint32_t off, int32_t sz, uint32_t val);
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| 44 |
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| 45 | typedef struct {
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| 46 | uint32_t addr_beg;
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| 47 | uint32_t addr_end;
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[3c30832] | 48 | uint32_t irq;
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[a06aa8b] | 49 | hw_init_t init;
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| 50 | hw_quit_t quit;
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| 51 | hw_exec_t exec;
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| 52 | hw_read_t read;
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| 53 | hw_write_t write;
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| 54 | } hw_t;
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[ff8d800] | 55 |
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[0d83ce8] | 56 | typedef struct {
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| 57 | uint32_t text_loc;
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| 58 | uint32_t text_len;
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| 59 | uint32_t data_loc;
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| 60 | uint32_t data_len;
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| 61 | uint32_t bss_loc;
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| 62 | uint32_t bss_len;
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| 63 | size_t load_len;
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| 64 | SDL_RWops *ops;
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| 65 | } abs_t;
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| 66 |
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[bdd5a63] | 67 | static uint64_t freq;
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| 68 | static uint64_t quan;
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| 69 |
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| 70 | SDL_mutex *cpu_mutex;
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| 71 |
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[ff8d800] | 72 | static bool reset = true;
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| 73 |
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[a06aa8b] | 74 | static uint8_t ram_data[RAM_SIZE];
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| 75 | static uint8_t rom_data[ROM_SIZE];
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| 76 |
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[ba36b71] | 77 | static uint32_t ram_ro_beg = 0x1234;
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| 78 | static uint32_t ram_ro_end = 0x1234;
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| 79 | static uint32_t ram_rw_beg = 0x1234;
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| 80 | static uint32_t ram_rw_end = 0x1234;
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[a06aa8b] | 81 |
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[ba36b71] | 82 | static uint32_t rom_ro_beg;
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| 83 | static uint32_t rom_ro_end;
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| 84 | static uint32_t rom_rw_beg;
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| 85 | static uint32_t rom_rw_end;
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[a06aa8b] | 86 |
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| 87 | static hw_t hw_map[] = {
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[3c30832] | 88 | { 0x180000, 0x200000, 0, fpu_init, fpu_quit, fpu_exec, fpu_read, fpu_write },
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[ac4e192] | 89 | { 0x200000, 0x280002, 1, vid_init, vid_quit, vid_exec, vid_read, vid_write },
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[212bc4c] | 90 | { 0x3a0001, 0x3a4001, 4, tim_init, tim_quit, tim_exec, tim_read, tim_write },
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[3c30832] | 91 | { 0x3a4001, 0x3a8001, 0, lcd_init, lcd_quit, lcd_exec, lcd_read, lcd_write },
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| 92 | { 0x3a8001, 0x3ac001, 5, ser_init, ser_quit, ser_exec, ser_read, ser_write },
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[0529a19] | 93 | { 0x3ac001, 0x3b0001, 5, mid_init, mid_quit, mid_exec, mid_read, mid_write },
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[3c30832] | 94 | { 0x3b0001, 0x3b4001, 0, fdd_init, fdd_quit, fdd_exec, fdd_read, fdd_write },
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| 95 | { 0x3b4001, 0x3b8001, 0, snd_init, snd_quit, snd_exec, snd_read, snd_write },
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| 96 | { 0x3b8001, 0x3bc001, 0, led_init, led_quit, led_exec, led_read, led_write },
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[4ed9bfe] | 97 | { 0x3bc001, 0x3c0001, 3, kbd_init, kbd_quit, kbd_exec, kbd_read, kbd_write }
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[a06aa8b] | 98 | };
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| 99 |
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| 100 | static hw_t *hw_by_addr(uint32_t addr)
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| 101 | {
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| 102 | for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
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| 103 | if (addr >= hw_map[i].addr_beg && addr < hw_map[i].addr_end) {
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| 104 | return hw_map + i;
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| 105 | }
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| 106 | }
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| 107 |
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| 108 | return NULL;
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| 109 | }
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| 110 |
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| 111 | static void hw_init(void)
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| 112 | {
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[bb4fd0c] | 113 | inf("starting hardware");
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[b909777] | 114 |
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[a06aa8b] | 115 | for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
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| 116 | hw_map[i].init();
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| 117 | }
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| 118 | }
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| 119 |
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[bb4fd0c] | 120 | static void hw_quit(void)
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| 121 | {
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| 122 | inf("halting hardware");
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| 123 |
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| 124 | for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
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| 125 | hw_map[i].quit();
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| 126 | }
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| 127 | }
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| 128 |
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[3c30832] | 129 | static uint32_t hw_exec(void)
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[a06aa8b] | 130 | {
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[3c30832] | 131 | uint32_t irq = 0;
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| 132 |
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[a06aa8b] | 133 | for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
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[3c30832] | 134 | if (hw_map[i].exec() && hw_map[i].irq > irq) {
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| 135 | irq = hw_map[i].irq;
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| 136 | }
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[a06aa8b] | 137 | }
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[3c30832] | 138 |
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| 139 | return irq;
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[a06aa8b] | 140 | }
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| 141 |
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| 142 | static uint32_t hw_off(hw_t *hw, uint32_t addr)
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| 143 | {
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| 144 | if ((hw->addr_beg & 0x1) == 0) {
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| 145 | return addr - hw->addr_beg;
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| 146 | }
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| 147 |
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| 148 | return (addr - hw->addr_beg) / 2;
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| 149 | }
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| 150 |
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[0d83ce8] | 151 | static void open_abs(const char *path, abs_t *abs)
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[b909777] | 152 | {
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[0d83ce8] | 153 | abs->ops = SDL_RWFromFile(path, "rb");
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[b909777] | 154 |
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[0d83ce8] | 155 | if (abs->ops == NULL) {
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| 156 | fail("error while opening .abs file %s", path);
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[b909777] | 157 | }
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| 158 |
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[0d83ce8] | 159 | if (SDL_ReadBE16(abs->ops) != 0x601b) {
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| 160 | fail("invalid .abs file %s", path);
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[b909777] | 161 | }
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| 162 |
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[0d83ce8] | 163 | abs->text_len = SDL_ReadBE32(abs->ops);
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| 164 | abs->data_len = SDL_ReadBE32(abs->ops);
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| 165 | abs->bss_len = SDL_ReadBE32(abs->ops);
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[b909777] | 166 |
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[0d83ce8] | 167 | SDL_ReadBE32(abs->ops);
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| 168 | SDL_ReadBE32(abs->ops);
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[b909777] | 169 |
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[0d83ce8] | 170 | abs->text_loc = SDL_ReadBE32(abs->ops);
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[b909777] | 171 |
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[0d83ce8] | 172 | SDL_ReadBE16(abs->ops);
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[b909777] | 173 |
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[0d83ce8] | 174 | abs->data_loc = SDL_ReadBE32(abs->ops);
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| 175 | abs->bss_loc = SDL_ReadBE32(abs->ops);
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[b909777] | 176 |
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[0d83ce8] | 177 | inf("text 0x%x:0x%x data 0x%x:0x%x bss 0x%x:0x%x",
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| 178 | abs->text_loc, abs->text_len, abs->data_loc, abs->data_len, abs->bss_loc, abs->bss_len);
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[b909777] | 179 |
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[0d83ce8] | 180 | abs->load_len = (size_t)SDL_RWsize(abs->ops) - 36;
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| 181 | }
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[b909777] | 182 |
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[0d83ce8] | 183 | static void load_abs(const char *path, abs_t *abs, uint8_t *data)
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| 184 | {
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[b909777] | 185 | size_t loaded = 0;
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| 186 |
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[0d83ce8] | 187 | while (loaded < abs->load_len) {
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| 188 | size_t n_rd = SDL_RWread(abs->ops, data + loaded, 1, abs->load_len - loaded);
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[b909777] | 189 |
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| 190 | if (n_rd == 0) {
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[0d83ce8] | 191 | fail("error while reading .abs file %s", path);
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[b909777] | 192 | }
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| 193 |
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| 194 | loaded += n_rd;
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| 195 | }
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| 196 |
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[0d83ce8] | 197 | SDL_RWclose(abs->ops);
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| 198 | }
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[ba36b71] | 199 |
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[0d83ce8] | 200 | static void bios_init(void)
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| 201 | {
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| 202 | inf("loading BIOS file %s", bios);
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| 203 |
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| 204 | abs_t abs;
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| 205 | open_abs(bios, &abs);
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| 206 |
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| 207 | if (abs.text_loc != ROM_START || abs.text_loc + abs.text_len != abs.data_loc ||
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| 208 | abs.load_len != abs.text_len + abs.data_len || abs.load_len > ROM_SIZE) {
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| 209 | fail("invalid BIOS file %s", bios);
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| 210 | }
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| 211 |
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| 212 | load_abs(bios, &abs, rom_data);
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| 213 |
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| 214 | rom_ro_beg = abs.text_loc;
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| 215 | rom_ro_end = abs.text_loc + abs.text_len + abs.data_len;
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| 216 | rom_rw_beg = abs.bss_loc;
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| 217 | rom_rw_end = abs.bss_loc + abs.bss_len;
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[ba36b71] | 218 |
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| 219 | ver("rom_ro_beg 0x%08x rom_ro_end 0x%08x", rom_ro_beg, rom_ro_end);
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| 220 | ver("rom_rw_beg 0x%08x rom_rw_end 0x%08x", rom_rw_beg, rom_rw_end);
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[b909777] | 221 | }
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| 222 |
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[0d83ce8] | 223 | static void midas_init(void)
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| 224 | {
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| 225 | SDL_RWops *ops = SDL_RWFromFile(MIDAS_ABS, "rb");
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| 226 |
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| 227 | if (ops == NULL) {
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| 228 | return;
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| 229 | }
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| 230 |
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| 231 | SDL_RWclose(ops);
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| 232 |
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| 233 | inf("loading MIDAS file " MIDAS_ABS);
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| 234 |
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| 235 | abs_t abs;
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| 236 | open_abs(MIDAS_ABS, &abs);
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| 237 |
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| 238 | if (abs.text_loc != APP_START ||
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| 239 | abs.text_loc + abs.text_len != abs.data_loc ||
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| 240 | abs.data_loc + abs.data_len != abs.bss_loc ||
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| 241 | abs.load_len != abs.text_len + abs.data_len ||
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| 242 | abs.bss_loc + abs.bss_len > RAM_SIZE) {
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| 243 | fail("invalid MIDAS file " MIDAS_ABS);
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| 244 | }
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| 245 |
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| 246 | load_abs(MIDAS_ABS, &abs, ram_data + APP_START - RAM_START);
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| 247 |
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| 248 | ram_ro_beg = ram_rw_beg = APP_START;
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| 249 | ram_ro_end = ram_rw_end = RAM_START + RAM_SIZE;
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| 250 | }
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| 251 |
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[ff8d800] | 252 | uint32_t m68k_read_disassembler_8(uint32_t addr)
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| 253 | {
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[a06aa8b] | 254 | return m68k_read_memory_8(addr);
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[ff8d800] | 255 | }
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| 256 |
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| 257 | uint32_t m68k_read_disassembler_16(uint32_t addr)
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| 258 | {
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[a06aa8b] | 259 | return m68k_read_memory_16(addr);
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[ff8d800] | 260 | }
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| 261 |
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| 262 | uint32_t m68k_read_disassembler_32(uint32_t addr)
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| 263 | {
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[a06aa8b] | 264 | return m68k_read_memory_32(addr);
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[ff8d800] | 265 | }
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| 266 |
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| 267 | uint32_t m68k_read_memory_8(uint32_t addr)
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| 268 | {
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[4c71d39] | 269 | ver3("mem rd 0x%08x:8", addr);
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[a06aa8b] | 270 |
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[ba36b71] | 271 | if (addr >= ram_ro_beg && addr <= ram_ro_end - 1) {
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| 272 | return ram_data[addr - RAM_START];
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| 273 | }
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| 274 |
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| 275 | if (addr >= ram_rw_beg && addr <= ram_rw_end - 1) {
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[a06aa8b] | 276 | return ram_data[addr - RAM_START];
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| 277 | }
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| 278 |
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[ba36b71] | 279 | if (addr >= rom_ro_beg && addr <= rom_ro_end - 1) {
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[a06aa8b] | 280 | return rom_data[addr - ROM_START];
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| 281 | }
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| 282 |
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[ba36b71] | 283 | if (addr >= rom_rw_beg && addr <= rom_rw_end - 1) {
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| 284 | // ROM has its BSS section in RAM.
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| 285 | return ram_data[addr - RAM_START];
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| 286 | }
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| 287 |
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[a06aa8b] | 288 | hw_t *hw = hw_by_addr(addr);
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| 289 |
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| 290 | if (hw != NULL) {
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| 291 | return hw->read(hw_off(hw, addr), 1);
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| 292 | }
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| 293 |
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[555b171] | 294 | if (addr <= APP_START - 1) {
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[ba36b71] | 295 | return ram_data[addr];
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| 296 | }
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| 297 |
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[a06aa8b] | 298 | fail("invalid read 0x%08x:8", addr);
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[ff8d800] | 299 | }
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| 300 |
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| 301 | uint32_t m68k_read_memory_16(uint32_t addr)
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| 302 | {
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[4c71d39] | 303 | ver3("mem rd 0x%08x:16", addr);
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[ff8d800] | 304 |
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[ba36b71] | 305 | if (addr >= ram_ro_beg && addr <= ram_ro_end - 2) {
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| 306 | return
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| 307 | ((uint32_t)ram_data[addr - RAM_START + 0] << 8) |
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| 308 | ((uint32_t)ram_data[addr - RAM_START + 1] << 0);
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| 309 | }
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| 310 |
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| 311 | if (addr >= ram_rw_beg && addr <= ram_rw_end - 2) {
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[a06aa8b] | 312 | return
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| 313 | ((uint32_t)ram_data[addr - RAM_START + 0] << 8) |
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| 314 | ((uint32_t)ram_data[addr - RAM_START + 1] << 0);
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| 315 | }
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| 316 |
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[ba36b71] | 317 | if (addr >= rom_ro_beg && addr <= rom_ro_end - 2) {
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[a06aa8b] | 318 | return
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| 319 | ((uint32_t)rom_data[addr - ROM_START + 0] << 8) |
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| 320 | ((uint32_t)rom_data[addr - ROM_START + 1] << 0);
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[ff8d800] | 321 | }
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| 322 |
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[ba36b71] | 323 | if (addr >= rom_rw_beg && addr <= rom_rw_end - 2) {
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| 324 | // ROM has its BSS section in RAM.
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| 325 | return
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| 326 | ((uint32_t)ram_data[addr - RAM_START + 0] << 8) |
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| 327 | ((uint32_t)ram_data[addr - RAM_START + 1] << 0);
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| 328 | }
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| 329 |
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[a06aa8b] | 330 | hw_t *hw = hw_by_addr(addr);
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| 331 |
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| 332 | if (hw != NULL) {
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| 333 | return hw->read(hw_off(hw, addr), 2);
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[ff8d800] | 334 | }
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| 335 |
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[555b171] | 336 | if (addr <= APP_START - 2) {
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[ba36b71] | 337 | return
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[9674f1a] | 338 | ((uint32_t)ram_data[addr + 0] << 8) |
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| 339 | ((uint32_t)ram_data[addr + 1] << 0);
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[ba36b71] | 340 | }
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| 341 |
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[a06aa8b] | 342 | fail("invalid read 0x%08x:16", addr);
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[ff8d800] | 343 | }
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| 344 |
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| 345 | uint32_t m68k_read_memory_32(uint32_t addr)
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| 346 | {
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[4c71d39] | 347 | ver3("mem rd 0x%08x:32", addr);
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[ff8d800] | 348 |
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| 349 | if (reset) {
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| 350 | if (addr == 0) {
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[b909777] | 351 | addr += ROM_START;
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[ff8d800] | 352 | }
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[b909777] | 353 | else if (addr == 4) {
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| 354 | addr += ROM_START;
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[ff8d800] | 355 | reset = false;
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| 356 | }
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[b909777] | 357 | else {
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| 358 | fail("invalid reset sequence");
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| 359 | }
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[ff8d800] | 360 | }
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| 361 |
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[ba36b71] | 362 | if (addr >= ram_ro_beg && addr <= ram_ro_end - 4) {
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[a06aa8b] | 363 | return
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| 364 | ((uint32_t)ram_data[addr - RAM_START + 0] << 24) |
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| 365 | ((uint32_t)ram_data[addr - RAM_START + 1] << 16) |
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| 366 | ((uint32_t)ram_data[addr - RAM_START + 2] << 8) |
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| 367 | ((uint32_t)ram_data[addr - RAM_START + 3] << 0);
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| 368 | }
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| 369 |
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[ba36b71] | 370 | if (addr >= ram_rw_beg && addr <= ram_rw_end - 4) {
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| 371 | return
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| 372 | ((uint32_t)ram_data[addr - RAM_START + 0] << 24) |
|
---|
| 373 | ((uint32_t)ram_data[addr - RAM_START + 1] << 16) |
|
---|
| 374 | ((uint32_t)ram_data[addr - RAM_START + 2] << 8) |
|
---|
| 375 | ((uint32_t)ram_data[addr - RAM_START + 3] << 0);
|
---|
| 376 | }
|
---|
| 377 |
|
---|
| 378 | if (addr >= rom_ro_beg && addr <= rom_ro_end - 4) {
|
---|
[a06aa8b] | 379 | return
|
---|
| 380 | ((uint32_t)rom_data[addr - ROM_START + 0] << 24) |
|
---|
| 381 | ((uint32_t)rom_data[addr - ROM_START + 1] << 16) |
|
---|
| 382 | ((uint32_t)rom_data[addr - ROM_START + 2] << 8) |
|
---|
| 383 | ((uint32_t)rom_data[addr - ROM_START + 3] << 0);
|
---|
| 384 | }
|
---|
| 385 |
|
---|
[ba36b71] | 386 | if (addr >= rom_rw_beg && addr <= rom_rw_end - 4) {
|
---|
| 387 | // ROM has its BSS section in RAM.
|
---|
| 388 | return
|
---|
| 389 | ((uint32_t)ram_data[addr - RAM_START + 0] << 24) |
|
---|
| 390 | ((uint32_t)ram_data[addr - RAM_START + 1] << 16) |
|
---|
| 391 | ((uint32_t)ram_data[addr - RAM_START + 2] << 8) |
|
---|
| 392 | ((uint32_t)ram_data[addr - RAM_START + 3] << 0);
|
---|
| 393 | }
|
---|
| 394 |
|
---|
[a06aa8b] | 395 | hw_t *hw = hw_by_addr(addr);
|
---|
| 396 |
|
---|
| 397 | if (hw != NULL) {
|
---|
| 398 | return hw->read(hw_off(hw, addr), 4);
|
---|
| 399 | }
|
---|
| 400 |
|
---|
[555b171] | 401 | if (addr <= APP_START - 4) {
|
---|
[ba36b71] | 402 | return
|
---|
| 403 | ((uint32_t)ram_data[addr + 0] << 24) |
|
---|
| 404 | ((uint32_t)ram_data[addr + 1] << 16) |
|
---|
| 405 | ((uint32_t)ram_data[addr + 2] << 8) |
|
---|
| 406 | ((uint32_t)ram_data[addr + 3] << 0);
|
---|
| 407 | }
|
---|
| 408 |
|
---|
[a06aa8b] | 409 | fail("invalid read 0x%08x:32", addr);
|
---|
[ff8d800] | 410 | }
|
---|
| 411 |
|
---|
| 412 | void m68k_write_memory_8(uint32_t addr, uint32_t val)
|
---|
| 413 | {
|
---|
[4c71d39] | 414 | ver3("mem wr 0x%08x:8 0x%02x", addr, val);
|
---|
[a06aa8b] | 415 |
|
---|
[ba36b71] | 416 | if (addr >= ram_rw_beg && addr <= ram_rw_end - 1) {
|
---|
[a06aa8b] | 417 | ram_data[addr - RAM_START] = (uint8_t)val;
|
---|
| 418 | return;
|
---|
| 419 | }
|
---|
| 420 |
|
---|
[ba36b71] | 421 | if (addr >= rom_rw_beg && addr <= rom_rw_end - 1) {
|
---|
[a06aa8b] | 422 | // ROM has its BSS section in RAM.
|
---|
| 423 | ram_data[addr - RAM_START] = (uint8_t)val;
|
---|
| 424 | return;
|
---|
| 425 | }
|
---|
| 426 |
|
---|
| 427 | hw_t *hw = hw_by_addr(addr);
|
---|
| 428 |
|
---|
| 429 | if (hw != NULL) {
|
---|
| 430 | hw->write(hw_off(hw, addr), 1, val);
|
---|
| 431 | return;
|
---|
| 432 | }
|
---|
| 433 |
|
---|
[555b171] | 434 | if (addr <= APP_START - 1) {
|
---|
[ba36b71] | 435 | ram_data[addr] = (uint8_t)val;
|
---|
| 436 | return;
|
---|
| 437 | }
|
---|
| 438 |
|
---|
[74c44d9] | 439 | // once midas.abs gets loaded, activate RAM
|
---|
[c5b6c90] | 440 |
|
---|
| 441 | if (addr == APP_START) {
|
---|
[74c44d9] | 442 | ram_data[addr] = (uint8_t)val;
|
---|
[c5b6c90] | 443 | ram_rw_beg = APP_START;
|
---|
| 444 | ram_rw_end = RAM_START + RAM_SIZE;
|
---|
| 445 | return;
|
---|
| 446 | }
|
---|
| 447 |
|
---|
[a06aa8b] | 448 | fail("invalid write 0x%08x:8 0x%02x", addr, val);
|
---|
[ff8d800] | 449 | }
|
---|
| 450 |
|
---|
| 451 | void m68k_write_memory_16(uint32_t addr, uint32_t val)
|
---|
| 452 | {
|
---|
[4c71d39] | 453 | ver3("mem wr 0x%08x:16 0x%04x", addr, val);
|
---|
[a06aa8b] | 454 |
|
---|
[ba36b71] | 455 | if (addr >= ram_rw_beg && addr <= ram_rw_end - 2) {
|
---|
[a06aa8b] | 456 | ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 8);
|
---|
| 457 | ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 0);
|
---|
| 458 | return;
|
---|
| 459 | }
|
---|
| 460 |
|
---|
[ba36b71] | 461 | if (addr >= rom_rw_beg && addr <= rom_rw_end - 2) {
|
---|
[a06aa8b] | 462 | // ROM has its BSS section in RAM.
|
---|
| 463 | ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 8);
|
---|
| 464 | ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 0);
|
---|
| 465 | return;
|
---|
| 466 | }
|
---|
| 467 |
|
---|
| 468 | hw_t *hw = hw_by_addr(addr);
|
---|
| 469 |
|
---|
| 470 | if (hw != NULL) {
|
---|
| 471 | hw->write(hw_off(hw, addr), 2, val);
|
---|
| 472 | return;
|
---|
| 473 | }
|
---|
| 474 |
|
---|
[555b171] | 475 | if (addr <= APP_START - 2) {
|
---|
[ba36b71] | 476 | ram_data[addr + 0] = (uint8_t)(val >> 8);
|
---|
| 477 | ram_data[addr + 1] = (uint8_t)(val >> 0);
|
---|
| 478 | return;
|
---|
| 479 | }
|
---|
| 480 |
|
---|
[a06aa8b] | 481 | fail("invalid write 0x%08x:16 0x%04x", addr, val);
|
---|
[ff8d800] | 482 | }
|
---|
| 483 |
|
---|
| 484 | void m68k_write_memory_32(uint32_t addr, uint32_t val)
|
---|
| 485 | {
|
---|
[4c71d39] | 486 | ver3("mem wr 0x%08x:32 0x%08x", addr, val);
|
---|
[a06aa8b] | 487 |
|
---|
[ba36b71] | 488 | if (addr >= ram_rw_beg && addr <= ram_rw_end - 4) {
|
---|
[a06aa8b] | 489 | ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 24);
|
---|
| 490 | ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 16);
|
---|
| 491 | ram_data[addr - RAM_START + 2] = (uint8_t)(val >> 8);
|
---|
| 492 | ram_data[addr - RAM_START + 3] = (uint8_t)(val >> 0);
|
---|
| 493 | return;
|
---|
| 494 | }
|
---|
| 495 |
|
---|
[ba36b71] | 496 | if (addr >= rom_rw_beg && addr <= rom_rw_end - 4) {
|
---|
[a06aa8b] | 497 | // ROM has its BSS section in RAM.
|
---|
| 498 | ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 24);
|
---|
| 499 | ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 16);
|
---|
| 500 | ram_data[addr - RAM_START + 2] = (uint8_t)(val >> 8);
|
---|
| 501 | ram_data[addr - RAM_START + 3] = (uint8_t)(val >> 0);
|
---|
| 502 | return;
|
---|
| 503 | }
|
---|
| 504 |
|
---|
| 505 | hw_t *hw = hw_by_addr(addr);
|
---|
| 506 |
|
---|
| 507 | if (hw != NULL) {
|
---|
| 508 | hw->write(hw_off(hw, addr), 4, val);
|
---|
| 509 | return;
|
---|
| 510 | }
|
---|
| 511 |
|
---|
[555b171] | 512 | if (addr <= APP_START - 4) {
|
---|
[ba36b71] | 513 | ram_data[addr + 0] = (uint8_t)(val >> 24);
|
---|
| 514 | ram_data[addr + 1] = (uint8_t)(val >> 16);
|
---|
| 515 | ram_data[addr + 2] = (uint8_t)(val >> 8);
|
---|
| 516 | ram_data[addr + 3] = (uint8_t)(val >> 0);
|
---|
| 517 | return;
|
---|
| 518 | }
|
---|
| 519 |
|
---|
[a06aa8b] | 520 | fail("invalid write 0x%08x:32 0x%08x", addr, val);
|
---|
[ff8d800] | 521 | }
|
---|
| 522 |
|
---|
[5fa5369] | 523 | uint8_t cpu_peek(int32_t addr)
|
---|
| 524 | {
|
---|
| 525 | if (addr >= RAM_START && addr <= RAM_START + RAM_SIZE - 1) {
|
---|
| 526 | return ram_data[addr - RAM_START];
|
---|
| 527 | }
|
---|
| 528 |
|
---|
| 529 | if (addr >= ROM_START && addr <= ROM_START + ROM_SIZE - 1) {
|
---|
| 530 | return rom_data[addr - ROM_START];
|
---|
| 531 | }
|
---|
| 532 |
|
---|
| 533 | return 0;
|
---|
| 534 | }
|
---|
| 535 |
|
---|
| 536 | void cpu_poke(int32_t addr, uint8_t val)
|
---|
| 537 | {
|
---|
| 538 | if (addr >= RAM_START && addr <= RAM_START + RAM_SIZE - 1) {
|
---|
| 539 | ram_data[addr - RAM_START] = val;
|
---|
| 540 | }
|
---|
| 541 |
|
---|
| 542 | if (addr >= ROM_START && addr <= ROM_START + ROM_SIZE - 1) {
|
---|
| 543 | rom_data[addr - ROM_START] = val;
|
---|
| 544 | }
|
---|
| 545 | }
|
---|
| 546 |
|
---|
[9674f1a] | 547 | static void inst_cb(void)
|
---|
| 548 | {
|
---|
| 549 | uint32_t pc = m68k_get_reg(NULL, M68K_REG_PC);
|
---|
| 550 | uint32_t op = m68k_read_memory_16(pc);
|
---|
| 551 |
|
---|
[149c3e0] | 552 | gdb_inst(op == 0x4e4f);
|
---|
| 553 |
|
---|
[9674f1a] | 554 | if (op == 0x4e4d) {
|
---|
| 555 | uint32_t sp = m68k_get_reg(NULL, M68K_REG_SP);
|
---|
| 556 | uint32_t fun = m68k_read_memory_16(sp);
|
---|
| 557 |
|
---|
| 558 | switch (fun) {
|
---|
| 559 | case 1:
|
---|
| 560 | ver2("BIOS B_RDAV %u", m68k_read_memory_16(sp + 2));
|
---|
| 561 | break;
|
---|
| 562 |
|
---|
| 563 | case 2:
|
---|
| 564 | ver2("BIOS B_GETC %u", m68k_read_memory_16(sp + 2));
|
---|
| 565 | break;
|
---|
| 566 |
|
---|
| 567 | case 3:
|
---|
| 568 | ver2("BIOS B_PUTC %u %u",
|
---|
| 569 | m68k_read_memory_16(sp + 2),
|
---|
| 570 | m68k_read_memory_16(sp + 4));
|
---|
| 571 | break;
|
---|
| 572 |
|
---|
| 573 | case 4:
|
---|
| 574 | ver2("BIOS B_RDWR %u 0x%08x %u %u %u",
|
---|
| 575 | m68k_read_memory_16(sp + 2),
|
---|
| 576 | m68k_read_memory_32(sp + 4),
|
---|
| 577 | m68k_read_memory_16(sp + 8),
|
---|
| 578 | m68k_read_memory_16(sp + 10),
|
---|
| 579 | m68k_read_memory_16(sp + 12));
|
---|
| 580 | break;
|
---|
| 581 |
|
---|
| 582 | case 5:
|
---|
| 583 | ver2("BIOS B_SETV %u 0x%08x",
|
---|
| 584 | m68k_read_memory_16(sp + 2),
|
---|
| 585 | m68k_read_memory_32(sp + 4));
|
---|
| 586 | break;
|
---|
| 587 |
|
---|
| 588 | case 7:
|
---|
| 589 | ver2("BIOS B_GBPB %u", m68k_read_memory_16(sp + 2));
|
---|
| 590 | break;
|
---|
| 591 |
|
---|
| 592 | case 8:
|
---|
| 593 | ver2("BIOS B_THRE %u", m68k_read_memory_16(sp + 2));
|
---|
| 594 | break;
|
---|
| 595 |
|
---|
| 596 | case 9:
|
---|
| 597 | ver2("BIOS B_MCHG %u", m68k_read_memory_16(sp + 2));
|
---|
| 598 | break;
|
---|
| 599 |
|
---|
| 600 | case 10:
|
---|
| 601 | ver2("BIOS B_DMAP");
|
---|
| 602 | break;
|
---|
| 603 |
|
---|
| 604 | default:
|
---|
| 605 | fail("invalid function: BIOS %d", fun);
|
---|
| 606 | }
|
---|
| 607 | }
|
---|
| 608 | else if (op == 0x4e4e) {
|
---|
| 609 | uint32_t sp = m68k_get_reg(NULL, M68K_REG_SP);
|
---|
| 610 | uint32_t fun = m68k_read_memory_16(sp);
|
---|
| 611 |
|
---|
| 612 | switch (fun) {
|
---|
| 613 | case 0:
|
---|
| 614 | ver2("XBIOS X_PIOREC %u", m68k_read_memory_16(sp + 2));
|
---|
| 615 | break;
|
---|
| 616 |
|
---|
| 617 | case 1:
|
---|
| 618 | ver2("XBIOS X_SETPRT %u 0x%02x 0x%02x 0x%02x 0x%02x",
|
---|
| 619 | m68k_read_memory_16(sp + 2),
|
---|
| 620 | m68k_read_memory_16(sp + 4),
|
---|
| 621 | m68k_read_memory_16(sp + 6),
|
---|
| 622 | m68k_read_memory_16(sp + 8),
|
---|
| 623 | m68k_read_memory_16(sp + 10));
|
---|
| 624 | break;
|
---|
| 625 |
|
---|
| 626 | case 2:
|
---|
| 627 | ver2("XBIOS X_FLOPRD 0x%08x 0x%08x %u %u %u %u %u",
|
---|
| 628 | m68k_read_memory_32(sp + 2),
|
---|
| 629 | m68k_read_memory_32(sp + 6),
|
---|
| 630 | m68k_read_memory_16(sp + 10),
|
---|
| 631 | m68k_read_memory_16(sp + 12),
|
---|
| 632 | m68k_read_memory_16(sp + 14),
|
---|
| 633 | m68k_read_memory_16(sp + 16),
|
---|
| 634 | m68k_read_memory_16(sp + 18));
|
---|
| 635 | break;
|
---|
| 636 |
|
---|
| 637 | case 3:
|
---|
| 638 | ver2("XBIOS X_FLOPWR 0x%08x 0x%08x %u %u %u %u %u",
|
---|
| 639 | m68k_read_memory_32(sp + 2),
|
---|
| 640 | m68k_read_memory_32(sp + 6),
|
---|
| 641 | m68k_read_memory_16(sp + 10),
|
---|
| 642 | m68k_read_memory_16(sp + 12),
|
---|
| 643 | m68k_read_memory_16(sp + 14),
|
---|
| 644 | m68k_read_memory_16(sp + 16),
|
---|
| 645 | m68k_read_memory_16(sp + 18));
|
---|
| 646 | break;
|
---|
| 647 |
|
---|
| 648 | case 4:
|
---|
| 649 | ver2("XBIOS X_FORMAT 0x%08x 0x%08x %u %u %u %u %u 0x%08x %u",
|
---|
| 650 | m68k_read_memory_32(sp + 2),
|
---|
| 651 | m68k_read_memory_32(sp + 6),
|
---|
| 652 | m68k_read_memory_16(sp + 10),
|
---|
| 653 | m68k_read_memory_16(sp + 12),
|
---|
| 654 | m68k_read_memory_16(sp + 14),
|
---|
| 655 | m68k_read_memory_16(sp + 16),
|
---|
| 656 | m68k_read_memory_16(sp + 18),
|
---|
| 657 | m68k_read_memory_32(sp + 20),
|
---|
| 658 | m68k_read_memory_16(sp + 24));
|
---|
| 659 | break;
|
---|
| 660 |
|
---|
| 661 | case 5:
|
---|
| 662 | ver2("XBIOS X_VERIFY 0x%08x 0x%08x %u %u %u %u %u",
|
---|
| 663 | m68k_read_memory_32(sp + 2),
|
---|
| 664 | m68k_read_memory_32(sp + 6),
|
---|
| 665 | m68k_read_memory_16(sp + 10),
|
---|
| 666 | m68k_read_memory_16(sp + 12),
|
---|
| 667 | m68k_read_memory_16(sp + 14),
|
---|
| 668 | m68k_read_memory_16(sp + 16),
|
---|
| 669 | m68k_read_memory_16(sp + 18));
|
---|
| 670 | break;
|
---|
| 671 |
|
---|
| 672 | case 6:
|
---|
| 673 | ver2("XBIOS X_PRBOOT 0x%08x %u %u %u",
|
---|
| 674 | m68k_read_memory_32(sp + 2),
|
---|
| 675 | m68k_read_memory_16(sp + 6),
|
---|
| 676 | m68k_read_memory_16(sp + 8),
|
---|
| 677 | m68k_read_memory_16(sp + 10));
|
---|
| 678 | break;
|
---|
| 679 |
|
---|
| 680 | case 7:
|
---|
| 681 | ver2("XBIOS X_RANDOM");
|
---|
| 682 | break;
|
---|
| 683 |
|
---|
| 684 | case 8:
|
---|
| 685 | ver2("XBIOS X_ANALOG");
|
---|
| 686 | break;
|
---|
| 687 |
|
---|
| 688 | case 9:
|
---|
| 689 | ver2("XBIOS X_CLRAFI");
|
---|
| 690 | break;
|
---|
| 691 |
|
---|
| 692 | case 10:
|
---|
| 693 | ver2("XBIOS X_APICHK");
|
---|
| 694 | break;
|
---|
| 695 |
|
---|
| 696 | case 11:
|
---|
| 697 | ver2("XBIOS X_MTDEFS ");
|
---|
| 698 | break;
|
---|
| 699 |
|
---|
| 700 | default:
|
---|
| 701 | fail("invalid function: XBIOS %d", fun);
|
---|
| 702 | }
|
---|
| 703 | }
|
---|
| 704 | }
|
---|
| 705 |
|
---|
[bdd5a63] | 706 | void cpu_init(void)
|
---|
[ff8d800] | 707 | {
|
---|
[bdd5a63] | 708 | cpu_mutex = SDL_CreateMutex();
|
---|
| 709 |
|
---|
| 710 | if (cpu_mutex == NULL) {
|
---|
| 711 | fail("SDL_CreateMutex() failed: %s", SDL_GetError());
|
---|
| 712 | }
|
---|
| 713 |
|
---|
| 714 | freq = SDL_GetPerformanceFrequency();
|
---|
| 715 | quan = freq / PER_SEC;
|
---|
| 716 |
|
---|
| 717 | inf("freq %" PRIu64 " quan %" PRIu64, freq, quan);
|
---|
| 718 |
|
---|
[a06aa8b] | 719 | hw_init();
|
---|
[1efc42c] | 720 | bios_init();
|
---|
[0d83ce8] | 721 | midas_init();
|
---|
[ff8d800] | 722 |
|
---|
| 723 | m68k_init();
|
---|
| 724 | m68k_set_cpu_type(M68K_CPU_TYPE_68000);
|
---|
[9674f1a] | 725 | m68k_set_instr_hook_callback(inst_cb);
|
---|
[ff8d800] | 726 | m68k_pulse_reset();
|
---|
[bdd5a63] | 727 | }
|
---|
[ff8d800] | 728 |
|
---|
[bdd5a63] | 729 | void cpu_quit(void)
|
---|
| 730 | {
|
---|
| 731 | hw_quit();
|
---|
| 732 | SDL_DestroyMutex(cpu_mutex);
|
---|
| 733 | }
|
---|
[7eb8971] | 734 |
|
---|
[bdd5a63] | 735 | void cpu_loop(void)
|
---|
| 736 | {
|
---|
| 737 | inf("entering CPU loop");
|
---|
[6e313dd] | 738 | int32_t count = 0;
|
---|
[e41c6b6] | 739 |
|
---|
[bdd5a63] | 740 | while (SDL_AtomicGet(&run) != 0) {
|
---|
[ebc8f69] | 741 | uint64_t until = SDL_GetPerformanceCounter() + quan;
|
---|
| 742 |
|
---|
[bdd5a63] | 743 | if (SDL_LockMutex(cpu_mutex) < 0) {
|
---|
| 744 | fail("SDL_LockMutex() failed: %s", SDL_GetError());
|
---|
| 745 | }
|
---|
| 746 |
|
---|
[ebc8f69] | 747 | m68k_execute(CPU_FREQ / PER_SEC);
|
---|
[3c30832] | 748 | uint32_t irq = hw_exec();
|
---|
| 749 |
|
---|
| 750 | if (irq > 0) {
|
---|
| 751 | ver2("irq %u", irq);
|
---|
| 752 | }
|
---|
| 753 |
|
---|
| 754 | m68k_set_irq(irq);
|
---|
[e41c6b6] | 755 |
|
---|
[bdd5a63] | 756 | if (SDL_UnlockMutex(cpu_mutex) < 0) {
|
---|
| 757 | fail("SDL_UnlockMutex() failed: %s", SDL_GetError());
|
---|
[e41c6b6] | 758 | }
|
---|
[ebc8f69] | 759 |
|
---|
[6e313dd] | 760 | if ((++count & 0x1ff) == 0) {
|
---|
| 761 | SDL_Delay(0);
|
---|
| 762 | }
|
---|
| 763 |
|
---|
[ebc8f69] | 764 | while (SDL_GetPerformanceCounter() < until) {
|
---|
[6e313dd] | 765 | for (int32_t i = 0; i < 100; ++i) {
|
---|
| 766 | _mm_pause();
|
---|
| 767 | }
|
---|
[ebc8f69] | 768 | }
|
---|
[ff8d800] | 769 | }
|
---|
[e41c6b6] | 770 |
|
---|
| 771 | inf("leaving CPU loop");
|
---|
[ff8d800] | 772 | }
|
---|