[a06aa8b] | 1 | /*
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| 2 | * Copyright (C) 2017 The Contributors
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| 3 | *
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| 4 | * This program is free software: you can redistribute it and/or modify
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| 5 | * it under the terms of the GNU General Public License as published by
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| 6 | * the Free Software Foundation, either version 3 of the License, or (at
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| 7 | * your option) any later version.
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| 8 | *
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| 9 | * This program is distributed in the hope that it will be useful, but
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| 10 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 12 | * General Public License for more details.
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| 13 | *
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| 14 | * A copy of the GNU General Public License can be found in the file
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[2147e53] | 15 | * "gpl.txt" in the top directory of this repository.
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[a06aa8b] | 16 | */
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| 17 |
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[ff8d800] | 18 | #include <all.h>
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| 19 |
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[4c71d39] | 20 | #define ver(...) _ver(cpu_verbose, 0, __VA_ARGS__)
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| 21 | #define ver2(...) _ver(cpu_verbose, 1, __VA_ARGS__)
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| 22 | #define ver3(...) _ver(cpu_verbose, 2, __VA_ARGS__)
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[ff8d800] | 23 |
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[4c71d39] | 24 | int32_t cpu_verbose = 0;
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[a06aa8b] | 25 |
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[ebc8f69] | 26 | #define CPU_FREQ 7000000
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| 27 | #define PER_SEC 100000
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[ff8d800] | 28 |
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[555b171] | 29 | #define APP_START 0x10000
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[ba36b71] | 30 |
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[a06aa8b] | 31 | #define RAM_START 0x0
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| 32 | #define RAM_SIZE 0x100000
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| 33 |
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| 34 | #define ROM_START 0x100000
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| 35 | #define ROM_SIZE 0x10000
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| 36 |
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| 37 | typedef void (*hw_init_t)(void);
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| 38 | typedef void (*hw_quit_t)(void);
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[3c30832] | 39 | typedef bool (*hw_exec_t)(void);
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[a06aa8b] | 40 | typedef uint32_t (*hw_read_t)(uint32_t off, int32_t sz);
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| 41 | typedef void (*hw_write_t)(uint32_t off, int32_t sz, uint32_t val);
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| 42 |
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| 43 | typedef struct {
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| 44 | uint32_t addr_beg;
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| 45 | uint32_t addr_end;
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[3c30832] | 46 | uint32_t irq;
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[a06aa8b] | 47 | hw_init_t init;
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| 48 | hw_quit_t quit;
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| 49 | hw_exec_t exec;
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| 50 | hw_read_t read;
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| 51 | hw_write_t write;
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| 52 | } hw_t;
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[ff8d800] | 53 |
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[bdd5a63] | 54 | static uint64_t freq;
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| 55 | static uint64_t quan;
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| 56 |
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| 57 | SDL_mutex *cpu_mutex;
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| 58 |
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[ff8d800] | 59 | static bool reset = true;
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| 60 |
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[a06aa8b] | 61 | static uint8_t ram_data[RAM_SIZE];
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| 62 | static uint8_t rom_data[ROM_SIZE];
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| 63 |
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[ba36b71] | 64 | static uint32_t ram_ro_beg = 0x1234;
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| 65 | static uint32_t ram_ro_end = 0x1234;
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| 66 | static uint32_t ram_rw_beg = 0x1234;
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| 67 | static uint32_t ram_rw_end = 0x1234;
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[a06aa8b] | 68 |
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[ba36b71] | 69 | static uint32_t rom_ro_beg;
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| 70 | static uint32_t rom_ro_end;
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| 71 | static uint32_t rom_rw_beg;
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| 72 | static uint32_t rom_rw_end;
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[a06aa8b] | 73 |
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| 74 | static hw_t hw_map[] = {
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[3c30832] | 75 | { 0x180000, 0x200000, 0, fpu_init, fpu_quit, fpu_exec, fpu_read, fpu_write },
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[ac4e192] | 76 | { 0x200000, 0x280002, 1, vid_init, vid_quit, vid_exec, vid_read, vid_write },
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[212bc4c] | 77 | { 0x3a0001, 0x3a4001, 4, tim_init, tim_quit, tim_exec, tim_read, tim_write },
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[3c30832] | 78 | { 0x3a4001, 0x3a8001, 0, lcd_init, lcd_quit, lcd_exec, lcd_read, lcd_write },
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| 79 | { 0x3a8001, 0x3ac001, 5, ser_init, ser_quit, ser_exec, ser_read, ser_write },
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| 80 | { 0x3ac001, 0x3b0001, 0, mid_init, mid_quit, mid_exec, mid_read, mid_write },
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| 81 | { 0x3b0001, 0x3b4001, 0, fdd_init, fdd_quit, fdd_exec, fdd_read, fdd_write },
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| 82 | { 0x3b4001, 0x3b8001, 0, snd_init, snd_quit, snd_exec, snd_read, snd_write },
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| 83 | { 0x3b8001, 0x3bc001, 0, led_init, led_quit, led_exec, led_read, led_write },
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| 84 | { 0x3bc001, 0x3c0001, 0, kbd_init, kbd_quit, kbd_exec, kbd_read, kbd_write }
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[a06aa8b] | 85 | };
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| 86 |
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| 87 | static hw_t *hw_by_addr(uint32_t addr)
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| 88 | {
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| 89 | for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
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| 90 | if (addr >= hw_map[i].addr_beg && addr < hw_map[i].addr_end) {
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| 91 | return hw_map + i;
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| 92 | }
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| 93 | }
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| 94 |
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| 95 | return NULL;
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| 96 | }
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| 97 |
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| 98 | static void hw_init(void)
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| 99 | {
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[bb4fd0c] | 100 | inf("starting hardware");
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[b909777] | 101 |
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[a06aa8b] | 102 | for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
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| 103 | hw_map[i].init();
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| 104 | }
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| 105 | }
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| 106 |
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[bb4fd0c] | 107 | static void hw_quit(void)
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| 108 | {
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| 109 | inf("halting hardware");
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| 110 |
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| 111 | for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
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| 112 | hw_map[i].quit();
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| 113 | }
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| 114 | }
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| 115 |
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[3c30832] | 116 | static uint32_t hw_exec(void)
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[a06aa8b] | 117 | {
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[3c30832] | 118 | uint32_t irq = 0;
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| 119 |
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[a06aa8b] | 120 | for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
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[3c30832] | 121 | if (hw_map[i].exec() && hw_map[i].irq > irq) {
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| 122 | irq = hw_map[i].irq;
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| 123 | }
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[a06aa8b] | 124 | }
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[3c30832] | 125 |
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| 126 | return irq;
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[a06aa8b] | 127 | }
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| 128 |
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| 129 | static uint32_t hw_off(hw_t *hw, uint32_t addr)
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| 130 | {
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| 131 | if ((hw->addr_beg & 0x1) == 0) {
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| 132 | return addr - hw->addr_beg;
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| 133 | }
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| 134 |
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| 135 | return (addr - hw->addr_beg) / 2;
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| 136 | }
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| 137 |
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[1efc42c] | 138 | static void bios_init(void)
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[b909777] | 139 | {
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[ba36b71] | 140 | inf("loading BIOS file %s", bios);
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[b909777] | 141 |
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| 142 | SDL_RWops *ops = SDL_RWFromFile(bios, "rb");
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| 143 |
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| 144 | if (ops == NULL) {
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| 145 | fail("error while opening BIOS file %s", bios);
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| 146 | }
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| 147 |
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| 148 | if (SDL_ReadBE16(ops) != 0x601b) {
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| 149 | fail("invalid BIOS file %s", bios);
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| 150 | }
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| 151 |
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| 152 | uint32_t text_len = SDL_ReadBE32(ops);
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| 153 | uint32_t data_len = SDL_ReadBE32(ops);
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| 154 | uint32_t bss_len = SDL_ReadBE32(ops);
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| 155 |
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| 156 | SDL_ReadBE32(ops);
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| 157 | SDL_ReadBE32(ops);
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| 158 |
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| 159 | uint32_t text_loc = SDL_ReadBE32(ops);
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| 160 |
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| 161 | SDL_ReadBE16(ops);
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| 162 |
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| 163 | uint32_t data_loc = SDL_ReadBE32(ops);
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| 164 | uint32_t bss_loc = SDL_ReadBE32(ops);
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| 165 |
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[ba36b71] | 166 | inf("BIOS text 0x%x:0x%x data 0x%x:0x%x bss 0x%x:0x%x",
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| 167 | text_loc, text_len, data_loc, data_len, bss_loc, bss_len);
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[b909777] | 168 |
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| 169 | size_t load_len = (size_t)SDL_RWsize(ops) - 36;
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| 170 |
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[ba36b71] | 171 | if (text_loc != ROM_START || text_loc + text_len != data_loc ||
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| 172 | load_len != text_len + data_len || load_len > ROM_SIZE) {
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| 173 | fail("invalid BIOS file %s", bios);
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[b909777] | 174 | }
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| 175 |
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| 176 | size_t loaded = 0;
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| 177 |
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| 178 | while (loaded < load_len) {
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| 179 | size_t n_rd = SDL_RWread(ops, rom_data + loaded, 1, load_len - loaded);
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| 180 |
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| 181 | if (n_rd == 0) {
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| 182 | fail("error while reading BIOS file %s", bios);
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| 183 | }
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| 184 |
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| 185 | loaded += n_rd;
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| 186 | }
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| 187 |
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| 188 | SDL_RWclose(ops);
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[ba36b71] | 189 |
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| 190 | rom_ro_beg = text_loc;
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| 191 | rom_ro_end = text_loc + text_len + data_len;
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| 192 | rom_rw_beg = bss_loc;
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| 193 | rom_rw_end = bss_loc + bss_len;
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| 194 |
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| 195 | ver("rom_ro_beg 0x%08x rom_ro_end 0x%08x", rom_ro_beg, rom_ro_end);
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| 196 | ver("rom_rw_beg 0x%08x rom_rw_end 0x%08x", rom_rw_beg, rom_rw_end);
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[b909777] | 197 | }
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| 198 |
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[ff8d800] | 199 | uint32_t m68k_read_disassembler_8(uint32_t addr)
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| 200 | {
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[a06aa8b] | 201 | return m68k_read_memory_8(addr);
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[ff8d800] | 202 | }
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| 203 |
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| 204 | uint32_t m68k_read_disassembler_16(uint32_t addr)
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| 205 | {
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[a06aa8b] | 206 | return m68k_read_memory_16(addr);
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[ff8d800] | 207 | }
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| 208 |
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| 209 | uint32_t m68k_read_disassembler_32(uint32_t addr)
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| 210 | {
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[a06aa8b] | 211 | return m68k_read_memory_32(addr);
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[ff8d800] | 212 | }
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| 213 |
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| 214 | uint32_t m68k_read_memory_8(uint32_t addr)
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| 215 | {
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[4c71d39] | 216 | ver3("mem rd 0x%08x:8", addr);
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[a06aa8b] | 217 |
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[ba36b71] | 218 | if (addr >= ram_ro_beg && addr <= ram_ro_end - 1) {
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| 219 | return ram_data[addr - RAM_START];
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| 220 | }
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| 221 |
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| 222 | if (addr >= ram_rw_beg && addr <= ram_rw_end - 1) {
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[a06aa8b] | 223 | return ram_data[addr - RAM_START];
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| 224 | }
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| 225 |
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[ba36b71] | 226 | if (addr >= rom_ro_beg && addr <= rom_ro_end - 1) {
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[a06aa8b] | 227 | return rom_data[addr - ROM_START];
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| 228 | }
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| 229 |
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[ba36b71] | 230 | if (addr >= rom_rw_beg && addr <= rom_rw_end - 1) {
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| 231 | // ROM has its BSS section in RAM.
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| 232 | return ram_data[addr - RAM_START];
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| 233 | }
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| 234 |
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[a06aa8b] | 235 | hw_t *hw = hw_by_addr(addr);
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| 236 |
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| 237 | if (hw != NULL) {
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| 238 | return hw->read(hw_off(hw, addr), 1);
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| 239 | }
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| 240 |
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[555b171] | 241 | if (addr <= APP_START - 1) {
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[ba36b71] | 242 | return ram_data[addr];
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| 243 | }
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| 244 |
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[a06aa8b] | 245 | fail("invalid read 0x%08x:8", addr);
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[ff8d800] | 246 | }
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| 247 |
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| 248 | uint32_t m68k_read_memory_16(uint32_t addr)
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| 249 | {
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[4c71d39] | 250 | ver3("mem rd 0x%08x:16", addr);
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[ff8d800] | 251 |
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[ba36b71] | 252 | if (addr >= ram_ro_beg && addr <= ram_ro_end - 2) {
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| 253 | return
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| 254 | ((uint32_t)ram_data[addr - RAM_START + 0] << 8) |
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| 255 | ((uint32_t)ram_data[addr - RAM_START + 1] << 0);
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| 256 | }
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| 257 |
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| 258 | if (addr >= ram_rw_beg && addr <= ram_rw_end - 2) {
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[a06aa8b] | 259 | return
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| 260 | ((uint32_t)ram_data[addr - RAM_START + 0] << 8) |
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| 261 | ((uint32_t)ram_data[addr - RAM_START + 1] << 0);
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| 262 | }
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| 263 |
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[ba36b71] | 264 | if (addr >= rom_ro_beg && addr <= rom_ro_end - 2) {
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[a06aa8b] | 265 | return
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| 266 | ((uint32_t)rom_data[addr - ROM_START + 0] << 8) |
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| 267 | ((uint32_t)rom_data[addr - ROM_START + 1] << 0);
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[ff8d800] | 268 | }
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| 269 |
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[ba36b71] | 270 | if (addr >= rom_rw_beg && addr <= rom_rw_end - 2) {
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| 271 | // ROM has its BSS section in RAM.
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| 272 | return
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| 273 | ((uint32_t)ram_data[addr - RAM_START + 0] << 8) |
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| 274 | ((uint32_t)ram_data[addr - RAM_START + 1] << 0);
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| 275 | }
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| 276 |
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[a06aa8b] | 277 | hw_t *hw = hw_by_addr(addr);
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| 278 |
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| 279 | if (hw != NULL) {
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| 280 | return hw->read(hw_off(hw, addr), 2);
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[ff8d800] | 281 | }
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| 282 |
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[555b171] | 283 | if (addr <= APP_START - 2) {
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[ba36b71] | 284 | return
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[9674f1a] | 285 | ((uint32_t)ram_data[addr + 0] << 8) |
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| 286 | ((uint32_t)ram_data[addr + 1] << 0);
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[ba36b71] | 287 | }
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| 288 |
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[a06aa8b] | 289 | fail("invalid read 0x%08x:16", addr);
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[ff8d800] | 290 | }
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| 291 |
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| 292 | uint32_t m68k_read_memory_32(uint32_t addr)
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| 293 | {
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[4c71d39] | 294 | ver3("mem rd 0x%08x:32", addr);
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[ff8d800] | 295 |
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| 296 | if (reset) {
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| 297 | if (addr == 0) {
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[b909777] | 298 | addr += ROM_START;
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[ff8d800] | 299 | }
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[b909777] | 300 | else if (addr == 4) {
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| 301 | addr += ROM_START;
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[ff8d800] | 302 | reset = false;
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| 303 | }
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[b909777] | 304 | else {
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| 305 | fail("invalid reset sequence");
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| 306 | }
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[ff8d800] | 307 | }
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| 308 |
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[ba36b71] | 309 | if (addr >= ram_ro_beg && addr <= ram_ro_end - 4) {
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[a06aa8b] | 310 | return
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| 311 | ((uint32_t)ram_data[addr - RAM_START + 0] << 24) |
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| 312 | ((uint32_t)ram_data[addr - RAM_START + 1] << 16) |
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| 313 | ((uint32_t)ram_data[addr - RAM_START + 2] << 8) |
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| 314 | ((uint32_t)ram_data[addr - RAM_START + 3] << 0);
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| 315 | }
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| 316 |
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[ba36b71] | 317 | if (addr >= ram_rw_beg && addr <= ram_rw_end - 4) {
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| 318 | return
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| 319 | ((uint32_t)ram_data[addr - RAM_START + 0] << 24) |
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| 320 | ((uint32_t)ram_data[addr - RAM_START + 1] << 16) |
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| 321 | ((uint32_t)ram_data[addr - RAM_START + 2] << 8) |
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| 322 | ((uint32_t)ram_data[addr - RAM_START + 3] << 0);
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| 323 | }
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| 324 |
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| 325 | if (addr >= rom_ro_beg && addr <= rom_ro_end - 4) {
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[a06aa8b] | 326 | return
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| 327 | ((uint32_t)rom_data[addr - ROM_START + 0] << 24) |
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| 328 | ((uint32_t)rom_data[addr - ROM_START + 1] << 16) |
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| 329 | ((uint32_t)rom_data[addr - ROM_START + 2] << 8) |
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| 330 | ((uint32_t)rom_data[addr - ROM_START + 3] << 0);
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| 331 | }
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| 332 |
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[ba36b71] | 333 | if (addr >= rom_rw_beg && addr <= rom_rw_end - 4) {
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| 334 | // ROM has its BSS section in RAM.
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| 335 | return
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| 336 | ((uint32_t)ram_data[addr - RAM_START + 0] << 24) |
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| 337 | ((uint32_t)ram_data[addr - RAM_START + 1] << 16) |
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| 338 | ((uint32_t)ram_data[addr - RAM_START + 2] << 8) |
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| 339 | ((uint32_t)ram_data[addr - RAM_START + 3] << 0);
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| 340 | }
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| 341 |
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[a06aa8b] | 342 | hw_t *hw = hw_by_addr(addr);
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| 343 |
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| 344 | if (hw != NULL) {
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| 345 | return hw->read(hw_off(hw, addr), 4);
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| 346 | }
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| 347 |
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[555b171] | 348 | if (addr <= APP_START - 4) {
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[ba36b71] | 349 | return
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| 350 | ((uint32_t)ram_data[addr + 0] << 24) |
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| 351 | ((uint32_t)ram_data[addr + 1] << 16) |
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| 352 | ((uint32_t)ram_data[addr + 2] << 8) |
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| 353 | ((uint32_t)ram_data[addr + 3] << 0);
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| 354 | }
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| 355 |
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[a06aa8b] | 356 | fail("invalid read 0x%08x:32", addr);
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[ff8d800] | 357 | }
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| 358 |
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| 359 | void m68k_write_memory_8(uint32_t addr, uint32_t val)
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| 360 | {
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[4c71d39] | 361 | ver3("mem wr 0x%08x:8 0x%02x", addr, val);
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[a06aa8b] | 362 |
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[ba36b71] | 363 | if (addr >= ram_rw_beg && addr <= ram_rw_end - 1) {
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[a06aa8b] | 364 | ram_data[addr - RAM_START] = (uint8_t)val;
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| 365 | return;
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| 366 | }
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| 367 |
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[ba36b71] | 368 | if (addr >= rom_rw_beg && addr <= rom_rw_end - 1) {
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[a06aa8b] | 369 | // ROM has its BSS section in RAM.
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| 370 | ram_data[addr - RAM_START] = (uint8_t)val;
|
---|
| 371 | return;
|
---|
| 372 | }
|
---|
| 373 |
|
---|
| 374 | hw_t *hw = hw_by_addr(addr);
|
---|
| 375 |
|
---|
| 376 | if (hw != NULL) {
|
---|
| 377 | hw->write(hw_off(hw, addr), 1, val);
|
---|
| 378 | return;
|
---|
| 379 | }
|
---|
| 380 |
|
---|
[555b171] | 381 | if (addr <= APP_START - 1) {
|
---|
[ba36b71] | 382 | ram_data[addr] = (uint8_t)val;
|
---|
| 383 | return;
|
---|
| 384 | }
|
---|
| 385 |
|
---|
[74c44d9] | 386 | // once midas.abs gets loaded, activate RAM
|
---|
[c5b6c90] | 387 |
|
---|
| 388 | if (addr == APP_START) {
|
---|
[74c44d9] | 389 | ram_data[addr] = (uint8_t)val;
|
---|
[c5b6c90] | 390 | ram_rw_beg = APP_START;
|
---|
| 391 | ram_rw_end = RAM_START + RAM_SIZE;
|
---|
| 392 | return;
|
---|
| 393 | }
|
---|
| 394 |
|
---|
[a06aa8b] | 395 | fail("invalid write 0x%08x:8 0x%02x", addr, val);
|
---|
[ff8d800] | 396 | }
|
---|
| 397 |
|
---|
| 398 | void m68k_write_memory_16(uint32_t addr, uint32_t val)
|
---|
| 399 | {
|
---|
[4c71d39] | 400 | ver3("mem wr 0x%08x:16 0x%04x", addr, val);
|
---|
[a06aa8b] | 401 |
|
---|
[ba36b71] | 402 | if (addr >= ram_rw_beg && addr <= ram_rw_end - 2) {
|
---|
[a06aa8b] | 403 | ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 8);
|
---|
| 404 | ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 0);
|
---|
| 405 | return;
|
---|
| 406 | }
|
---|
| 407 |
|
---|
[ba36b71] | 408 | if (addr >= rom_rw_beg && addr <= rom_rw_end - 2) {
|
---|
[a06aa8b] | 409 | // ROM has its BSS section in RAM.
|
---|
| 410 | ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 8);
|
---|
| 411 | ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 0);
|
---|
| 412 | return;
|
---|
| 413 | }
|
---|
| 414 |
|
---|
| 415 | hw_t *hw = hw_by_addr(addr);
|
---|
| 416 |
|
---|
| 417 | if (hw != NULL) {
|
---|
| 418 | hw->write(hw_off(hw, addr), 2, val);
|
---|
| 419 | return;
|
---|
| 420 | }
|
---|
| 421 |
|
---|
[555b171] | 422 | if (addr <= APP_START - 2) {
|
---|
[ba36b71] | 423 | ram_data[addr + 0] = (uint8_t)(val >> 8);
|
---|
| 424 | ram_data[addr + 1] = (uint8_t)(val >> 0);
|
---|
| 425 | return;
|
---|
| 426 | }
|
---|
| 427 |
|
---|
[a06aa8b] | 428 | fail("invalid write 0x%08x:16 0x%04x", addr, val);
|
---|
[ff8d800] | 429 | }
|
---|
| 430 |
|
---|
| 431 | void m68k_write_memory_32(uint32_t addr, uint32_t val)
|
---|
| 432 | {
|
---|
[4c71d39] | 433 | ver3("mem wr 0x%08x:32 0x%08x", addr, val);
|
---|
[a06aa8b] | 434 |
|
---|
[ba36b71] | 435 | if (addr >= ram_rw_beg && addr <= ram_rw_end - 4) {
|
---|
[a06aa8b] | 436 | ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 24);
|
---|
| 437 | ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 16);
|
---|
| 438 | ram_data[addr - RAM_START + 2] = (uint8_t)(val >> 8);
|
---|
| 439 | ram_data[addr - RAM_START + 3] = (uint8_t)(val >> 0);
|
---|
| 440 | return;
|
---|
| 441 | }
|
---|
| 442 |
|
---|
[ba36b71] | 443 | if (addr >= rom_rw_beg && addr <= rom_rw_end - 4) {
|
---|
[a06aa8b] | 444 | // ROM has its BSS section in RAM.
|
---|
| 445 | ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 24);
|
---|
| 446 | ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 16);
|
---|
| 447 | ram_data[addr - RAM_START + 2] = (uint8_t)(val >> 8);
|
---|
| 448 | ram_data[addr - RAM_START + 3] = (uint8_t)(val >> 0);
|
---|
| 449 | return;
|
---|
| 450 | }
|
---|
| 451 |
|
---|
| 452 | hw_t *hw = hw_by_addr(addr);
|
---|
| 453 |
|
---|
| 454 | if (hw != NULL) {
|
---|
| 455 | hw->write(hw_off(hw, addr), 4, val);
|
---|
| 456 | return;
|
---|
| 457 | }
|
---|
| 458 |
|
---|
[555b171] | 459 | if (addr <= APP_START - 4) {
|
---|
[ba36b71] | 460 | ram_data[addr + 0] = (uint8_t)(val >> 24);
|
---|
| 461 | ram_data[addr + 1] = (uint8_t)(val >> 16);
|
---|
| 462 | ram_data[addr + 2] = (uint8_t)(val >> 8);
|
---|
| 463 | ram_data[addr + 3] = (uint8_t)(val >> 0);
|
---|
| 464 | return;
|
---|
| 465 | }
|
---|
| 466 |
|
---|
[a06aa8b] | 467 | fail("invalid write 0x%08x:32 0x%08x", addr, val);
|
---|
[ff8d800] | 468 | }
|
---|
| 469 |
|
---|
[5fa5369] | 470 | uint8_t cpu_peek(int32_t addr)
|
---|
| 471 | {
|
---|
| 472 | if (addr >= RAM_START && addr <= RAM_START + RAM_SIZE - 1) {
|
---|
| 473 | return ram_data[addr - RAM_START];
|
---|
| 474 | }
|
---|
| 475 |
|
---|
| 476 | if (addr >= ROM_START && addr <= ROM_START + ROM_SIZE - 1) {
|
---|
| 477 | return rom_data[addr - ROM_START];
|
---|
| 478 | }
|
---|
| 479 |
|
---|
| 480 | return 0;
|
---|
| 481 | }
|
---|
| 482 |
|
---|
| 483 | void cpu_poke(int32_t addr, uint8_t val)
|
---|
| 484 | {
|
---|
| 485 | if (addr >= RAM_START && addr <= RAM_START + RAM_SIZE - 1) {
|
---|
| 486 | ram_data[addr - RAM_START] = val;
|
---|
| 487 | }
|
---|
| 488 |
|
---|
| 489 | if (addr >= ROM_START && addr <= ROM_START + ROM_SIZE - 1) {
|
---|
| 490 | rom_data[addr - ROM_START] = val;
|
---|
| 491 | }
|
---|
| 492 | }
|
---|
| 493 |
|
---|
[9674f1a] | 494 | static void inst_cb(void)
|
---|
| 495 | {
|
---|
| 496 | uint32_t pc = m68k_get_reg(NULL, M68K_REG_PC);
|
---|
| 497 | uint32_t op = m68k_read_memory_16(pc);
|
---|
| 498 |
|
---|
[149c3e0] | 499 | gdb_inst(op == 0x4e4f);
|
---|
| 500 |
|
---|
[9674f1a] | 501 | if (op == 0x4e4d) {
|
---|
| 502 | uint32_t sp = m68k_get_reg(NULL, M68K_REG_SP);
|
---|
| 503 | uint32_t fun = m68k_read_memory_16(sp);
|
---|
| 504 |
|
---|
| 505 | switch (fun) {
|
---|
| 506 | case 1:
|
---|
| 507 | ver2("BIOS B_RDAV %u", m68k_read_memory_16(sp + 2));
|
---|
| 508 | break;
|
---|
| 509 |
|
---|
| 510 | case 2:
|
---|
| 511 | ver2("BIOS B_GETC %u", m68k_read_memory_16(sp + 2));
|
---|
| 512 | break;
|
---|
| 513 |
|
---|
| 514 | case 3:
|
---|
| 515 | ver2("BIOS B_PUTC %u %u",
|
---|
| 516 | m68k_read_memory_16(sp + 2),
|
---|
| 517 | m68k_read_memory_16(sp + 4));
|
---|
| 518 | break;
|
---|
| 519 |
|
---|
| 520 | case 4:
|
---|
| 521 | ver2("BIOS B_RDWR %u 0x%08x %u %u %u",
|
---|
| 522 | m68k_read_memory_16(sp + 2),
|
---|
| 523 | m68k_read_memory_32(sp + 4),
|
---|
| 524 | m68k_read_memory_16(sp + 8),
|
---|
| 525 | m68k_read_memory_16(sp + 10),
|
---|
| 526 | m68k_read_memory_16(sp + 12));
|
---|
| 527 | break;
|
---|
| 528 |
|
---|
| 529 | case 5:
|
---|
| 530 | ver2("BIOS B_SETV %u 0x%08x",
|
---|
| 531 | m68k_read_memory_16(sp + 2),
|
---|
| 532 | m68k_read_memory_32(sp + 4));
|
---|
| 533 | break;
|
---|
| 534 |
|
---|
| 535 | case 7:
|
---|
| 536 | ver2("BIOS B_GBPB %u", m68k_read_memory_16(sp + 2));
|
---|
| 537 | break;
|
---|
| 538 |
|
---|
| 539 | case 8:
|
---|
| 540 | ver2("BIOS B_THRE %u", m68k_read_memory_16(sp + 2));
|
---|
| 541 | break;
|
---|
| 542 |
|
---|
| 543 | case 9:
|
---|
| 544 | ver2("BIOS B_MCHG %u", m68k_read_memory_16(sp + 2));
|
---|
| 545 | break;
|
---|
| 546 |
|
---|
| 547 | case 10:
|
---|
| 548 | ver2("BIOS B_DMAP");
|
---|
| 549 | break;
|
---|
| 550 |
|
---|
| 551 | default:
|
---|
| 552 | fail("invalid function: BIOS %d", fun);
|
---|
| 553 | }
|
---|
| 554 | }
|
---|
| 555 | else if (op == 0x4e4e) {
|
---|
| 556 | uint32_t sp = m68k_get_reg(NULL, M68K_REG_SP);
|
---|
| 557 | uint32_t fun = m68k_read_memory_16(sp);
|
---|
| 558 |
|
---|
| 559 | switch (fun) {
|
---|
| 560 | case 0:
|
---|
| 561 | ver2("XBIOS X_PIOREC %u", m68k_read_memory_16(sp + 2));
|
---|
| 562 | break;
|
---|
| 563 |
|
---|
| 564 | case 1:
|
---|
| 565 | ver2("XBIOS X_SETPRT %u 0x%02x 0x%02x 0x%02x 0x%02x",
|
---|
| 566 | m68k_read_memory_16(sp + 2),
|
---|
| 567 | m68k_read_memory_16(sp + 4),
|
---|
| 568 | m68k_read_memory_16(sp + 6),
|
---|
| 569 | m68k_read_memory_16(sp + 8),
|
---|
| 570 | m68k_read_memory_16(sp + 10));
|
---|
| 571 | break;
|
---|
| 572 |
|
---|
| 573 | case 2:
|
---|
| 574 | ver2("XBIOS X_FLOPRD 0x%08x 0x%08x %u %u %u %u %u",
|
---|
| 575 | m68k_read_memory_32(sp + 2),
|
---|
| 576 | m68k_read_memory_32(sp + 6),
|
---|
| 577 | m68k_read_memory_16(sp + 10),
|
---|
| 578 | m68k_read_memory_16(sp + 12),
|
---|
| 579 | m68k_read_memory_16(sp + 14),
|
---|
| 580 | m68k_read_memory_16(sp + 16),
|
---|
| 581 | m68k_read_memory_16(sp + 18));
|
---|
| 582 | break;
|
---|
| 583 |
|
---|
| 584 | case 3:
|
---|
| 585 | ver2("XBIOS X_FLOPWR 0x%08x 0x%08x %u %u %u %u %u",
|
---|
| 586 | m68k_read_memory_32(sp + 2),
|
---|
| 587 | m68k_read_memory_32(sp + 6),
|
---|
| 588 | m68k_read_memory_16(sp + 10),
|
---|
| 589 | m68k_read_memory_16(sp + 12),
|
---|
| 590 | m68k_read_memory_16(sp + 14),
|
---|
| 591 | m68k_read_memory_16(sp + 16),
|
---|
| 592 | m68k_read_memory_16(sp + 18));
|
---|
| 593 | break;
|
---|
| 594 |
|
---|
| 595 | case 4:
|
---|
| 596 | ver2("XBIOS X_FORMAT 0x%08x 0x%08x %u %u %u %u %u 0x%08x %u",
|
---|
| 597 | m68k_read_memory_32(sp + 2),
|
---|
| 598 | m68k_read_memory_32(sp + 6),
|
---|
| 599 | m68k_read_memory_16(sp + 10),
|
---|
| 600 | m68k_read_memory_16(sp + 12),
|
---|
| 601 | m68k_read_memory_16(sp + 14),
|
---|
| 602 | m68k_read_memory_16(sp + 16),
|
---|
| 603 | m68k_read_memory_16(sp + 18),
|
---|
| 604 | m68k_read_memory_32(sp + 20),
|
---|
| 605 | m68k_read_memory_16(sp + 24));
|
---|
| 606 | break;
|
---|
| 607 |
|
---|
| 608 | case 5:
|
---|
| 609 | ver2("XBIOS X_VERIFY 0x%08x 0x%08x %u %u %u %u %u",
|
---|
| 610 | m68k_read_memory_32(sp + 2),
|
---|
| 611 | m68k_read_memory_32(sp + 6),
|
---|
| 612 | m68k_read_memory_16(sp + 10),
|
---|
| 613 | m68k_read_memory_16(sp + 12),
|
---|
| 614 | m68k_read_memory_16(sp + 14),
|
---|
| 615 | m68k_read_memory_16(sp + 16),
|
---|
| 616 | m68k_read_memory_16(sp + 18));
|
---|
| 617 | break;
|
---|
| 618 |
|
---|
| 619 | case 6:
|
---|
| 620 | ver2("XBIOS X_PRBOOT 0x%08x %u %u %u",
|
---|
| 621 | m68k_read_memory_32(sp + 2),
|
---|
| 622 | m68k_read_memory_16(sp + 6),
|
---|
| 623 | m68k_read_memory_16(sp + 8),
|
---|
| 624 | m68k_read_memory_16(sp + 10));
|
---|
| 625 | break;
|
---|
| 626 |
|
---|
| 627 | case 7:
|
---|
| 628 | ver2("XBIOS X_RANDOM");
|
---|
| 629 | break;
|
---|
| 630 |
|
---|
| 631 | case 8:
|
---|
| 632 | ver2("XBIOS X_ANALOG");
|
---|
| 633 | break;
|
---|
| 634 |
|
---|
| 635 | case 9:
|
---|
| 636 | ver2("XBIOS X_CLRAFI");
|
---|
| 637 | break;
|
---|
| 638 |
|
---|
| 639 | case 10:
|
---|
| 640 | ver2("XBIOS X_APICHK");
|
---|
| 641 | break;
|
---|
| 642 |
|
---|
| 643 | case 11:
|
---|
| 644 | ver2("XBIOS X_MTDEFS ");
|
---|
| 645 | break;
|
---|
| 646 |
|
---|
| 647 | default:
|
---|
| 648 | fail("invalid function: XBIOS %d", fun);
|
---|
| 649 | }
|
---|
| 650 | }
|
---|
| 651 | }
|
---|
| 652 |
|
---|
[bdd5a63] | 653 | void cpu_init(void)
|
---|
[ff8d800] | 654 | {
|
---|
[bdd5a63] | 655 | cpu_mutex = SDL_CreateMutex();
|
---|
| 656 |
|
---|
| 657 | if (cpu_mutex == NULL) {
|
---|
| 658 | fail("SDL_CreateMutex() failed: %s", SDL_GetError());
|
---|
| 659 | }
|
---|
| 660 |
|
---|
| 661 | freq = SDL_GetPerformanceFrequency();
|
---|
| 662 | quan = freq / PER_SEC;
|
---|
| 663 |
|
---|
| 664 | inf("freq %" PRIu64 " quan %" PRIu64, freq, quan);
|
---|
| 665 |
|
---|
[a06aa8b] | 666 | hw_init();
|
---|
[1efc42c] | 667 | bios_init();
|
---|
[ff8d800] | 668 |
|
---|
| 669 | m68k_init();
|
---|
| 670 | m68k_set_cpu_type(M68K_CPU_TYPE_68000);
|
---|
[9674f1a] | 671 | m68k_set_instr_hook_callback(inst_cb);
|
---|
[ff8d800] | 672 | m68k_pulse_reset();
|
---|
[bdd5a63] | 673 | }
|
---|
[ff8d800] | 674 |
|
---|
[bdd5a63] | 675 | void cpu_quit(void)
|
---|
| 676 | {
|
---|
| 677 | hw_quit();
|
---|
| 678 | SDL_DestroyMutex(cpu_mutex);
|
---|
| 679 | }
|
---|
[7eb8971] | 680 |
|
---|
[bdd5a63] | 681 | void cpu_loop(void)
|
---|
| 682 | {
|
---|
| 683 | inf("entering CPU loop");
|
---|
[6e313dd] | 684 | int32_t count = 0;
|
---|
[e41c6b6] | 685 |
|
---|
[bdd5a63] | 686 | while (SDL_AtomicGet(&run) != 0) {
|
---|
[ebc8f69] | 687 | uint64_t until = SDL_GetPerformanceCounter() + quan;
|
---|
| 688 |
|
---|
[bdd5a63] | 689 | if (SDL_LockMutex(cpu_mutex) < 0) {
|
---|
| 690 | fail("SDL_LockMutex() failed: %s", SDL_GetError());
|
---|
| 691 | }
|
---|
| 692 |
|
---|
[ebc8f69] | 693 | m68k_execute(CPU_FREQ / PER_SEC);
|
---|
[3c30832] | 694 | uint32_t irq = hw_exec();
|
---|
| 695 |
|
---|
| 696 | if (irq > 0) {
|
---|
| 697 | ver2("irq %u", irq);
|
---|
| 698 | }
|
---|
| 699 |
|
---|
| 700 | m68k_set_irq(irq);
|
---|
[e41c6b6] | 701 |
|
---|
[bdd5a63] | 702 | if (SDL_UnlockMutex(cpu_mutex) < 0) {
|
---|
| 703 | fail("SDL_UnlockMutex() failed: %s", SDL_GetError());
|
---|
[e41c6b6] | 704 | }
|
---|
[ebc8f69] | 705 |
|
---|
[6e313dd] | 706 | if ((++count & 0x1ff) == 0) {
|
---|
| 707 | SDL_Delay(0);
|
---|
| 708 | }
|
---|
| 709 |
|
---|
[ebc8f69] | 710 | while (SDL_GetPerformanceCounter() < until) {
|
---|
[6e313dd] | 711 | for (int32_t i = 0; i < 100; ++i) {
|
---|
| 712 | _mm_pause();
|
---|
| 713 | }
|
---|
[ebc8f69] | 714 | }
|
---|
[ff8d800] | 715 | }
|
---|
[e41c6b6] | 716 |
|
---|
| 717 | inf("leaving CPU loop");
|
---|
[ff8d800] | 718 | }
|
---|