1 | /*
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2 | * Copyright (C) 2017 The Contributors
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3 | *
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4 | * This program is free software: you can redistribute it and/or modify
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5 | * it under the terms of the GNU General Public License as published by
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6 | * the Free Software Foundation, either version 3 of the License, or (at
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7 | * your option) any later version.
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8 | *
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9 | * This program is distributed in the hope that it will be useful, but
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10 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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12 | * General Public License for more details.
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13 | *
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14 | * A copy of the GNU General Public License can be found in the file
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15 | * "gpl.txt" in the top directory of this repository.
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16 | */
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17 |
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18 | #include <all.h>
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19 |
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20 | #define ver(...) _ver(cpu_verbose, 0, __VA_ARGS__)
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21 | #define ver2(...) _ver(cpu_verbose, 1, __VA_ARGS__)
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22 | #define ver3(...) _ver(cpu_verbose, 2, __VA_ARGS__)
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23 |
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24 | int32_t cpu_verbose = 0;
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25 |
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26 | #define CPU_FREQ 7000000
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27 | #define PER_SEC 100000
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28 |
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29 | #define APP_START 0x10000
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30 |
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31 | #define RAM_START 0x0
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32 | #define RAM_SIZE 0x100000
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33 |
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34 | #define ROM_START 0x100000
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35 | #define ROM_SIZE 0x10000
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36 |
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37 | typedef void (*hw_init_t)(void);
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38 | typedef void (*hw_quit_t)(void);
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39 | typedef void (*hw_exec_t)(void);
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40 | typedef uint32_t (*hw_read_t)(uint32_t off, int32_t sz);
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41 | typedef void (*hw_write_t)(uint32_t off, int32_t sz, uint32_t val);
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42 |
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43 | typedef struct {
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44 | uint32_t addr_beg;
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45 | uint32_t addr_end;
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46 | hw_init_t init;
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47 | hw_quit_t quit;
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48 | hw_exec_t exec;
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49 | hw_read_t read;
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50 | hw_write_t write;
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51 | } hw_t;
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52 |
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53 | static bool reset = true;
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54 |
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55 | static uint8_t ram_data[RAM_SIZE];
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56 | static uint8_t rom_data[ROM_SIZE];
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57 |
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58 | static uint32_t ram_ro_beg = 0x1234;
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59 | static uint32_t ram_ro_end = 0x1234;
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60 | static uint32_t ram_rw_beg = 0x1234;
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61 | static uint32_t ram_rw_end = 0x1234;
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62 |
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63 | static uint32_t rom_ro_beg;
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64 | static uint32_t rom_ro_end;
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65 | static uint32_t rom_rw_beg;
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66 | static uint32_t rom_rw_end;
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67 |
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68 | static hw_t hw_map[] = {
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69 | { 0x180000, 0x200000, fpu_init, fpu_quit, fpu_exec, fpu_read, fpu_write },
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70 | { 0x200000, 0x280000, vid_init, vid_quit, vid_exec, vid_read, vid_write },
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71 | { 0x3a0001, 0x3a4001, tim_init, tim_quit, tim_exec, tim_read, tim_write },
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72 | { 0x3a4001, 0x3a8001, lcd_init, lcd_quit, lcd_exec, lcd_read, lcd_write },
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73 | { 0x3a8001, 0x3ac001, ser_init, ser_quit, ser_exec, ser_read, ser_write },
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74 | { 0x3ac001, 0x3b0001, mid_init, mid_quit, mid_exec, mid_read, mid_write },
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75 | { 0x3b0001, 0x3b4001, fdd_init, fdd_quit, fdd_exec, fdd_read, fdd_write },
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76 | { 0x3b4001, 0x3b8001, snd_init, snd_quit, snd_exec, snd_read, snd_write },
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77 | { 0x3b8001, 0x3bc001, led_init, led_quit, led_exec, led_read, led_write },
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78 | { 0x3bc001, 0x3c0001, kbd_init, kbd_quit, kbd_exec, kbd_read, kbd_write }
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79 | };
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80 |
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81 | static hw_t *hw_by_addr(uint32_t addr)
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82 | {
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83 | for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
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84 | if (addr >= hw_map[i].addr_beg && addr < hw_map[i].addr_end) {
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85 | return hw_map + i;
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86 | }
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87 | }
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88 |
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89 | return NULL;
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90 | }
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91 |
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92 | static void hw_init(void)
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93 | {
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94 | inf("initializing hardware");
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95 |
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96 | for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
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97 | hw_map[i].init();
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98 | }
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99 | }
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100 |
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101 | static void hw_exec(void)
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102 | {
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103 | for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
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104 | hw_map[i].exec();
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105 | }
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106 | }
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107 |
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108 | static uint32_t hw_off(hw_t *hw, uint32_t addr)
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109 | {
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110 | if ((hw->addr_beg & 0x1) == 0) {
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111 | return addr - hw->addr_beg;
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112 | }
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113 |
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114 | return (addr - hw->addr_beg) / 2;
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115 | }
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116 |
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117 | static void bios_init(const char *bios)
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118 | {
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119 | inf("loading BIOS file %s", bios);
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120 |
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121 | SDL_RWops *ops = SDL_RWFromFile(bios, "rb");
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122 |
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123 | if (ops == NULL) {
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124 | fail("error while opening BIOS file %s", bios);
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125 | }
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126 |
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127 | if (SDL_ReadBE16(ops) != 0x601b) {
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128 | fail("invalid BIOS file %s", bios);
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129 | }
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130 |
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131 | uint32_t text_len = SDL_ReadBE32(ops);
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132 | uint32_t data_len = SDL_ReadBE32(ops);
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133 | uint32_t bss_len = SDL_ReadBE32(ops);
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134 |
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135 | SDL_ReadBE32(ops);
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136 | SDL_ReadBE32(ops);
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137 |
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138 | uint32_t text_loc = SDL_ReadBE32(ops);
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139 |
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140 | SDL_ReadBE16(ops);
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141 |
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142 | uint32_t data_loc = SDL_ReadBE32(ops);
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143 | uint32_t bss_loc = SDL_ReadBE32(ops);
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144 |
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145 | inf("BIOS text 0x%x:0x%x data 0x%x:0x%x bss 0x%x:0x%x",
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146 | text_loc, text_len, data_loc, data_len, bss_loc, bss_len);
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147 |
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148 | size_t load_len = (size_t)SDL_RWsize(ops) - 36;
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149 |
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150 | if (text_loc != ROM_START || text_loc + text_len != data_loc ||
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151 | load_len != text_len + data_len || load_len > ROM_SIZE) {
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152 | fail("invalid BIOS file %s", bios);
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153 | }
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154 |
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155 | size_t loaded = 0;
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156 |
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157 | while (loaded < load_len) {
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158 | size_t n_rd = SDL_RWread(ops, rom_data + loaded, 1, load_len - loaded);
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159 |
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160 | if (n_rd == 0) {
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161 | fail("error while reading BIOS file %s", bios);
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162 | }
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163 |
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164 | loaded += n_rd;
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165 | }
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166 |
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167 | SDL_RWclose(ops);
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168 |
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169 | rom_ro_beg = text_loc;
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170 | rom_ro_end = text_loc + text_len + data_len;
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171 | rom_rw_beg = bss_loc;
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172 | rom_rw_end = bss_loc + bss_len;
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173 |
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174 | ver("rom_ro_beg 0x%08x rom_ro_end 0x%08x", rom_ro_beg, rom_ro_end);
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175 | ver("rom_rw_beg 0x%08x rom_rw_end 0x%08x", rom_rw_beg, rom_rw_end);
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176 | }
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177 |
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178 | uint32_t m68k_read_disassembler_8(uint32_t addr)
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179 | {
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180 | return m68k_read_memory_8(addr);
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181 | }
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182 |
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183 | uint32_t m68k_read_disassembler_16(uint32_t addr)
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184 | {
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185 | return m68k_read_memory_16(addr);
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186 | }
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187 |
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188 | uint32_t m68k_read_disassembler_32(uint32_t addr)
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189 | {
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190 | return m68k_read_memory_32(addr);
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191 | }
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192 |
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193 | uint32_t m68k_read_memory_8(uint32_t addr)
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194 | {
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195 | ver3("mem rd 0x%08x:8", addr);
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196 |
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197 | if (addr >= ram_ro_beg && addr <= ram_ro_end - 1) {
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198 | return ram_data[addr - RAM_START];
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199 | }
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200 |
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201 | if (addr >= ram_rw_beg && addr <= ram_rw_end - 1) {
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202 | return ram_data[addr - RAM_START];
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203 | }
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204 |
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205 | if (addr >= rom_ro_beg && addr <= rom_ro_end - 1) {
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206 | return rom_data[addr - ROM_START];
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207 | }
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208 |
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209 | if (addr >= rom_rw_beg && addr <= rom_rw_end - 1) {
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210 | // ROM has its BSS section in RAM.
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211 | return ram_data[addr - RAM_START];
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212 | }
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213 |
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214 | hw_t *hw = hw_by_addr(addr);
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215 |
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216 | if (hw != NULL) {
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217 | return hw->read(hw_off(hw, addr), 1);
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218 | }
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219 |
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220 | if (addr <= APP_START - 1) {
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221 | return ram_data[addr];
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222 | }
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223 |
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224 | fail("invalid read 0x%08x:8", addr);
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225 | }
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226 |
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227 | uint32_t m68k_read_memory_16(uint32_t addr)
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228 | {
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229 | ver3("mem rd 0x%08x:16", addr);
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230 |
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231 | if (addr >= ram_ro_beg && addr <= ram_ro_end - 2) {
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232 | return
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233 | ((uint32_t)ram_data[addr - RAM_START + 0] << 8) |
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234 | ((uint32_t)ram_data[addr - RAM_START + 1] << 0);
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235 | }
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236 |
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237 | if (addr >= ram_rw_beg && addr <= ram_rw_end - 2) {
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238 | return
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239 | ((uint32_t)ram_data[addr - RAM_START + 0] << 8) |
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240 | ((uint32_t)ram_data[addr - RAM_START + 1] << 0);
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241 | }
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242 |
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243 | if (addr >= rom_ro_beg && addr <= rom_ro_end - 2) {
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244 | return
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245 | ((uint32_t)rom_data[addr - ROM_START + 0] << 8) |
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246 | ((uint32_t)rom_data[addr - ROM_START + 1] << 0);
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247 | }
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248 |
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249 | if (addr >= rom_rw_beg && addr <= rom_rw_end - 2) {
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250 | // ROM has its BSS section in RAM.
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251 | return
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252 | ((uint32_t)ram_data[addr - RAM_START + 0] << 8) |
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253 | ((uint32_t)ram_data[addr - RAM_START + 1] << 0);
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254 | }
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255 |
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256 | hw_t *hw = hw_by_addr(addr);
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257 |
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258 | if (hw != NULL) {
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259 | return hw->read(hw_off(hw, addr), 2);
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260 | }
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261 |
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262 | if (addr <= APP_START - 2) {
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263 | return
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264 | ((uint32_t)ram_data[addr + 0] << 8) |
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265 | ((uint32_t)ram_data[addr + 1] << 0);
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266 | }
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267 |
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268 | fail("invalid read 0x%08x:16", addr);
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269 | }
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270 |
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271 | uint32_t m68k_read_memory_32(uint32_t addr)
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272 | {
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273 | ver3("mem rd 0x%08x:32", addr);
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274 |
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275 | if (reset) {
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276 | if (addr == 0) {
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277 | addr += ROM_START;
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278 | }
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279 | else if (addr == 4) {
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280 | addr += ROM_START;
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281 | reset = false;
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282 | }
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283 | else {
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284 | fail("invalid reset sequence");
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285 | }
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286 | }
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287 |
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288 | if (addr >= ram_ro_beg && addr <= ram_ro_end - 4) {
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289 | return
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290 | ((uint32_t)ram_data[addr - RAM_START + 0] << 24) |
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291 | ((uint32_t)ram_data[addr - RAM_START + 1] << 16) |
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292 | ((uint32_t)ram_data[addr - RAM_START + 2] << 8) |
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293 | ((uint32_t)ram_data[addr - RAM_START + 3] << 0);
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294 | }
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295 |
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296 | if (addr >= ram_rw_beg && addr <= ram_rw_end - 4) {
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297 | return
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298 | ((uint32_t)ram_data[addr - RAM_START + 0] << 24) |
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299 | ((uint32_t)ram_data[addr - RAM_START + 1] << 16) |
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300 | ((uint32_t)ram_data[addr - RAM_START + 2] << 8) |
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301 | ((uint32_t)ram_data[addr - RAM_START + 3] << 0);
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302 | }
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303 |
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304 | if (addr >= rom_ro_beg && addr <= rom_ro_end - 4) {
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305 | return
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306 | ((uint32_t)rom_data[addr - ROM_START + 0] << 24) |
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307 | ((uint32_t)rom_data[addr - ROM_START + 1] << 16) |
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308 | ((uint32_t)rom_data[addr - ROM_START + 2] << 8) |
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309 | ((uint32_t)rom_data[addr - ROM_START + 3] << 0);
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310 | }
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311 |
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312 | if (addr >= rom_rw_beg && addr <= rom_rw_end - 4) {
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313 | // ROM has its BSS section in RAM.
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314 | return
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315 | ((uint32_t)ram_data[addr - RAM_START + 0] << 24) |
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316 | ((uint32_t)ram_data[addr - RAM_START + 1] << 16) |
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317 | ((uint32_t)ram_data[addr - RAM_START + 2] << 8) |
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318 | ((uint32_t)ram_data[addr - RAM_START + 3] << 0);
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319 | }
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320 |
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321 | hw_t *hw = hw_by_addr(addr);
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322 |
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323 | if (hw != NULL) {
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324 | return hw->read(hw_off(hw, addr), 4);
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325 | }
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326 |
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327 | if (addr <= APP_START - 4) {
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328 | return
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329 | ((uint32_t)ram_data[addr + 0] << 24) |
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330 | ((uint32_t)ram_data[addr + 1] << 16) |
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331 | ((uint32_t)ram_data[addr + 2] << 8) |
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332 | ((uint32_t)ram_data[addr + 3] << 0);
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333 | }
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334 |
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335 | fail("invalid read 0x%08x:32", addr);
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336 | }
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337 |
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338 | void m68k_write_memory_8(uint32_t addr, uint32_t val)
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339 | {
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340 | ver3("mem wr 0x%08x:8 0x%02x", addr, val);
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341 |
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342 | if (addr >= ram_rw_beg && addr <= ram_rw_end - 1) {
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343 | ram_data[addr - RAM_START] = (uint8_t)val;
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344 | return;
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345 | }
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346 |
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347 | if (addr >= rom_rw_beg && addr <= rom_rw_end - 1) {
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348 | // ROM has its BSS section in RAM.
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349 | ram_data[addr - RAM_START] = (uint8_t)val;
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350 | return;
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351 | }
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352 |
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353 | hw_t *hw = hw_by_addr(addr);
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354 |
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355 | if (hw != NULL) {
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356 | hw->write(hw_off(hw, addr), 1, val);
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357 | return;
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358 | }
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359 |
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360 | if (addr <= APP_START - 1) {
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361 | ram_data[addr] = (uint8_t)val;
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362 | return;
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363 | }
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364 |
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365 | fail("invalid write 0x%08x:8 0x%02x", addr, val);
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366 | }
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367 |
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368 | void m68k_write_memory_16(uint32_t addr, uint32_t val)
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369 | {
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370 | ver3("mem wr 0x%08x:16 0x%04x", addr, val);
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371 |
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372 | if (addr >= ram_rw_beg && addr <= ram_rw_end - 2) {
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373 | ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 8);
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374 | ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 0);
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375 | return;
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376 | }
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377 |
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378 | if (addr >= rom_rw_beg && addr <= rom_rw_end - 2) {
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379 | // ROM has its BSS section in RAM.
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380 | ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 8);
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381 | ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 0);
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382 | return;
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383 | }
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384 |
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385 | hw_t *hw = hw_by_addr(addr);
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386 |
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387 | if (hw != NULL) {
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388 | hw->write(hw_off(hw, addr), 2, val);
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389 | return;
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390 | }
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391 |
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392 | if (addr <= APP_START - 2) {
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393 | ram_data[addr + 0] = (uint8_t)(val >> 8);
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394 | ram_data[addr + 1] = (uint8_t)(val >> 0);
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395 | return;
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396 | }
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397 |
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398 | fail("invalid write 0x%08x:16 0x%04x", addr, val);
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399 | }
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400 |
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401 | void m68k_write_memory_32(uint32_t addr, uint32_t val)
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402 | {
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403 | ver3("mem wr 0x%08x:32 0x%08x", addr, val);
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404 |
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405 | if (addr >= ram_rw_beg && addr <= ram_rw_end - 4) {
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406 | ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 24);
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407 | ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 16);
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408 | ram_data[addr - RAM_START + 2] = (uint8_t)(val >> 8);
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409 | ram_data[addr - RAM_START + 3] = (uint8_t)(val >> 0);
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410 | return;
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411 | }
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412 |
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413 | if (addr >= rom_rw_beg && addr <= rom_rw_end - 4) {
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414 | // ROM has its BSS section in RAM.
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415 | ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 24);
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416 | ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 16);
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417 | ram_data[addr - RAM_START + 2] = (uint8_t)(val >> 8);
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418 | ram_data[addr - RAM_START + 3] = (uint8_t)(val >> 0);
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419 | return;
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420 | }
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---|
421 |
|
---|
422 | hw_t *hw = hw_by_addr(addr);
|
---|
423 |
|
---|
424 | if (hw != NULL) {
|
---|
425 | hw->write(hw_off(hw, addr), 4, val);
|
---|
426 | return;
|
---|
427 | }
|
---|
428 |
|
---|
429 | if (addr <= APP_START - 4) {
|
---|
430 | ram_data[addr + 0] = (uint8_t)(val >> 24);
|
---|
431 | ram_data[addr + 1] = (uint8_t)(val >> 16);
|
---|
432 | ram_data[addr + 2] = (uint8_t)(val >> 8);
|
---|
433 | ram_data[addr + 3] = (uint8_t)(val >> 0);
|
---|
434 | return;
|
---|
435 | }
|
---|
436 |
|
---|
437 | fail("invalid write 0x%08x:32 0x%08x", addr, val);
|
---|
438 | }
|
---|
439 |
|
---|
440 | static void inst_cb(void)
|
---|
441 | {
|
---|
442 | uint32_t pc = m68k_get_reg(NULL, M68K_REG_PC);
|
---|
443 | uint32_t op = m68k_read_memory_16(pc);
|
---|
444 |
|
---|
445 | if (op == 0x4e4d) {
|
---|
446 | uint32_t sp = m68k_get_reg(NULL, M68K_REG_SP);
|
---|
447 | uint32_t fun = m68k_read_memory_16(sp);
|
---|
448 |
|
---|
449 | switch (fun) {
|
---|
450 | case 1:
|
---|
451 | ver2("BIOS B_RDAV %u", m68k_read_memory_16(sp + 2));
|
---|
452 | break;
|
---|
453 |
|
---|
454 | case 2:
|
---|
455 | ver2("BIOS B_GETC %u", m68k_read_memory_16(sp + 2));
|
---|
456 | break;
|
---|
457 |
|
---|
458 | case 3:
|
---|
459 | ver2("BIOS B_PUTC %u %u",
|
---|
460 | m68k_read_memory_16(sp + 2),
|
---|
461 | m68k_read_memory_16(sp + 4));
|
---|
462 | break;
|
---|
463 |
|
---|
464 | case 4:
|
---|
465 | ver2("BIOS B_RDWR %u 0x%08x %u %u %u",
|
---|
466 | m68k_read_memory_16(sp + 2),
|
---|
467 | m68k_read_memory_32(sp + 4),
|
---|
468 | m68k_read_memory_16(sp + 8),
|
---|
469 | m68k_read_memory_16(sp + 10),
|
---|
470 | m68k_read_memory_16(sp + 12));
|
---|
471 | break;
|
---|
472 |
|
---|
473 | case 5:
|
---|
474 | ver2("BIOS B_SETV %u 0x%08x",
|
---|
475 | m68k_read_memory_16(sp + 2),
|
---|
476 | m68k_read_memory_32(sp + 4));
|
---|
477 | break;
|
---|
478 |
|
---|
479 | case 7:
|
---|
480 | ver2("BIOS B_GBPB %u", m68k_read_memory_16(sp + 2));
|
---|
481 | break;
|
---|
482 |
|
---|
483 | case 8:
|
---|
484 | ver2("BIOS B_THRE %u", m68k_read_memory_16(sp + 2));
|
---|
485 | break;
|
---|
486 |
|
---|
487 | case 9:
|
---|
488 | ver2("BIOS B_MCHG %u", m68k_read_memory_16(sp + 2));
|
---|
489 | break;
|
---|
490 |
|
---|
491 | case 10:
|
---|
492 | ver2("BIOS B_DMAP");
|
---|
493 | break;
|
---|
494 |
|
---|
495 | default:
|
---|
496 | fail("invalid function: BIOS %d", fun);
|
---|
497 | }
|
---|
498 | }
|
---|
499 | else if (op == 0x4e4e) {
|
---|
500 | uint32_t sp = m68k_get_reg(NULL, M68K_REG_SP);
|
---|
501 | uint32_t fun = m68k_read_memory_16(sp);
|
---|
502 |
|
---|
503 | switch (fun) {
|
---|
504 | case 0:
|
---|
505 | ver2("XBIOS X_PIOREC %u", m68k_read_memory_16(sp + 2));
|
---|
506 | break;
|
---|
507 |
|
---|
508 | case 1:
|
---|
509 | ver2("XBIOS X_SETPRT %u 0x%02x 0x%02x 0x%02x 0x%02x",
|
---|
510 | m68k_read_memory_16(sp + 2),
|
---|
511 | m68k_read_memory_16(sp + 4),
|
---|
512 | m68k_read_memory_16(sp + 6),
|
---|
513 | m68k_read_memory_16(sp + 8),
|
---|
514 | m68k_read_memory_16(sp + 10));
|
---|
515 | break;
|
---|
516 |
|
---|
517 | case 2:
|
---|
518 | ver2("XBIOS X_FLOPRD 0x%08x 0x%08x %u %u %u %u %u",
|
---|
519 | m68k_read_memory_32(sp + 2),
|
---|
520 | m68k_read_memory_32(sp + 6),
|
---|
521 | m68k_read_memory_16(sp + 10),
|
---|
522 | m68k_read_memory_16(sp + 12),
|
---|
523 | m68k_read_memory_16(sp + 14),
|
---|
524 | m68k_read_memory_16(sp + 16),
|
---|
525 | m68k_read_memory_16(sp + 18));
|
---|
526 | break;
|
---|
527 |
|
---|
528 | case 3:
|
---|
529 | ver2("XBIOS X_FLOPWR 0x%08x 0x%08x %u %u %u %u %u",
|
---|
530 | m68k_read_memory_32(sp + 2),
|
---|
531 | m68k_read_memory_32(sp + 6),
|
---|
532 | m68k_read_memory_16(sp + 10),
|
---|
533 | m68k_read_memory_16(sp + 12),
|
---|
534 | m68k_read_memory_16(sp + 14),
|
---|
535 | m68k_read_memory_16(sp + 16),
|
---|
536 | m68k_read_memory_16(sp + 18));
|
---|
537 | break;
|
---|
538 |
|
---|
539 | case 4:
|
---|
540 | ver2("XBIOS X_FORMAT 0x%08x 0x%08x %u %u %u %u %u 0x%08x %u",
|
---|
541 | m68k_read_memory_32(sp + 2),
|
---|
542 | m68k_read_memory_32(sp + 6),
|
---|
543 | m68k_read_memory_16(sp + 10),
|
---|
544 | m68k_read_memory_16(sp + 12),
|
---|
545 | m68k_read_memory_16(sp + 14),
|
---|
546 | m68k_read_memory_16(sp + 16),
|
---|
547 | m68k_read_memory_16(sp + 18),
|
---|
548 | m68k_read_memory_32(sp + 20),
|
---|
549 | m68k_read_memory_16(sp + 24));
|
---|
550 | break;
|
---|
551 |
|
---|
552 | case 5:
|
---|
553 | ver2("XBIOS X_VERIFY 0x%08x 0x%08x %u %u %u %u %u",
|
---|
554 | m68k_read_memory_32(sp + 2),
|
---|
555 | m68k_read_memory_32(sp + 6),
|
---|
556 | m68k_read_memory_16(sp + 10),
|
---|
557 | m68k_read_memory_16(sp + 12),
|
---|
558 | m68k_read_memory_16(sp + 14),
|
---|
559 | m68k_read_memory_16(sp + 16),
|
---|
560 | m68k_read_memory_16(sp + 18));
|
---|
561 | break;
|
---|
562 |
|
---|
563 | case 6:
|
---|
564 | ver2("XBIOS X_PRBOOT 0x%08x %u %u %u",
|
---|
565 | m68k_read_memory_32(sp + 2),
|
---|
566 | m68k_read_memory_16(sp + 6),
|
---|
567 | m68k_read_memory_16(sp + 8),
|
---|
568 | m68k_read_memory_16(sp + 10));
|
---|
569 | break;
|
---|
570 |
|
---|
571 | case 7:
|
---|
572 | ver2("XBIOS X_RANDOM");
|
---|
573 | break;
|
---|
574 |
|
---|
575 | case 8:
|
---|
576 | ver2("XBIOS X_ANALOG");
|
---|
577 | break;
|
---|
578 |
|
---|
579 | case 9:
|
---|
580 | ver2("XBIOS X_CLRAFI");
|
---|
581 | break;
|
---|
582 |
|
---|
583 | case 10:
|
---|
584 | ver2("XBIOS X_APICHK");
|
---|
585 | break;
|
---|
586 |
|
---|
587 | case 11:
|
---|
588 | ver2("XBIOS X_MTDEFS ");
|
---|
589 | break;
|
---|
590 |
|
---|
591 | default:
|
---|
592 | fail("invalid function: XBIOS %d", fun);
|
---|
593 | }
|
---|
594 | }
|
---|
595 | }
|
---|
596 |
|
---|
597 | void cpu_loop(const char *bios)
|
---|
598 | {
|
---|
599 | hw_init();
|
---|
600 | bios_init(bios);
|
---|
601 |
|
---|
602 | inf("entering CPU loop");
|
---|
603 | m68k_init();
|
---|
604 | m68k_set_cpu_type(M68K_CPU_TYPE_68000);
|
---|
605 | m68k_set_instr_hook_callback(inst_cb);
|
---|
606 | m68k_pulse_reset();
|
---|
607 |
|
---|
608 | uint64_t freq = SDL_GetPerformanceFrequency();
|
---|
609 | uint64_t quan = freq / PER_SEC;
|
---|
610 | inf("freq %" PRIu64 " quan %" PRIu64, freq, quan);
|
---|
611 |
|
---|
612 | bool run = true;
|
---|
613 |
|
---|
614 | while (run) {
|
---|
615 | uint64_t until = SDL_GetPerformanceCounter() + quan;
|
---|
616 |
|
---|
617 | m68k_execute(CPU_FREQ / PER_SEC);
|
---|
618 | hw_exec();
|
---|
619 |
|
---|
620 | SDL_Event ev;
|
---|
621 |
|
---|
622 | while (SDL_PollEvent(&ev) > 0) {
|
---|
623 | if (ev.type == SDL_QUIT) {
|
---|
624 | run = false;
|
---|
625 | }
|
---|
626 | }
|
---|
627 |
|
---|
628 | while (SDL_GetPerformanceCounter() < until) {
|
---|
629 | _mm_pause();
|
---|
630 | }
|
---|
631 | }
|
---|
632 |
|
---|
633 | inf("leaving CPU loop");
|
---|
634 | }
|
---|