source: buchla-emu/emu/cpu.c@ 4c71d39

Last change on this file since 4c71d39 was 4c71d39, checked in by Thomas Lopatic <thomas@…>, 7 years ago

More granular verbosity.
  • Property mode set to 100644
File size: 11.3 KB
Line 
1/*
2 * Copyright (C) 2017 The Contributors
3 *
4 * This program is free software: you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation, either version 3 of the License, or (at
7 * your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
13 *
14 * A copy of the GNU General Public License can be found in the file
15 * "gpl.txt" in the top directory of this repository.
16 */
17
18#include <all.h>
19
20#define ver(...) _ver(cpu_verbose, 0, __VA_ARGS__)
21#define ver2(...) _ver(cpu_verbose, 1, __VA_ARGS__)
22#define ver3(...) _ver(cpu_verbose, 2, __VA_ARGS__)
23
24int32_t cpu_verbose = 0;
25
26#define CPU_FREQ 7000000
27#define PER_SEC 100000
28
29#define APP_START 0x10000
30
31#define RAM_START 0x0
32#define RAM_SIZE 0x100000
33
34#define ROM_START 0x100000
35#define ROM_SIZE 0x10000
36
37typedef void (*hw_init_t)(void);
38typedef void (*hw_quit_t)(void);
39typedef void (*hw_exec_t)(void);
40typedef uint32_t (*hw_read_t)(uint32_t off, int32_t sz);
41typedef void (*hw_write_t)(uint32_t off, int32_t sz, uint32_t val);
42
43typedef struct {
44 uint32_t addr_beg;
45 uint32_t addr_end;
46 hw_init_t init;
47 hw_quit_t quit;
48 hw_exec_t exec;
49 hw_read_t read;
50 hw_write_t write;
51} hw_t;
52
53static bool reset = true;
54
55static uint8_t ram_data[RAM_SIZE];
56static uint8_t rom_data[ROM_SIZE];
57
58static uint32_t ram_ro_beg = 0x1234;
59static uint32_t ram_ro_end = 0x1234;
60static uint32_t ram_rw_beg = 0x1234;
61static uint32_t ram_rw_end = 0x1234;
62
63static uint32_t rom_ro_beg;
64static uint32_t rom_ro_end;
65static uint32_t rom_rw_beg;
66static uint32_t rom_rw_end;
67
68static hw_t hw_map[] = {
69 { 0x180000, 0x200000, fpu_init, fpu_quit, fpu_exec, fpu_read, fpu_write },
70 { 0x200000, 0x280000, vid_init, vid_quit, vid_exec, vid_read, vid_write },
71 { 0x3a0001, 0x3a4001, tim_init, tim_quit, tim_exec, tim_read, tim_write },
72 { 0x3a4001, 0x3a8001, lcd_init, lcd_quit, lcd_exec, lcd_read, lcd_write },
73 { 0x3a8001, 0x3ac001, ser_init, ser_quit, ser_exec, ser_read, ser_write },
74 { 0x3ac001, 0x3b0001, mid_init, mid_quit, mid_exec, mid_read, mid_write },
75 { 0x3b0001, 0x3b4001, fdd_init, fdd_quit, fdd_exec, fdd_read, fdd_write },
76 { 0x3b4001, 0x3b8001, snd_init, snd_quit, snd_exec, snd_read, snd_write },
77 { 0x3b8001, 0x3bc001, led_init, led_quit, led_exec, led_read, led_write },
78 { 0x3bc001, 0x3c0001, kbd_init, kbd_quit, kbd_exec, kbd_read, kbd_write }
79};
80
81static hw_t *hw_by_addr(uint32_t addr)
82{
83 for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
84 if (addr >= hw_map[i].addr_beg && addr < hw_map[i].addr_end) {
85 return hw_map + i;
86 }
87 }
88
89 return NULL;
90}
91
92static void hw_init(void)
93{
94 inf("initializing hardware");
95
96 for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
97 hw_map[i].init();
98 }
99}
100
101static void hw_exec(void)
102{
103 for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
104 hw_map[i].exec();
105 }
106}
107
108static uint32_t hw_off(hw_t *hw, uint32_t addr)
109{
110 if ((hw->addr_beg & 0x1) == 0) {
111 return addr - hw->addr_beg;
112 }
113
114 return (addr - hw->addr_beg) / 2;
115}
116
117static void bios_init(const char *bios)
118{
119 inf("loading BIOS file %s", bios);
120
121 SDL_RWops *ops = SDL_RWFromFile(bios, "rb");
122
123 if (ops == NULL) {
124 fail("error while opening BIOS file %s", bios);
125 }
126
127 if (SDL_ReadBE16(ops) != 0x601b) {
128 fail("invalid BIOS file %s", bios);
129 }
130
131 uint32_t text_len = SDL_ReadBE32(ops);
132 uint32_t data_len = SDL_ReadBE32(ops);
133 uint32_t bss_len = SDL_ReadBE32(ops);
134
135 SDL_ReadBE32(ops);
136 SDL_ReadBE32(ops);
137
138 uint32_t text_loc = SDL_ReadBE32(ops);
139
140 SDL_ReadBE16(ops);
141
142 uint32_t data_loc = SDL_ReadBE32(ops);
143 uint32_t bss_loc = SDL_ReadBE32(ops);
144
145 inf("BIOS text 0x%x:0x%x data 0x%x:0x%x bss 0x%x:0x%x",
146 text_loc, text_len, data_loc, data_len, bss_loc, bss_len);
147
148 size_t load_len = (size_t)SDL_RWsize(ops) - 36;
149
150 if (text_loc != ROM_START || text_loc + text_len != data_loc ||
151 load_len != text_len + data_len || load_len > ROM_SIZE) {
152 fail("invalid BIOS file %s", bios);
153 }
154
155 size_t loaded = 0;
156
157 while (loaded < load_len) {
158 size_t n_rd = SDL_RWread(ops, rom_data + loaded, 1, load_len - loaded);
159
160 if (n_rd == 0) {
161 fail("error while reading BIOS file %s", bios);
162 }
163
164 loaded += n_rd;
165 }
166
167 SDL_RWclose(ops);
168
169 rom_ro_beg = text_loc;
170 rom_ro_end = text_loc + text_len + data_len;
171 rom_rw_beg = bss_loc;
172 rom_rw_end = bss_loc + bss_len;
173
174 ver("rom_ro_beg 0x%08x rom_ro_end 0x%08x", rom_ro_beg, rom_ro_end);
175 ver("rom_rw_beg 0x%08x rom_rw_end 0x%08x", rom_rw_beg, rom_rw_end);
176}
177
178uint32_t m68k_read_disassembler_8(uint32_t addr)
179{
180 return m68k_read_memory_8(addr);
181}
182
183uint32_t m68k_read_disassembler_16(uint32_t addr)
184{
185 return m68k_read_memory_16(addr);
186}
187
188uint32_t m68k_read_disassembler_32(uint32_t addr)
189{
190 return m68k_read_memory_32(addr);
191}
192
193uint32_t m68k_read_memory_8(uint32_t addr)
194{
195 ver3("mem rd 0x%08x:8", addr);
196
197 if (addr >= ram_ro_beg && addr <= ram_ro_end - 1) {
198 return ram_data[addr - RAM_START];
199 }
200
201 if (addr >= ram_rw_beg && addr <= ram_rw_end - 1) {
202 return ram_data[addr - RAM_START];
203 }
204
205 if (addr >= rom_ro_beg && addr <= rom_ro_end - 1) {
206 return rom_data[addr - ROM_START];
207 }
208
209 if (addr >= rom_rw_beg && addr <= rom_rw_end - 1) {
210 // ROM has its BSS section in RAM.
211 return ram_data[addr - RAM_START];
212 }
213
214 hw_t *hw = hw_by_addr(addr);
215
216 if (hw != NULL) {
217 return hw->read(hw_off(hw, addr), 1);
218 }
219
220 if (addr <= APP_START - 1) {
221 return ram_data[addr];
222 }
223
224 fail("invalid read 0x%08x:8", addr);
225}
226
227uint32_t m68k_read_memory_16(uint32_t addr)
228{
229 ver3("mem rd 0x%08x:16", addr);
230
231 if (addr >= ram_ro_beg && addr <= ram_ro_end - 2) {
232 return
233 ((uint32_t)ram_data[addr - RAM_START + 0] << 8) |
234 ((uint32_t)ram_data[addr - RAM_START + 1] << 0);
235 }
236
237 if (addr >= ram_rw_beg && addr <= ram_rw_end - 2) {
238 return
239 ((uint32_t)ram_data[addr - RAM_START + 0] << 8) |
240 ((uint32_t)ram_data[addr - RAM_START + 1] << 0);
241 }
242
243 if (addr >= rom_ro_beg && addr <= rom_ro_end - 2) {
244 return
245 ((uint32_t)rom_data[addr - ROM_START + 0] << 8) |
246 ((uint32_t)rom_data[addr - ROM_START + 1] << 0);
247 }
248
249 if (addr >= rom_rw_beg && addr <= rom_rw_end - 2) {
250 // ROM has its BSS section in RAM.
251 return
252 ((uint32_t)ram_data[addr - RAM_START + 0] << 8) |
253 ((uint32_t)ram_data[addr - RAM_START + 1] << 0);
254 }
255
256 hw_t *hw = hw_by_addr(addr);
257
258 if (hw != NULL) {
259 return hw->read(hw_off(hw, addr), 2);
260 }
261
262 if (addr <= APP_START - 2) {
263 return
264 ((uint32_t)ram_data[addr - 0] << 8) |
265 ((uint32_t)ram_data[addr - 1] << 0);
266 }
267
268 fail("invalid read 0x%08x:16", addr);
269}
270
271uint32_t m68k_read_memory_32(uint32_t addr)
272{
273 ver3("mem rd 0x%08x:32", addr);
274
275 if (reset) {
276 if (addr == 0) {
277 addr += ROM_START;
278 }
279
280 else if (addr == 4) {
281 addr += ROM_START;
282 reset = false;
283 }
284 else {
285 fail("invalid reset sequence");
286 }
287 }
288
289 if (addr >= ram_ro_beg && addr <= ram_ro_end - 4) {
290 return
291 ((uint32_t)ram_data[addr - RAM_START + 0] << 24) |
292 ((uint32_t)ram_data[addr - RAM_START + 1] << 16) |
293 ((uint32_t)ram_data[addr - RAM_START + 2] << 8) |
294 ((uint32_t)ram_data[addr - RAM_START + 3] << 0);
295 }
296
297 if (addr >= ram_rw_beg && addr <= ram_rw_end - 4) {
298 return
299 ((uint32_t)ram_data[addr - RAM_START + 0] << 24) |
300 ((uint32_t)ram_data[addr - RAM_START + 1] << 16) |
301 ((uint32_t)ram_data[addr - RAM_START + 2] << 8) |
302 ((uint32_t)ram_data[addr - RAM_START + 3] << 0);
303 }
304
305 if (addr >= rom_ro_beg && addr <= rom_ro_end - 4) {
306 return
307 ((uint32_t)rom_data[addr - ROM_START + 0] << 24) |
308 ((uint32_t)rom_data[addr - ROM_START + 1] << 16) |
309 ((uint32_t)rom_data[addr - ROM_START + 2] << 8) |
310 ((uint32_t)rom_data[addr - ROM_START + 3] << 0);
311 }
312
313 if (addr >= rom_rw_beg && addr <= rom_rw_end - 4) {
314 // ROM has its BSS section in RAM.
315 return
316 ((uint32_t)ram_data[addr - RAM_START + 0] << 24) |
317 ((uint32_t)ram_data[addr - RAM_START + 1] << 16) |
318 ((uint32_t)ram_data[addr - RAM_START + 2] << 8) |
319 ((uint32_t)ram_data[addr - RAM_START + 3] << 0);
320 }
321
322 hw_t *hw = hw_by_addr(addr);
323
324 if (hw != NULL) {
325 return hw->read(hw_off(hw, addr), 4);
326 }
327
328 if (addr <= APP_START - 4) {
329 return
330 ((uint32_t)ram_data[addr + 0] << 24) |
331 ((uint32_t)ram_data[addr + 1] << 16) |
332 ((uint32_t)ram_data[addr + 2] << 8) |
333 ((uint32_t)ram_data[addr + 3] << 0);
334 }
335
336 fail("invalid read 0x%08x:32", addr);
337}
338
339void m68k_write_memory_8(uint32_t addr, uint32_t val)
340{
341 ver3("mem wr 0x%08x:8 0x%02x", addr, val);
342
343 if (addr >= ram_rw_beg && addr <= ram_rw_end - 1) {
344 ram_data[addr - RAM_START] = (uint8_t)val;
345 return;
346 }
347
348 if (addr >= rom_rw_beg && addr <= rom_rw_end - 1) {
349 // ROM has its BSS section in RAM.
350 ram_data[addr - RAM_START] = (uint8_t)val;
351 return;
352 }
353
354 hw_t *hw = hw_by_addr(addr);
355
356 if (hw != NULL) {
357 hw->write(hw_off(hw, addr), 1, val);
358 return;
359 }
360
361 if (addr <= APP_START - 1) {
362 ram_data[addr] = (uint8_t)val;
363 return;
364 }
365
366 fail("invalid write 0x%08x:8 0x%02x", addr, val);
367}
368
369void m68k_write_memory_16(uint32_t addr, uint32_t val)
370{
371 ver3("mem wr 0x%08x:16 0x%04x", addr, val);
372
373 if (addr >= ram_rw_beg && addr <= ram_rw_end - 2) {
374 ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 8);
375 ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 0);
376 return;
377 }
378
379 if (addr >= rom_rw_beg && addr <= rom_rw_end - 2) {
380 // ROM has its BSS section in RAM.
381 ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 8);
382 ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 0);
383 return;
384 }
385
386 hw_t *hw = hw_by_addr(addr);
387
388 if (hw != NULL) {
389 hw->write(hw_off(hw, addr), 2, val);
390 return;
391 }
392
393 if (addr <= APP_START - 2) {
394 ram_data[addr + 0] = (uint8_t)(val >> 8);
395 ram_data[addr + 1] = (uint8_t)(val >> 0);
396 return;
397 }
398
399 fail("invalid write 0x%08x:16 0x%04x", addr, val);
400}
401
402void m68k_write_memory_32(uint32_t addr, uint32_t val)
403{
404 ver3("mem wr 0x%08x:32 0x%08x", addr, val);
405
406 if (addr >= ram_rw_beg && addr <= ram_rw_end - 4) {
407 ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 24);
408 ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 16);
409 ram_data[addr - RAM_START + 2] = (uint8_t)(val >> 8);
410 ram_data[addr - RAM_START + 3] = (uint8_t)(val >> 0);
411 return;
412 }
413
414 if (addr >= rom_rw_beg && addr <= rom_rw_end - 4) {
415 // ROM has its BSS section in RAM.
416 ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 24);
417 ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 16);
418 ram_data[addr - RAM_START + 2] = (uint8_t)(val >> 8);
419 ram_data[addr - RAM_START + 3] = (uint8_t)(val >> 0);
420 return;
421 }
422
423 hw_t *hw = hw_by_addr(addr);
424
425 if (hw != NULL) {
426 hw->write(hw_off(hw, addr), 4, val);
427 return;
428 }
429
430 if (addr <= APP_START - 4) {
431 ram_data[addr + 0] = (uint8_t)(val >> 24);
432 ram_data[addr + 1] = (uint8_t)(val >> 16);
433 ram_data[addr + 2] = (uint8_t)(val >> 8);
434 ram_data[addr + 3] = (uint8_t)(val >> 0);
435 return;
436 }
437
438 fail("invalid write 0x%08x:32 0x%08x", addr, val);
439}
440
441void cpu_loop(const char *bios)
442{
443 hw_init();
444 bios_init(bios);
445
446 inf("entering CPU loop");
447 m68k_init();
448 m68k_set_cpu_type(M68K_CPU_TYPE_68000);
449 m68k_pulse_reset();
450
451 uint64_t freq = SDL_GetPerformanceFrequency();
452 uint64_t quan = freq / PER_SEC;
453 inf("freq %" PRIu64 " quan %" PRIu64, freq, quan);
454
455 bool run = true;
456
457 while (run) {
458 uint64_t until = SDL_GetPerformanceCounter() + quan;
459
460 m68k_execute(CPU_FREQ / PER_SEC);
461 hw_exec();
462
463 SDL_Event ev;
464
465 while (SDL_PollEvent(&ev) > 0) {
466 if (ev.type == SDL_QUIT) {
467 run = false;
468 }
469 }
470
471 while (SDL_GetPerformanceCounter() < until) {
472 _mm_pause();
473 }
474 }
475
476 inf("leaving CPU loop");
477}
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