source: buchla-emu/emu/cpu.c@ ebc8f69

Last change on this file since ebc8f69 was ebc8f69, checked in by Thomas Lopatic <thomas@…>, 7 years ago

Throttle CPU to 7 MHz.
  • Property mode set to 100644
File size: 11.3 KB
Line 
1/*
2 * Copyright (C) 2017 The Contributors
3 *
4 * This program is free software: you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation, either version 3 of the License, or (at
7 * your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
13 *
14 * A copy of the GNU General Public License can be found in the file
15 * "gpl.txt" in the top directory of this repository.
16 */
17
18#include <all.h>
19
20#define ver(...) { \
21 if (cpu_verbose) { \
22 SDL_LogVerbose(SDL_LOG_CATEGORY_APPLICATION, __VA_ARGS__); \
23 } \
24}
25
26bool cpu_verbose = false;
27
28#define CPU_FREQ 7000000
29#define PER_SEC 100000
30
31#define APP_START 0x10000
32
33#define RAM_START 0x0
34#define RAM_SIZE 0x100000
35
36#define ROM_START 0x100000
37#define ROM_SIZE 0x10000
38
39typedef void (*hw_init_t)(void);
40typedef void (*hw_quit_t)(void);
41typedef void (*hw_exec_t)(void);
42typedef uint32_t (*hw_read_t)(uint32_t off, int32_t sz);
43typedef void (*hw_write_t)(uint32_t off, int32_t sz, uint32_t val);
44
45typedef struct {
46 uint32_t addr_beg;
47 uint32_t addr_end;
48 hw_init_t init;
49 hw_quit_t quit;
50 hw_exec_t exec;
51 hw_read_t read;
52 hw_write_t write;
53} hw_t;
54
55static bool reset = true;
56
57static uint8_t ram_data[RAM_SIZE];
58static uint8_t rom_data[ROM_SIZE];
59
60static uint32_t ram_ro_beg = 0x1234;
61static uint32_t ram_ro_end = 0x1234;
62static uint32_t ram_rw_beg = 0x1234;
63static uint32_t ram_rw_end = 0x1234;
64
65static uint32_t rom_ro_beg;
66static uint32_t rom_ro_end;
67static uint32_t rom_rw_beg;
68static uint32_t rom_rw_end;
69
70static hw_t hw_map[] = {
71 { 0x180000, 0x200000, fpu_init, fpu_quit, fpu_exec, fpu_read, fpu_write },
72 { 0x200000, 0x280000, vid_init, vid_quit, vid_exec, vid_read, vid_write },
73 { 0x3a0001, 0x3a4001, tim_init, tim_quit, tim_exec, tim_read, tim_write },
74 { 0x3a4001, 0x3a8001, lcd_init, lcd_quit, lcd_exec, lcd_read, lcd_write },
75 { 0x3a8001, 0x3ac001, ser_init, ser_quit, ser_exec, ser_read, ser_write },
76 { 0x3ac001, 0x3b0001, mid_init, mid_quit, mid_exec, mid_read, mid_write },
77 { 0x3b0001, 0x3b4001, fdd_init, fdd_quit, fdd_exec, fdd_read, fdd_write },
78 { 0x3b4001, 0x3b8001, snd_init, snd_quit, snd_exec, snd_read, snd_write },
79 { 0x3b8001, 0x3bc001, led_init, led_quit, led_exec, led_read, led_write },
80 { 0x3bc001, 0x3c0001, kbd_init, kbd_quit, kbd_exec, kbd_read, kbd_write }
81};
82
83static hw_t *hw_by_addr(uint32_t addr)
84{
85 for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
86 if (addr >= hw_map[i].addr_beg && addr < hw_map[i].addr_end) {
87 return hw_map + i;
88 }
89 }
90
91 return NULL;
92}
93
94static void hw_init(void)
95{
96 inf("initializing hardware");
97
98 for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
99 hw_map[i].init();
100 }
101}
102
103static void hw_exec(void)
104{
105 for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
106 hw_map[i].exec();
107 }
108}
109
110static uint32_t hw_off(hw_t *hw, uint32_t addr)
111{
112 if ((hw->addr_beg & 0x1) == 0) {
113 return addr - hw->addr_beg;
114 }
115
116 return (addr - hw->addr_beg) / 2;
117}
118
119static void bios_init(const char *bios)
120{
121 inf("loading BIOS file %s", bios);
122
123 SDL_RWops *ops = SDL_RWFromFile(bios, "rb");
124
125 if (ops == NULL) {
126 fail("error while opening BIOS file %s", bios);
127 }
128
129 if (SDL_ReadBE16(ops) != 0x601b) {
130 fail("invalid BIOS file %s", bios);
131 }
132
133 uint32_t text_len = SDL_ReadBE32(ops);
134 uint32_t data_len = SDL_ReadBE32(ops);
135 uint32_t bss_len = SDL_ReadBE32(ops);
136
137 SDL_ReadBE32(ops);
138 SDL_ReadBE32(ops);
139
140 uint32_t text_loc = SDL_ReadBE32(ops);
141
142 SDL_ReadBE16(ops);
143
144 uint32_t data_loc = SDL_ReadBE32(ops);
145 uint32_t bss_loc = SDL_ReadBE32(ops);
146
147 inf("BIOS text 0x%x:0x%x data 0x%x:0x%x bss 0x%x:0x%x",
148 text_loc, text_len, data_loc, data_len, bss_loc, bss_len);
149
150 size_t load_len = (size_t)SDL_RWsize(ops) - 36;
151
152 if (text_loc != ROM_START || text_loc + text_len != data_loc ||
153 load_len != text_len + data_len || load_len > ROM_SIZE) {
154 fail("invalid BIOS file %s", bios);
155 }
156
157 size_t loaded = 0;
158
159 while (loaded < load_len) {
160 size_t n_rd = SDL_RWread(ops, rom_data + loaded, 1, load_len - loaded);
161
162 if (n_rd == 0) {
163 fail("error while reading BIOS file %s", bios);
164 }
165
166 loaded += n_rd;
167 }
168
169 SDL_RWclose(ops);
170
171 rom_ro_beg = text_loc;
172 rom_ro_end = text_loc + text_len + data_len;
173 rom_rw_beg = bss_loc;
174 rom_rw_end = bss_loc + bss_len;
175
176 ver("rom_ro_beg 0x%08x rom_ro_end 0x%08x", rom_ro_beg, rom_ro_end);
177 ver("rom_rw_beg 0x%08x rom_rw_end 0x%08x", rom_rw_beg, rom_rw_end);
178}
179
180uint32_t m68k_read_disassembler_8(uint32_t addr)
181{
182 return m68k_read_memory_8(addr);
183}
184
185uint32_t m68k_read_disassembler_16(uint32_t addr)
186{
187 return m68k_read_memory_16(addr);
188}
189
190uint32_t m68k_read_disassembler_32(uint32_t addr)
191{
192 return m68k_read_memory_32(addr);
193}
194
195uint32_t m68k_read_memory_8(uint32_t addr)
196{
197 ver("mem rd 0x%08x:8", addr);
198
199 if (addr >= ram_ro_beg && addr <= ram_ro_end - 1) {
200 return ram_data[addr - RAM_START];
201 }
202
203 if (addr >= ram_rw_beg && addr <= ram_rw_end - 1) {
204 return ram_data[addr - RAM_START];
205 }
206
207 if (addr >= rom_ro_beg && addr <= rom_ro_end - 1) {
208 return rom_data[addr - ROM_START];
209 }
210
211 if (addr >= rom_rw_beg && addr <= rom_rw_end - 1) {
212 // ROM has its BSS section in RAM.
213 return ram_data[addr - RAM_START];
214 }
215
216 hw_t *hw = hw_by_addr(addr);
217
218 if (hw != NULL) {
219 return hw->read(hw_off(hw, addr), 1);
220 }
221
222 if (addr <= APP_START - 1) {
223 return ram_data[addr];
224 }
225
226 fail("invalid read 0x%08x:8", addr);
227}
228
229uint32_t m68k_read_memory_16(uint32_t addr)
230{
231 ver("mem rd 0x%08x:16", addr);
232
233 if (addr >= ram_ro_beg && addr <= ram_ro_end - 2) {
234 return
235 ((uint32_t)ram_data[addr - RAM_START + 0] << 8) |
236 ((uint32_t)ram_data[addr - RAM_START + 1] << 0);
237 }
238
239 if (addr >= ram_rw_beg && addr <= ram_rw_end - 2) {
240 return
241 ((uint32_t)ram_data[addr - RAM_START + 0] << 8) |
242 ((uint32_t)ram_data[addr - RAM_START + 1] << 0);
243 }
244
245 if (addr >= rom_ro_beg && addr <= rom_ro_end - 2) {
246 return
247 ((uint32_t)rom_data[addr - ROM_START + 0] << 8) |
248 ((uint32_t)rom_data[addr - ROM_START + 1] << 0);
249 }
250
251 if (addr >= rom_rw_beg && addr <= rom_rw_end - 2) {
252 // ROM has its BSS section in RAM.
253 return
254 ((uint32_t)ram_data[addr - RAM_START + 0] << 8) |
255 ((uint32_t)ram_data[addr - RAM_START + 1] << 0);
256 }
257
258 hw_t *hw = hw_by_addr(addr);
259
260 if (hw != NULL) {
261 return hw->read(hw_off(hw, addr), 2);
262 }
263
264 if (addr <= APP_START - 2) {
265 return
266 ((uint32_t)ram_data[addr - 0] << 8) |
267 ((uint32_t)ram_data[addr - 1] << 0);
268 }
269
270 fail("invalid read 0x%08x:16", addr);
271}
272
273uint32_t m68k_read_memory_32(uint32_t addr)
274{
275 ver("mem rd 0x%08x:32", addr);
276
277 if (reset) {
278 if (addr == 0) {
279 addr += ROM_START;
280 }
281
282 else if (addr == 4) {
283 addr += ROM_START;
284 reset = false;
285 }
286 else {
287 fail("invalid reset sequence");
288 }
289 }
290
291 if (addr >= ram_ro_beg && addr <= ram_ro_end - 4) {
292 return
293 ((uint32_t)ram_data[addr - RAM_START + 0] << 24) |
294 ((uint32_t)ram_data[addr - RAM_START + 1] << 16) |
295 ((uint32_t)ram_data[addr - RAM_START + 2] << 8) |
296 ((uint32_t)ram_data[addr - RAM_START + 3] << 0);
297 }
298
299 if (addr >= ram_rw_beg && addr <= ram_rw_end - 4) {
300 return
301 ((uint32_t)ram_data[addr - RAM_START + 0] << 24) |
302 ((uint32_t)ram_data[addr - RAM_START + 1] << 16) |
303 ((uint32_t)ram_data[addr - RAM_START + 2] << 8) |
304 ((uint32_t)ram_data[addr - RAM_START + 3] << 0);
305 }
306
307 if (addr >= rom_ro_beg && addr <= rom_ro_end - 4) {
308 return
309 ((uint32_t)rom_data[addr - ROM_START + 0] << 24) |
310 ((uint32_t)rom_data[addr - ROM_START + 1] << 16) |
311 ((uint32_t)rom_data[addr - ROM_START + 2] << 8) |
312 ((uint32_t)rom_data[addr - ROM_START + 3] << 0);
313 }
314
315 if (addr >= rom_rw_beg && addr <= rom_rw_end - 4) {
316 // ROM has its BSS section in RAM.
317 return
318 ((uint32_t)ram_data[addr - RAM_START + 0] << 24) |
319 ((uint32_t)ram_data[addr - RAM_START + 1] << 16) |
320 ((uint32_t)ram_data[addr - RAM_START + 2] << 8) |
321 ((uint32_t)ram_data[addr - RAM_START + 3] << 0);
322 }
323
324 hw_t *hw = hw_by_addr(addr);
325
326 if (hw != NULL) {
327 return hw->read(hw_off(hw, addr), 4);
328 }
329
330 if (addr <= APP_START - 4) {
331 return
332 ((uint32_t)ram_data[addr + 0] << 24) |
333 ((uint32_t)ram_data[addr + 1] << 16) |
334 ((uint32_t)ram_data[addr + 2] << 8) |
335 ((uint32_t)ram_data[addr + 3] << 0);
336 }
337
338 fail("invalid read 0x%08x:32", addr);
339}
340
341void m68k_write_memory_8(uint32_t addr, uint32_t val)
342{
343 ver("mem wr 0x%08x:8 0x%02x", addr, val);
344
345 if (addr >= ram_rw_beg && addr <= ram_rw_end - 1) {
346 ram_data[addr - RAM_START] = (uint8_t)val;
347 return;
348 }
349
350 if (addr >= rom_rw_beg && addr <= rom_rw_end - 1) {
351 // ROM has its BSS section in RAM.
352 ram_data[addr - RAM_START] = (uint8_t)val;
353 return;
354 }
355
356 hw_t *hw = hw_by_addr(addr);
357
358 if (hw != NULL) {
359 hw->write(hw_off(hw, addr), 1, val);
360 return;
361 }
362
363 if (addr <= APP_START - 1) {
364 ram_data[addr] = (uint8_t)val;
365 return;
366 }
367
368 fail("invalid write 0x%08x:8 0x%02x", addr, val);
369}
370
371void m68k_write_memory_16(uint32_t addr, uint32_t val)
372{
373 ver("mem wr 0x%08x:16 0x%04x", addr, val);
374
375 if (addr >= ram_rw_beg && addr <= ram_rw_end - 2) {
376 ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 8);
377 ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 0);
378 return;
379 }
380
381 if (addr >= rom_rw_beg && addr <= rom_rw_end - 2) {
382 // ROM has its BSS section in RAM.
383 ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 8);
384 ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 0);
385 return;
386 }
387
388 hw_t *hw = hw_by_addr(addr);
389
390 if (hw != NULL) {
391 hw->write(hw_off(hw, addr), 2, val);
392 return;
393 }
394
395 if (addr <= APP_START - 2) {
396 ram_data[addr + 0] = (uint8_t)(val >> 8);
397 ram_data[addr + 1] = (uint8_t)(val >> 0);
398 return;
399 }
400
401 fail("invalid write 0x%08x:16 0x%04x", addr, val);
402}
403
404void m68k_write_memory_32(uint32_t addr, uint32_t val)
405{
406 ver("mem wr 0x%08x:32 0x%08x", addr, val);
407
408 if (addr >= ram_rw_beg && addr <= ram_rw_end - 4) {
409 ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 24);
410 ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 16);
411 ram_data[addr - RAM_START + 2] = (uint8_t)(val >> 8);
412 ram_data[addr - RAM_START + 3] = (uint8_t)(val >> 0);
413 return;
414 }
415
416 if (addr >= rom_rw_beg && addr <= rom_rw_end - 4) {
417 // ROM has its BSS section in RAM.
418 ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 24);
419 ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 16);
420 ram_data[addr - RAM_START + 2] = (uint8_t)(val >> 8);
421 ram_data[addr - RAM_START + 3] = (uint8_t)(val >> 0);
422 return;
423 }
424
425 hw_t *hw = hw_by_addr(addr);
426
427 if (hw != NULL) {
428 hw->write(hw_off(hw, addr), 4, val);
429 return;
430 }
431
432 if (addr <= APP_START - 4) {
433 ram_data[addr + 0] = (uint8_t)(val >> 24);
434 ram_data[addr + 1] = (uint8_t)(val >> 16);
435 ram_data[addr + 2] = (uint8_t)(val >> 8);
436 ram_data[addr + 3] = (uint8_t)(val >> 0);
437 return;
438 }
439
440 fail("invalid write 0x%08x:32 0x%08x", addr, val);
441}
442
443void cpu_loop(const char *bios)
444{
445 hw_init();
446 bios_init(bios);
447
448 inf("entering CPU loop");
449 m68k_init();
450 m68k_set_cpu_type(M68K_CPU_TYPE_68000);
451 m68k_pulse_reset();
452
453 uint64_t freq = SDL_GetPerformanceFrequency();
454 uint64_t quan = freq / PER_SEC;
455 inf("freq %" PRIu64 " quan %" PRIu64, freq, quan);
456
457 bool run = true;
458
459 while (run) {
460 uint64_t until = SDL_GetPerformanceCounter() + quan;
461
462 m68k_execute(CPU_FREQ / PER_SEC);
463 hw_exec();
464
465 SDL_Event ev;
466
467 while (SDL_PollEvent(&ev) > 0) {
468 if (ev.type == SDL_QUIT) {
469 run = false;
470 }
471 }
472
473 while (SDL_GetPerformanceCounter() < until) {
474 _mm_pause();
475 }
476 }
477
478 inf("leaving CPU loop");
479}
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