[a06aa8b] | 1 | /*
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| 2 | * Copyright (C) 2017 The Contributors
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| 3 | *
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| 4 | * This program is free software: you can redistribute it and/or modify
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| 5 | * it under the terms of the GNU General Public License as published by
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| 6 | * the Free Software Foundation, either version 3 of the License, or (at
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| 7 | * your option) any later version.
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| 8 | *
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| 9 | * This program is distributed in the hope that it will be useful, but
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| 10 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 12 | * General Public License for more details.
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| 13 | *
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| 14 | * A copy of the GNU General Public License can be found in the file
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[2147e53] | 15 | * "gpl.txt" in the top directory of this repository.
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[a06aa8b] | 16 | */
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| 17 |
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| 18 | #include <all.h>
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| 19 |
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[4c71d39] | 20 | #define ver(...) _ver(fdd_verbose, 0, __VA_ARGS__)
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| 21 | #define ver2(...) _ver(fdd_verbose, 1, __VA_ARGS__)
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| 22 | #define ver3(...) _ver(fdd_verbose, 2, __VA_ARGS__)
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[a06aa8b] | 23 |
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[4c71d39] | 24 | int32_t fdd_verbose = 0;
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[a06aa8b] | 25 |
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[1efc42c] | 26 | #define N_CYL 80
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| 27 | #define N_SID 2
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[c5b6c90] | 28 | #define N_SEC 9
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[1efc42c] | 29 | #define SZ_SEC 512
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| 30 |
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| 31 | #define SZ_DISK (N_CYL * N_SID * N_SEC * SZ_SEC)
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| 32 |
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[c5b6c90] | 33 | #define REG_COM_STAT 0
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| 34 | #define REG_TRA 1
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| 35 | #define REG_SEC 2
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| 36 | #define REG_DAT 3
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| 37 |
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| 38 | #define COM_REST 0x00
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| 39 | #define COM_SEEK 0x10
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| 40 | #define COM_SEEK_VER 0x14
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| 41 | #define COM_RD_SEC 0x80
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| 42 | #define COM_RD_SEC_MUL 0x90
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| 43 | #define COM_WR_SEC_WP 0xa0
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| 44 | #define COM_WR_SEC 0xa2
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| 45 | #define COM_INT 0xd0
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[9b204fa] | 46 | #define COM_WR_TRA_WP 0xf0
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| 47 | #define COM_WR_TRA 0xf2
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[c5b6c90] | 48 |
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[1489228] | 49 | #define COM_LAT_CYC 5
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| 50 | #define COM_EXE_CYC 5
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[c5b6c90] | 51 |
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| 52 | typedef enum {
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| 53 | STEP_IDLE,
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| 54 | STEP_PREP,
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| 55 | STEP_EXEC
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| 56 | } step_t;
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| 57 |
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| 58 | typedef struct {
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| 59 | int32_t reg_tra;
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| 60 | int32_t reg_sec;
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| 61 | int32_t reg_dat;
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| 62 | int32_t sid;
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| 63 | step_t step;
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| 64 | int32_t com;
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| 65 | int32_t cyc;
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| 66 | uint8_t *dat;
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| 67 | bool tra_0;
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| 68 | } state_t;
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| 69 |
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| 70 | static state_t state = {
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| 71 | .reg_tra = 0, .reg_sec = 0, .reg_dat = 0, .sid = 0,
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| 72 | .step = STEP_IDLE, .com = -1, .cyc = 0, .dat = NULL, .tra_0 = false
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| 73 | };
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| 74 |
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[1efc42c] | 75 | static uint8_t image[SZ_DISK];
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| 76 |
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[c5b6c90] | 77 | static const char *com_string(int32_t com)
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| 78 | {
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| 79 | switch (com) {
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| 80 | case COM_REST:
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| 81 | return "COM_REST";
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| 82 |
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| 83 | case COM_SEEK:
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| 84 | return "COM_SEEK";
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| 85 |
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| 86 | case COM_SEEK_VER:
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| 87 | return "COM_SEEK_VER";
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| 88 |
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| 89 | case COM_RD_SEC:
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| 90 | return "COM_RD_SEC";
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| 91 |
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| 92 | case COM_RD_SEC_MUL:
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| 93 | return "COM_RD_SEC_MUL";
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| 94 |
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| 95 | case COM_WR_SEC_WP:
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| 96 | return "COM_WR_SEC_WP";
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| 97 |
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| 98 | case COM_WR_SEC:
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| 99 | return "COM_WR_SEC";
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| 100 |
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[9b204fa] | 101 | case COM_WR_TRA_WP:
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| 102 | return "COM_WR_TRA_WP";
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| 103 |
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[c5b6c90] | 104 | case COM_WR_TRA:
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| 105 | return "COM_WR_TRA";
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| 106 |
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| 107 | default:
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| 108 | fail("unknown command 0x%02x", com);
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| 109 | }
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| 110 | }
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| 111 |
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| 112 | static void stat_string(int32_t stat, char *buff) {
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| 113 | buff[0] = 0;
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| 114 |
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| 115 | if ((stat & 0x80) != 0) {
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| 116 | strcat(buff, " mot_on");
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| 117 | }
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| 118 |
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| 119 | if ((stat & 0x04) != 0) {
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| 120 | strcat(buff, " zero");
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| 121 | }
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| 122 |
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| 123 | if ((stat & 0x02) != 0) {
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| 124 | strcat(buff, " dat_req");
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| 125 | }
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| 126 |
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| 127 | if ((stat & 0x01) != 0) {
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| 128 | strcat(buff, " busy");
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| 129 | }
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| 130 | }
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| 131 |
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| 132 | void fdd_set_side(int32_t sid)
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| 133 | {
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| 134 | ver2("sid <- %d", sid);
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| 135 | state.sid = sid;
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| 136 | }
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| 137 |
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| 138 | void fdd_set_sel(int32_t sel)
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| 139 | {
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| 140 | ver2("sel <- %d", sel);
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| 141 | }
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| 142 |
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[a06aa8b] | 143 | void fdd_init(void)
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| 144 | {
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| 145 | ver("fdd init");
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[9b204fa] | 146 | inf("reading disk image file %s", disk);
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[1efc42c] | 147 |
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| 148 | SDL_RWops *ops = SDL_RWFromFile(disk, "rb");
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| 149 |
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| 150 | if (ops == NULL) {
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[9b204fa] | 151 | fail("error while opening disk image file %s for reading", disk);
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[1efc42c] | 152 | }
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| 153 |
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| 154 | size_t loaded = 0;
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| 155 |
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| 156 | while (loaded < SZ_DISK) {
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| 157 | size_t n_rd = SDL_RWread(ops, image + loaded, 1, SZ_DISK - loaded);
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| 158 |
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| 159 | if (n_rd == 0) {
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| 160 | fail("error while reading disk image file %s", disk);
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| 161 | }
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| 162 |
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| 163 | loaded += n_rd;
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| 164 | }
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| 165 |
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| 166 | SDL_RWclose(ops);
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[a06aa8b] | 167 | }
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| 168 |
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| 169 | void fdd_quit(void)
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| 170 | {
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| 171 | ver("fdd quit");
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[9b204fa] | 172 | inf("writing disk image file %s", disk);
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| 173 |
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| 174 | SDL_RWops *ops = SDL_RWFromFile(disk, "wb");
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| 175 |
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| 176 | if (ops == NULL) {
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| 177 | fail("error while opening disk image file %s for writing", disk);
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| 178 | }
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| 179 |
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| 180 | size_t stored = 0;
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| 181 |
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| 182 | while (stored < SZ_DISK) {
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| 183 | size_t n_wr = SDL_RWwrite(ops, image + stored, 1, SZ_DISK - stored);
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| 184 |
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| 185 | if (n_wr == 0) {
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| 186 | fail("error while writing disk image file %s", disk);
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| 187 | }
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| 188 |
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| 189 | stored += n_wr;
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| 190 | }
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| 191 |
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| 192 | SDL_RWclose(ops);
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[a06aa8b] | 193 | }
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| 194 |
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[3c30832] | 195 | bool fdd_exec(void)
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[a06aa8b] | 196 | {
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[4c71d39] | 197 | ver3("fdd exec");
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[c5b6c90] | 198 |
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| 199 | switch (state.step) {
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| 200 | case STEP_IDLE:
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| 201 | break;
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| 202 |
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| 203 | case STEP_PREP:
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| 204 | ver3("prep %d", state.cyc);
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| 205 | --state.cyc;
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| 206 |
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| 207 | if (state.cyc == 0) {
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| 208 | ver2("exec %s", com_string(state.com));
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| 209 | state.step = STEP_EXEC;
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| 210 | state.cyc = COM_EXE_CYC;
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| 211 | }
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| 212 |
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| 213 | break;
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| 214 |
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| 215 | case STEP_EXEC:
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| 216 | ver3("exec %d", state.cyc);
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| 217 | --state.cyc;
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| 218 |
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| 219 | if (state.cyc == 0) {
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| 220 | ver2("idle %s", com_string(state.com));
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| 221 | state.step = STEP_IDLE;
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| 222 | }
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| 223 |
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| 224 | break;
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| 225 | }
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| 226 |
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[3c30832] | 227 | return false;
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[a06aa8b] | 228 | }
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| 229 |
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| 230 | uint32_t fdd_read(uint32_t off, int32_t sz)
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| 231 | {
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[c5b6c90] | 232 | ver3("fdd rd %u:%d", off, sz * 8);
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| 233 |
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| 234 | if (sz != 1 || off > 3) {
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| 235 | fail("invalid fdd rd %u:%d", off, sz * 8);
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| 236 | }
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| 237 |
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| 238 | uint32_t rv;
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| 239 |
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| 240 | switch (off) {
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| 241 | case REG_COM_STAT:
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| 242 | rv = 0x80; // motor on
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| 243 |
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| 244 | if (state.step == STEP_EXEC) {
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| 245 | rv |= 0x01; // busy
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| 246 |
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| 247 | switch (state.com) {
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| 248 | case COM_RD_SEC:
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| 249 | case COM_RD_SEC_MUL:
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| 250 | case COM_WR_SEC:
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| 251 | case COM_WR_SEC_WP:
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| 252 | rv |= 0x02; // data request
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| 253 | break;
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| 254 | }
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| 255 | }
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| 256 |
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| 257 | if (state.tra_0) {
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| 258 | rv |= 0x04; // track zero
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| 259 | }
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| 260 |
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| 261 | char stat[100];
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| 262 | stat_string((int32_t)rv, stat);
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| 263 | ver3("stat -> 0x%02x%s", rv, stat);
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| 264 | break;
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| 265 |
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| 266 | case REG_TRA:
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| 267 | rv = (uint32_t)state.reg_tra;
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| 268 | ver2("tra -> %u", rv);
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| 269 | break;
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| 270 |
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| 271 | case REG_SEC:
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| 272 | rv = (uint32_t)state.reg_sec;
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| 273 | ver2("sec -> %u", rv);
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| 274 | break;
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| 275 |
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| 276 | case REG_DAT:
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| 277 | if (state.step != STEP_EXEC ||
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| 278 | (state.com != COM_RD_SEC && state.com != COM_RD_SEC_MUL)) {
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| 279 | fail("unexpected data register read");
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| 280 | }
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| 281 |
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| 282 | rv = *state.dat;
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[1489228] | 283 | int32_t addr = (int32_t)(state.dat - image);
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[c5b6c90] | 284 |
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| 285 | if ((addr & (SZ_SEC - 1)) == 0) {
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[1489228] | 286 | ver2("addr 0x%06x -> 0x%02x", addr, rv);
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[c5b6c90] | 287 | }
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| 288 | else {
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[1489228] | 289 | ver3("addr 0x%06x -> 0x%02x", addr, rv);
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[c5b6c90] | 290 | }
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| 291 |
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| 292 | ++state.dat;
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[1489228] | 293 | ++addr;
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| 294 |
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| 295 | if ((addr & (SZ_SEC - 1)) == 0 && state.com == COM_RD_SEC) {
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| 296 | state.step = STEP_IDLE;
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| 297 | state.cyc = 0;
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| 298 | }
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| 299 | else {
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| 300 | state.cyc = COM_EXE_CYC;
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| 301 | }
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| 302 |
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[c5b6c90] | 303 | break;
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| 304 |
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| 305 | default:
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| 306 | rv = 0;
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| 307 | break;
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| 308 | }
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| 309 |
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| 310 | return rv;
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[a06aa8b] | 311 | }
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| 312 |
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| 313 | void fdd_write(uint32_t off, int32_t sz, uint32_t val)
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| 314 | {
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[c5b6c90] | 315 | ver3("fdd wr %u:%d 0x%0*x", off, sz * 8, sz * 2, val);
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| 316 |
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| 317 | if (sz != 1 || off > 3) {
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| 318 | fail("invalid fdd wr %u:%d", off, sz * 8);
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| 319 | }
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| 320 |
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| 321 | switch (off) {
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| 322 | case REG_COM_STAT:
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| 323 | ver2("com <- 0x%02x, tra %d, sid %d, sec %d",
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| 324 | val, state.reg_tra, state.sid, state.reg_sec);
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| 325 |
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| 326 | state.com = (int32_t)val;
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| 327 |
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| 328 | ver2("prep %s", com_string(state.com));
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| 329 | state.step = STEP_PREP;
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| 330 | state.cyc = COM_LAT_CYC;
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| 331 |
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| 332 | switch (val) {
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| 333 | case COM_REST:
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| 334 | state.reg_tra = 0;
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| 335 | state.tra_0 = true;
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[8967dbc] | 336 | state.dat = NULL;
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[c5b6c90] | 337 | break;
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| 338 |
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| 339 | case COM_SEEK:
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| 340 | case COM_SEEK_VER:
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| 341 | state.reg_tra = state.reg_dat;
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| 342 | state.tra_0 = state.reg_tra == 0;
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[8967dbc] | 343 | state.dat = NULL;
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[c5b6c90] | 344 | break;
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| 345 |
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| 346 | case COM_RD_SEC:
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| 347 | case COM_RD_SEC_MUL:
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| 348 | case COM_WR_SEC:
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| 349 | case COM_WR_SEC_WP: {
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| 350 | size_t sec_off = (size_t)(((state.reg_tra * N_SID + state.sid) * N_SEC +
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| 351 | state.reg_sec - 1) * SZ_SEC);
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| 352 | state.dat = image + sec_off;
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| 353 | state.tra_0 = false;
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| 354 | break;
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| 355 | }
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| 356 |
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| 357 | case COM_INT:
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| 358 | state.step = STEP_IDLE;
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| 359 | state.cyc = 0;
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| 360 | state.dat = NULL;
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| 361 | state.tra_0 = false;
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| 362 | break;
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| 363 |
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| 364 | case COM_WR_TRA:
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[9b204fa] | 365 | case COM_WR_TRA_WP:
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[c5b6c90] | 366 | state.tra_0 = false;
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| 367 | fail("format not yet supported");
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| 368 | break;
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| 369 | }
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| 370 |
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| 371 | break;
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| 372 |
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| 373 | case REG_TRA:
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| 374 | state.reg_tra = (int32_t)val;
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| 375 | ver2("tra <- %u", val);
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| 376 | break;
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| 377 |
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| 378 | case REG_SEC:
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| 379 | state.reg_sec = (int32_t)val;
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| 380 | ver2("sec <- %u", val);
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| 381 | break;
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| 382 |
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| 383 | case REG_DAT:
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| 384 | if (state.step == STEP_EXEC &&
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| 385 | (state.com == COM_WR_SEC || state.com == COM_WR_SEC_WP)) {
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| 386 | *state.dat = (uint8_t)val;
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[1489228] | 387 | int32_t addr = (int32_t)(state.dat - image);
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[c5b6c90] | 388 |
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| 389 | if ((addr & (SZ_SEC - 1)) == 0) {
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[1489228] | 390 | ver2("addr 0x%06x <- 0x%02x", addr, val);
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[c5b6c90] | 391 | }
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| 392 | else {
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[1489228] | 393 | ver3("addr 0x%06x <- 0x%02x", addr, val);
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[c5b6c90] | 394 | }
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| 395 |
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| 396 | ++state.dat;
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[1489228] | 397 | ++addr;
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| 398 |
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| 399 | if ((addr & (SZ_SEC - 1)) == 0) {
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| 400 | state.step = STEP_IDLE;
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| 401 | state.cyc = 0;
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| 402 | }
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| 403 | else {
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| 404 | state.cyc = COM_EXE_CYC;
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| 405 | }
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[c5b6c90] | 406 | }
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| 407 | else {
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| 408 | state.reg_dat = (int32_t)val;
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| 409 | ver2("dat <- 0x%02x", val);
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| 410 | }
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| 411 |
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| 412 | break;
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| 413 |
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| 414 | default:
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| 415 | break;
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| 416 | }
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[a06aa8b] | 417 | }
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