source: buchla-emu/emu/fdd.c@ 08471db

Last change on this file since 08471db was 8967dbc, checked in by Thomas Lopatic <thomas@…>, 7 years ago

Minor cleanup.
  • Property mode set to 100644
File size: 6.8 KB
Line 
1/*
2 * Copyright (C) 2017 The Contributors
3 *
4 * This program is free software: you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation, either version 3 of the License, or (at
7 * your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
13 *
14 * A copy of the GNU General Public License can be found in the file
15 * "gpl.txt" in the top directory of this repository.
16 */
17
18#include <all.h>
19
20#define ver(...) _ver(fdd_verbose, 0, __VA_ARGS__)
21#define ver2(...) _ver(fdd_verbose, 1, __VA_ARGS__)
22#define ver3(...) _ver(fdd_verbose, 2, __VA_ARGS__)
23
24int32_t fdd_verbose = 0;
25
26#define N_CYL 80
27#define N_SID 2
28#define N_SEC 9
29#define SZ_SEC 512
30
31#define SZ_DISK (N_CYL * N_SID * N_SEC * SZ_SEC)
32
33#define REG_COM_STAT 0
34#define REG_TRA 1
35#define REG_SEC 2
36#define REG_DAT 3
37
38#define COM_REST 0x00
39#define COM_SEEK 0x10
40#define COM_SEEK_VER 0x14
41#define COM_RD_SEC 0x80
42#define COM_RD_SEC_MUL 0x90
43#define COM_WR_SEC_WP 0xa0
44#define COM_WR_SEC 0xa2
45#define COM_INT 0xd0
46#define COM_WR_TRA 0xf0
47
48#define COM_LAT_CYC 5
49#define COM_EXE_CYC 5
50
51typedef enum {
52 STEP_IDLE,
53 STEP_PREP,
54 STEP_EXEC
55} step_t;
56
57typedef struct {
58 int32_t reg_tra;
59 int32_t reg_sec;
60 int32_t reg_dat;
61 int32_t sid;
62 step_t step;
63 int32_t com;
64 int32_t cyc;
65 uint8_t *dat;
66 bool tra_0;
67} state_t;
68
69static state_t state = {
70 .reg_tra = 0, .reg_sec = 0, .reg_dat = 0, .sid = 0,
71 .step = STEP_IDLE, .com = -1, .cyc = 0, .dat = NULL, .tra_0 = false
72};
73
74static uint8_t image[SZ_DISK];
75
76static const char *com_string(int32_t com)
77{
78 switch (com) {
79 case COM_REST:
80 return "COM_REST";
81
82 case COM_SEEK:
83 return "COM_SEEK";
84
85 case COM_SEEK_VER:
86 return "COM_SEEK_VER";
87
88 case COM_RD_SEC:
89 return "COM_RD_SEC";
90
91 case COM_RD_SEC_MUL:
92 return "COM_RD_SEC_MUL";
93
94 case COM_WR_SEC_WP:
95 return "COM_WR_SEC_WP";
96
97 case COM_WR_SEC:
98 return "COM_WR_SEC";
99
100 case COM_WR_TRA:
101 return "COM_WR_TRA";
102
103 default:
104 fail("unknown command 0x%02x", com);
105 }
106}
107
108static void stat_string(int32_t stat, char *buff) {
109 buff[0] = 0;
110
111 if ((stat & 0x80) != 0) {
112 strcat(buff, " mot_on");
113 }
114
115 if ((stat & 0x04) != 0) {
116 strcat(buff, " zero");
117 }
118
119 if ((stat & 0x02) != 0) {
120 strcat(buff, " dat_req");
121 }
122
123 if ((stat & 0x01) != 0) {
124 strcat(buff, " busy");
125 }
126}
127
128void fdd_set_side(int32_t sid)
129{
130 ver2("sid <- %d", sid);
131 state.sid = sid;
132}
133
134void fdd_set_sel(int32_t sel)
135{
136 ver2("sel <- %d", sel);
137}
138
139void fdd_init(void)
140{
141 ver("fdd init");
142 inf("loading disk image file %s", disk);
143
144 SDL_RWops *ops = SDL_RWFromFile(disk, "rb");
145
146 if (ops == NULL) {
147 fail("error while opening disk image file %s", disk);
148 }
149
150 size_t loaded = 0;
151
152 while (loaded < SZ_DISK) {
153 size_t n_rd = SDL_RWread(ops, image + loaded, 1, SZ_DISK - loaded);
154
155 if (n_rd == 0) {
156 fail("error while reading disk image file %s", disk);
157 }
158
159 loaded += n_rd;
160 }
161
162 SDL_RWclose(ops);
163}
164
165void fdd_quit(void)
166{
167 ver("fdd quit");
168}
169
170bool fdd_exec(void)
171{
172 ver3("fdd exec");
173
174 switch (state.step) {
175 case STEP_IDLE:
176 break;
177
178 case STEP_PREP:
179 ver3("prep %d", state.cyc);
180 --state.cyc;
181
182 if (state.cyc == 0) {
183 ver2("exec %s", com_string(state.com));
184 state.step = STEP_EXEC;
185 state.cyc = COM_EXE_CYC;
186 }
187
188 break;
189
190 case STEP_EXEC:
191 ver3("exec %d", state.cyc);
192 --state.cyc;
193
194 if (state.cyc == 0) {
195 ver2("idle %s", com_string(state.com));
196 state.step = STEP_IDLE;
197 }
198
199 break;
200 }
201
202 return false;
203}
204
205uint32_t fdd_read(uint32_t off, int32_t sz)
206{
207 ver3("fdd rd %u:%d", off, sz * 8);
208
209 if (sz != 1 || off > 3) {
210 fail("invalid fdd rd %u:%d", off, sz * 8);
211 }
212
213 uint32_t rv;
214
215 switch (off) {
216 case REG_COM_STAT:
217 rv = 0x80; // motor on
218
219 if (state.step == STEP_EXEC) {
220 rv |= 0x01; // busy
221
222 switch (state.com) {
223 case COM_RD_SEC:
224 case COM_RD_SEC_MUL:
225 case COM_WR_SEC:
226 case COM_WR_SEC_WP:
227 rv |= 0x02; // data request
228 break;
229 }
230 }
231
232 if (state.tra_0) {
233 rv |= 0x04; // track zero
234 }
235
236 char stat[100];
237 stat_string((int32_t)rv, stat);
238 ver3("stat -> 0x%02x%s", rv, stat);
239 break;
240
241 case REG_TRA:
242 rv = (uint32_t)state.reg_tra;
243 ver2("tra -> %u", rv);
244 break;
245
246 case REG_SEC:
247 rv = (uint32_t)state.reg_sec;
248 ver2("sec -> %u", rv);
249 break;
250
251 case REG_DAT:
252 if (state.step != STEP_EXEC ||
253 (state.com != COM_RD_SEC && state.com != COM_RD_SEC_MUL)) {
254 fail("unexpected data register read");
255 }
256
257 rv = *state.dat;
258 int32_t addr = (int32_t)(state.dat - image);
259
260 if ((addr & (SZ_SEC - 1)) == 0) {
261 ver2("addr 0x%06x -> 0x%02x", addr, rv);
262 }
263 else {
264 ver3("addr 0x%06x -> 0x%02x", addr, rv);
265 }
266
267 ++state.dat;
268 ++addr;
269
270 if ((addr & (SZ_SEC - 1)) == 0 && state.com == COM_RD_SEC) {
271 state.step = STEP_IDLE;
272 state.cyc = 0;
273 }
274 else {
275 state.cyc = COM_EXE_CYC;
276 }
277
278 break;
279
280 default:
281 rv = 0;
282 break;
283 }
284
285 return rv;
286}
287
288void fdd_write(uint32_t off, int32_t sz, uint32_t val)
289{
290 ver3("fdd wr %u:%d 0x%0*x", off, sz * 8, sz * 2, val);
291
292 if (sz != 1 || off > 3) {
293 fail("invalid fdd wr %u:%d", off, sz * 8);
294 }
295
296 switch (off) {
297 case REG_COM_STAT:
298 ver2("com <- 0x%02x, tra %d, sid %d, sec %d",
299 val, state.reg_tra, state.sid, state.reg_sec);
300
301 state.com = (int32_t)val;
302
303 ver2("prep %s", com_string(state.com));
304 state.step = STEP_PREP;
305 state.cyc = COM_LAT_CYC;
306
307 switch (val) {
308 case COM_REST:
309 state.reg_tra = 0;
310 state.tra_0 = true;
311 state.dat = NULL;
312 break;
313
314 case COM_SEEK:
315 case COM_SEEK_VER:
316 state.reg_tra = state.reg_dat;
317 state.tra_0 = state.reg_tra == 0;
318 state.dat = NULL;
319 break;
320
321 case COM_RD_SEC:
322 case COM_RD_SEC_MUL:
323 case COM_WR_SEC:
324 case COM_WR_SEC_WP: {
325 size_t sec_off = (size_t)(((state.reg_tra * N_SID + state.sid) * N_SEC +
326 state.reg_sec - 1) * SZ_SEC);
327 state.dat = image + sec_off;
328 state.tra_0 = false;
329 break;
330 }
331
332 case COM_INT:
333 state.step = STEP_IDLE;
334 state.cyc = 0;
335 state.dat = NULL;
336 state.tra_0 = false;
337 break;
338
339 case COM_WR_TRA:
340 state.tra_0 = false;
341 fail("format not yet supported");
342 break;
343 }
344
345 break;
346
347 case REG_TRA:
348 state.reg_tra = (int32_t)val;
349 ver2("tra <- %u", val);
350 break;
351
352 case REG_SEC:
353 state.reg_sec = (int32_t)val;
354 ver2("sec <- %u", val);
355 break;
356
357 case REG_DAT:
358 if (state.step == STEP_EXEC &&
359 (state.com == COM_WR_SEC || state.com == COM_WR_SEC_WP)) {
360 *state.dat = (uint8_t)val;
361 int32_t addr = (int32_t)(state.dat - image);
362
363 if ((addr & (SZ_SEC - 1)) == 0) {
364 ver2("addr 0x%06x <- 0x%02x", addr, val);
365 }
366 else {
367 ver3("addr 0x%06x <- 0x%02x", addr, val);
368 }
369
370 ++state.dat;
371 ++addr;
372
373 if ((addr & (SZ_SEC - 1)) == 0) {
374 state.step = STEP_IDLE;
375 state.cyc = 0;
376 }
377 else {
378 state.cyc = COM_EXE_CYC;
379 }
380 }
381 else {
382 state.reg_dat = (int32_t)val;
383 ver2("dat <- 0x%02x", val);
384 }
385
386 break;
387
388 default:
389 break;
390 }
391}
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