[a06aa8b] | 1 | /*
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| 2 | * Copyright (C) 2017 The Contributors
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| 3 | *
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| 4 | * This program is free software: you can redistribute it and/or modify
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| 5 | * it under the terms of the GNU General Public License as published by
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| 6 | * the Free Software Foundation, either version 3 of the License, or (at
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| 7 | * your option) any later version.
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| 8 | *
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| 9 | * This program is distributed in the hope that it will be useful, but
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| 10 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 12 | * General Public License for more details.
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| 13 | *
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| 14 | * A copy of the GNU General Public License can be found in the file
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[2147e53] | 15 | * "gpl.txt" in the top directory of this repository.
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[a06aa8b] | 16 | */
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| 17 |
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| 18 | #include <all.h>
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| 19 |
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[4c71d39] | 20 | #define ver(...) _ver(tim_verbose, 0, __VA_ARGS__)
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| 21 | #define ver2(...) _ver(tim_verbose, 1, __VA_ARGS__)
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| 22 | #define ver3(...) _ver(tim_verbose, 2, __VA_ARGS__)
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[a06aa8b] | 23 |
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[9e0cd12] | 24 | int32_t tim_verbose = 0;
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[212bc4c] | 25 |
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| 26 | #define REG_CRX 0
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[40b2112] | 27 | #define REG_CR2_SR 1
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[212bc4c] | 28 | #define REG_T1H 2
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| 29 | #define REG_T1L 3
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| 30 | #define REG_T2H 4
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| 31 | #define REG_T2L 5
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| 32 | #define REG_T3H 6
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| 33 | #define REG_T3L 7
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| 34 |
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[9e0cd12] | 35 | #define COUNT_1 32
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| 36 | #define COUNT_2 3200
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| 37 | #define COUNT_3 801
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| 38 |
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| 39 | typedef struct {
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| 40 | bool irq_e;
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| 41 | bool irq;
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| 42 | int32_t latch;
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| 43 | int32_t count;
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| 44 | } state_timer;
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| 45 |
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| 46 | static state_timer timers[] = {
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| 47 | { .irq_e = false, .irq = false, .latch = COUNT_1, .count = COUNT_1 },
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| 48 | { .irq_e = false, .irq = false, .latch = COUNT_2, .count = COUNT_2 },
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| 49 | { .irq_e = false, .irq = false, .latch = COUNT_3, .count = COUNT_3 }
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| 50 | };
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| 51 |
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| 52 | static bool wr_cr1 = false;
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| 53 | static bool oper = false;
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[a06aa8b] | 54 |
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| 55 | void tim_init(void)
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| 56 | {
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| 57 | ver("tim init");
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| 58 | }
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| 59 |
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| 60 | void tim_quit(void)
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| 61 | {
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| 62 | ver("tim quit");
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| 63 | }
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| 64 |
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[3c30832] | 65 | bool tim_exec(void)
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[a06aa8b] | 66 | {
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[9e0cd12] | 67 | if (oper) {
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| 68 | for (int32_t i = 0; i < ARRAY_COUNT(timers); ++i) {
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[212bc4c] | 69 | --timers[i].count;
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[9e0cd12] | 70 |
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| 71 | if (timers[i].count == 0) {
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| 72 | ver2("tim %d zero", i + 1);
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[212bc4c] | 73 | timers[i].count = timers[i].latch;
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[9e0cd12] | 74 |
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| 75 | if (timers[i].irq_e) {
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| 76 | ver2("tim %d irq", i + 1);
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| 77 | timers[i].irq = true;
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| 78 | }
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[212bc4c] | 79 | }
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| 80 | }
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| 81 | }
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[52c8401] | 82 |
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[212bc4c] | 83 | return timers[0].irq || timers[1].irq || timers[2].irq;
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[a06aa8b] | 84 | }
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| 85 |
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| 86 | uint32_t tim_read(uint32_t off, int32_t sz)
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| 87 | {
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[4c71d39] | 88 | ver2("tim rd %u:%d", off, sz * 8);
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[52c8401] | 89 |
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[9e0cd12] | 90 | if (sz != 1 || off > 7) {
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| 91 | fail("invalid tim rd %u:%d", off, sz * 8);
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| 92 | }
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| 93 |
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| 94 | uint32_t rv = 0x00;
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| 95 |
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| 96 | switch (off) {
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[40b2112] | 97 | case REG_CR2_SR:
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[9e0cd12] | 98 | rv |= (uint32_t)timers[0].irq << 0;
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| 99 | rv |= (uint32_t)timers[1].irq << 1;
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| 100 | rv |= (uint32_t)timers[2].irq << 2;
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[52c8401] | 101 |
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[9e0cd12] | 102 | ver2("tim irqs %u %u %u",
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| 103 | (uint32_t)timers[0].irq, (uint32_t)timers[1].irq, (uint32_t)timers[2].irq);
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[212bc4c] | 104 | break;
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[52c8401] | 105 |
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[212bc4c] | 106 | case REG_T1L:
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[9e0cd12] | 107 | if (timers[0].irq) {
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| 108 | ver2("tim 1 !irq");
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| 109 | timers[0].irq = false;
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| 110 | }
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[52c8401] | 111 |
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[212bc4c] | 112 | break;
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[52c8401] | 113 |
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[212bc4c] | 114 | case REG_T2L:
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[9e0cd12] | 115 | if (timers[1].irq) {
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| 116 | ver2("tim 2 !irq");
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| 117 | timers[1].irq = false;
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| 118 | }
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[52c8401] | 119 |
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[212bc4c] | 120 | break;
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[52c8401] | 121 |
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[212bc4c] | 122 | case REG_T3L:
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[9e0cd12] | 123 | if (timers[2].irq) {
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| 124 | ver2("tim 3 !irq");
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| 125 | timers[2].irq = false;
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| 126 | }
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| 127 |
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[212bc4c] | 128 | break;
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[52c8401] | 129 |
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[212bc4c] | 130 | default:
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| 131 | break;
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| 132 | }
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[52c8401] | 133 |
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[212bc4c] | 134 | return rv;
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[a06aa8b] | 135 | }
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| 136 |
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| 137 | void tim_write(uint32_t off, int32_t sz, uint32_t val)
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| 138 | {
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[4c71d39] | 139 | ver2("tim wr %u:%d 0x%0*x", off, sz * 8, sz * 2, val);
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[9e0cd12] | 140 |
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| 141 | if (sz != 1 || off > 7) {
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| 142 | fail("invalid tim wr %u:%d", off, sz * 8);
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| 143 | }
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| 144 |
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| 145 | switch (off) {
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| 146 | case REG_CRX:
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| 147 | if (wr_cr1) {
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| 148 | if ((val & 0x01) == 0) {
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| 149 | ver2("tim start");
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| 150 | oper = true;
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| 151 | }
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| 152 |
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| 153 | timers[0].irq_e = (val & 0x40) != 0;
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| 154 | }
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| 155 | else {
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| 156 | timers[2].irq_e = (val & 0x40) != 0;
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| 157 | }
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| 158 |
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| 159 | break;
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| 160 |
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[40b2112] | 161 | case REG_CR2_SR:
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[9e0cd12] | 162 | wr_cr1 = (val & 0x01) != 0;
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| 163 | timers[1].irq_e = (val & 0x40) != 0;
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| 164 | break;
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| 165 |
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| 166 | default:
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| 167 | break;
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[212bc4c] | 168 | }
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[a06aa8b] | 169 | }
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