Changeset a06aa8b in buchla-emu


Ignore:
Timestamp:
07/20/2017 02:34:09 PM (5 years ago)
Author:
Thomas Lopatic <thomas@…>
Branches:
master
Children:
b909777
Parents:
f996387
Message:

Added skeleton device files.

Files:
10 added
6 edited

Legend:

Unmodified
Added
Removed
  • Makefile

    rf996387 ra06aa8b  
    6969                                gcc $(FLAGS_CPU) -c -o $@ $<
    7070
    71 EMU_C :=                main.c cpu.c sdl.c
     71EMU_C :=                main.c cpu.c vid.c fpu.c tim.c lcd.c ser.c mid.c fdd.c snd.c \
     72                                led.c kbd.c sdl.c
    7273EMU_O :=                $(EMU_C:.c=.o)
    7374EMU_OP :=               $(EMU_O:%=build/%)
  • copying.txt

    rf996387 ra06aa8b  
    44(Applicable to the source code in the "emu" subdirectory.)
    55
    6 Copyright (C) 2017 The Emulator Developers
     6Copyright (C) 2017 The Contributors
    77
    88This program is free software: you can redistribute it and/or modify
     
    1717
    1818A copy of the GNU General Public License can be found in the file
    19 "gpl-v3.txt" in this directory.
     19"gpl-v3.txt" in the top directory of this repository.
    2020
    2121
  • emu/all.h

    rf996387 ra06aa8b  
     1/*
     2 *  Copyright (C) 2017 The Contributors
     3 *
     4 *  This program is free software: you can redistribute it and/or modify
     5 *  it under the terms of the GNU General Public License as published by
     6 *  the Free Software Foundation, either version 3 of the License, or (at
     7 *  your option) any later version.
     8 *
     9 *  This program is distributed in the hope that it will be useful, but
     10 *  WITHOUT ANY WARRANTY; without even the implied warranty of
     11 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
     12 *  General Public License for more details.
     13 *
     14 *  A copy of the GNU General Public License can be found in the file
     15 *  "gpl-v3.txt" in the top directory of this repository.
     16 */
     17
    118#include <stdbool.h>
    219#include <stddef.h>
     
    1734}
    1835
     36#define ARRAY_COUNT(_a) (int32_t)(sizeof (_a) / sizeof (_a)[0])
     37
     38extern bool sdl_verbose;
    1939extern bool cpu_verbose;
    20 extern bool sdl_verbose;
     40extern bool fpu_verbose;
     41extern bool vid_verbose;
     42extern bool tim_verbose;
     43extern bool lcd_verbose;
     44extern bool ser_verbose;
     45extern bool mid_verbose;
     46extern bool fdd_verbose;
     47extern bool snd_verbose;
     48extern bool led_verbose;
     49extern bool kbd_verbose;
    2150
    2251extern void sdl_init(void);
     
    2453
    2554extern void cpu_loop(void);
     55
     56extern void fpu_init(void);
     57extern void fpu_quit(void);
     58extern void fpu_exec(void);
     59extern uint32_t fpu_read(uint32_t off, int32_t sz);
     60extern void fpu_write(uint32_t off, int32_t sz, uint32_t val);
     61
     62extern void vid_init(void);
     63extern void vid_quit(void);
     64extern void vid_exec(void);
     65extern uint32_t vid_read(uint32_t off, int32_t sz);
     66extern void vid_write(uint32_t off, int32_t sz, uint32_t val);
     67
     68extern void tim_init(void);
     69extern void tim_quit(void);
     70extern void tim_exec(void);
     71extern uint32_t tim_read(uint32_t off, int32_t sz);
     72extern void tim_write(uint32_t off, int32_t sz, uint32_t val);
     73
     74extern void lcd_init(void);
     75extern void lcd_quit(void);
     76extern void lcd_exec(void);
     77extern uint32_t lcd_read(uint32_t off, int32_t sz);
     78extern void lcd_write(uint32_t off, int32_t sz, uint32_t val);
     79
     80extern void ser_init(void);
     81extern void ser_quit(void);
     82extern void ser_exec(void);
     83extern uint32_t ser_read(uint32_t off, int32_t sz);
     84extern void ser_write(uint32_t off, int32_t sz, uint32_t val);
     85
     86extern void mid_init(void);
     87extern void mid_quit(void);
     88extern void mid_exec(void);
     89extern uint32_t mid_read(uint32_t off, int32_t sz);
     90extern void mid_write(uint32_t off, int32_t sz, uint32_t val);
     91
     92extern void fdd_init(void);
     93extern void fdd_quit(void);
     94extern void fdd_exec(void);
     95extern uint32_t fdd_read(uint32_t off, int32_t sz);
     96extern void fdd_write(uint32_t off, int32_t sz, uint32_t val);
     97
     98extern void snd_init(void);
     99extern void snd_quit(void);
     100extern void snd_exec(void);
     101extern uint32_t snd_read(uint32_t off, int32_t sz);
     102extern void snd_write(uint32_t off, int32_t sz, uint32_t val);
     103
     104extern void led_init(void);
     105extern void led_quit(void);
     106extern void led_exec(void);
     107extern uint32_t led_read(uint32_t off, int32_t sz);
     108extern void led_write(uint32_t off, int32_t sz, uint32_t val);
     109
     110extern void kbd_init(void);
     111extern void kbd_quit(void);
     112extern void kbd_exec(void);
     113extern uint32_t kbd_read(uint32_t off, int32_t sz);
     114extern void kbd_write(uint32_t off, int32_t sz, uint32_t val);
  • emu/cpu.c

    rf996387 ra06aa8b  
     1/*
     2 *  Copyright (C) 2017 The Contributors
     3 *
     4 *  This program is free software: you can redistribute it and/or modify
     5 *  it under the terms of the GNU General Public License as published by
     6 *  the Free Software Foundation, either version 3 of the License, or (at
     7 *  your option) any later version.
     8 *
     9 *  This program is distributed in the hope that it will be useful, but
     10 *  WITHOUT ANY WARRANTY; without even the implied warranty of
     11 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
     12 *  General Public License for more details.
     13 *
     14 *  A copy of the GNU General Public License can be found in the file
     15 *  "gpl-v3.txt" in the top directory of this repository.
     16 */
     17
    118#include <all.h>
    219
     
    724}
    825
     26bool cpu_verbose = false;
     27
    928#define CYCLES 10
    1029
    11 #define RESET_PC 0x100000
    12 #define RESET_SP 0x100000
    13 
    14 bool cpu_verbose = false;
     30#define RAM_START 0x0
     31#define RAM_SIZE 0x100000
     32
     33#define ROM_START 0x100000
     34#define ROM_SIZE 0x10000
     35
     36#define RESET_SP ROM_START
     37#define RESET_PC ROM_START
     38
     39typedef void (*hw_init_t)(void);
     40typedef void (*hw_quit_t)(void);
     41typedef void (*hw_exec_t)(void);
     42typedef uint32_t (*hw_read_t)(uint32_t off, int32_t sz);
     43typedef void (*hw_write_t)(uint32_t off, int32_t sz, uint32_t val);
     44
     45typedef struct {
     46        uint32_t addr_beg;
     47        uint32_t addr_end;
     48        hw_init_t init;
     49        hw_quit_t quit;
     50        hw_exec_t exec;
     51        hw_read_t read;
     52        hw_write_t write;
     53} hw_t;
     54
    1555static bool reset = true;
    1656
     57static uint8_t ram_data[RAM_SIZE];
     58static uint8_t rom_data[ROM_SIZE];
     59
     60static uint32_t ram_rd_beg;
     61static uint32_t ram_rd_end;
     62static uint32_t ram_wr_beg;
     63static uint32_t ram_wr_end;
     64
     65static uint32_t rom_rd_beg;
     66static uint32_t rom_rd_end;
     67static uint32_t rom_wr_beg;
     68static uint32_t rom_wr_end;
     69
     70static hw_t hw_map[] = {
     71        { 0x180000, 0x200000, fpu_init, fpu_quit, fpu_exec, fpu_read, fpu_write },
     72        { 0x200000, 0x280000, vid_init, vid_quit, vid_exec, vid_read, vid_write },
     73        { 0x3a0001, 0x3a4001, tim_init, tim_quit, tim_exec, tim_read, tim_write },
     74        { 0x3a4001, 0x3a8001, lcd_init, lcd_quit, lcd_exec, lcd_read, lcd_write },
     75        { 0x3a8001, 0x3ac001, ser_init, ser_quit, ser_exec, ser_read, ser_write },
     76        { 0x3ac001, 0x3b0001, mid_init, mid_quit, mid_exec, mid_read, mid_write },
     77        { 0x3b0001, 0x3b4001, fdd_init, fdd_quit, fdd_exec, fdd_read, fdd_write },
     78        { 0x3b4001, 0x3b8001, snd_init, snd_quit, snd_exec, snd_read, snd_write },
     79        { 0x3b8001, 0x3bc001, led_init, led_quit, led_exec, led_read, led_write },
     80        { 0x3bc001, 0x3c0001, kbd_init, kbd_quit, kbd_exec, kbd_read, kbd_write }
     81};
     82
     83static hw_t *hw_by_addr(uint32_t addr)
     84{
     85        for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
     86                if (addr >= hw_map[i].addr_beg && addr < hw_map[i].addr_end) {
     87                        return hw_map + i;
     88                }
     89        }
     90
     91        return NULL;
     92}
     93
     94static void hw_init(void)
     95{
     96        for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
     97                hw_map[i].init();
     98        }
     99}
     100
     101static void hw_exec(void)
     102{
     103        for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
     104                hw_map[i].exec();
     105        }
     106}
     107
     108static uint32_t hw_off(hw_t *hw, uint32_t addr)
     109{
     110        if ((hw->addr_beg & 0x1) == 0) {
     111                return addr - hw->addr_beg;
     112        }
     113
     114        return (addr - hw->addr_beg) / 2;
     115}
     116
    17117uint32_t m68k_read_disassembler_8(uint32_t addr)
    18118{
     119        return m68k_read_memory_8(addr);
     120}
     121
     122uint32_t m68k_read_disassembler_16(uint32_t addr)
     123{
     124        return m68k_read_memory_16(addr);
     125}
     126
     127uint32_t m68k_read_disassembler_32(uint32_t addr)
     128{
     129        return m68k_read_memory_32(addr);
     130}
     131
     132uint32_t m68k_read_memory_8(uint32_t addr)
     133{
    19134        ver("mem rd 0x%08x:8", addr);
    20         return 0;
    21 }
    22 
    23 uint32_t m68k_read_disassembler_16(uint32_t addr)
     135
     136        if (addr >= ram_rd_beg && addr <= ram_rd_end - 1) {
     137                return ram_data[addr - RAM_START];
     138        }
     139
     140        if (addr >= rom_rd_beg && addr <= rom_rd_end - 1) {
     141                return rom_data[addr - ROM_START];
     142        }
     143
     144        hw_t *hw = hw_by_addr(addr);
     145
     146        if (hw != NULL) {
     147                return hw->read(hw_off(hw, addr), 1);
     148        }
     149
     150        fail("invalid read 0x%08x:8", addr);
     151}
     152
     153uint32_t m68k_read_memory_16(uint32_t addr)
    24154{
    25155        ver("mem rd 0x%08x:16", addr);
    26         return 0;
    27 }
    28 
    29 uint32_t m68k_read_disassembler_32(uint32_t addr)
    30 {
    31         ver("mem rd 0x%08x:32", addr);
    32         return 0;
    33 }
    34 
    35 uint32_t m68k_read_memory_8(uint32_t addr)
    36 {
    37         ver("mem rd 0x%08x:8", addr);
    38         return 0;
    39 }
    40 
    41 uint32_t m68k_read_memory_16(uint32_t addr)
    42 {
    43         ver("mem rd 0x%08x:16", addr);
    44 
    45         if (addr < 0x100000) {
    46         }
    47 
    48         if (addr < 0x110000) {
    49                 return 0x60fe;
    50         }
    51 
    52         return 0;
     156
     157        if (addr >= ram_rd_beg && addr <= ram_rd_end - 2) {
     158                return
     159                                ((uint32_t)ram_data[addr - RAM_START + 0] << 8) |
     160                                ((uint32_t)ram_data[addr - RAM_START + 1] << 0);
     161        }
     162
     163        if (addr >= rom_rd_beg && addr <= rom_rd_end - 2) {
     164                return
     165                                ((uint32_t)rom_data[addr - ROM_START + 0] << 8) |
     166                                ((uint32_t)rom_data[addr - ROM_START + 1] << 0);
     167        }
     168
     169        hw_t *hw = hw_by_addr(addr);
     170
     171        if (hw != NULL) {
     172                return hw->read(hw_off(hw, addr), 2);
     173        }
     174
     175        fail("invalid read 0x%08x:16", addr);
    53176}
    54177
     
    70193        }
    71194
    72         return 0;
     195        if (addr >= ram_rd_beg && addr <= ram_rd_end - 4) {
     196                return
     197                                ((uint32_t)ram_data[addr - RAM_START + 0] << 24) |
     198                                ((uint32_t)ram_data[addr - RAM_START + 1] << 16) |
     199                                ((uint32_t)ram_data[addr - RAM_START + 2] <<  8) |
     200                                ((uint32_t)ram_data[addr - RAM_START + 3] <<  0);
     201        }
     202
     203        if (addr >= rom_rd_beg && addr <= rom_rd_end - 4) {
     204                return
     205                                ((uint32_t)rom_data[addr - ROM_START + 0] << 24) |
     206                                ((uint32_t)rom_data[addr - ROM_START + 1] << 16) |
     207                                ((uint32_t)rom_data[addr - ROM_START + 2] <<  8) |
     208                                ((uint32_t)rom_data[addr - ROM_START + 3] <<  0);
     209        }
     210
     211        hw_t *hw = hw_by_addr(addr);
     212
     213        if (hw != NULL) {
     214                return hw->read(hw_off(hw, addr), 4);
     215        }
     216
     217        fail("invalid read 0x%08x:32", addr);
    73218}
    74219
     
    76221{
    77222        ver("mem wr 0x%08x:8 0x%02x", addr, val);
     223
     224        if (addr >= ram_wr_beg && addr <= ram_wr_end - 1) {
     225                ram_data[addr - RAM_START] = (uint8_t)val;
     226                return;
     227        }
     228
     229        if (addr >= rom_wr_beg && addr <= rom_wr_end - 1) {
     230                // ROM has its BSS section in RAM.
     231                ram_data[addr - RAM_START] = (uint8_t)val;
     232                return;
     233        }
     234
     235        hw_t *hw = hw_by_addr(addr);
     236
     237        if (hw != NULL) {
     238                hw->write(hw_off(hw, addr), 1, val);
     239                return;
     240        }
     241
     242        fail("invalid write 0x%08x:8 0x%02x", addr, val);
    78243}
    79244
     
    81246{
    82247        ver("mem wr 0x%08x:16 0x%04x", addr, val);
     248
     249        if (addr >= ram_wr_beg && addr <= ram_wr_end - 2) {
     250                ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 8);
     251                ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 0);
     252                return;
     253        }
     254
     255        if (addr >= rom_wr_beg && addr <= rom_wr_end - 2) {
     256                // ROM has its BSS section in RAM.
     257                ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 8);
     258                ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 0);
     259                return;
     260        }
     261
     262        hw_t *hw = hw_by_addr(addr);
     263
     264        if (hw != NULL) {
     265                hw->write(hw_off(hw, addr), 2, val);
     266                return;
     267        }
     268
     269        fail("invalid write 0x%08x:16 0x%04x", addr, val);
    83270}
    84271
     
    86273{
    87274        ver("mem wr 0x%08x:32 0x%08x", addr, val);
     275
     276        if (addr >= ram_wr_beg && addr <= ram_wr_end - 4) {
     277                ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 24);
     278                ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 16);
     279                ram_data[addr - RAM_START + 2] = (uint8_t)(val >>  8);
     280                ram_data[addr - RAM_START + 3] = (uint8_t)(val >>  0);
     281                return;
     282        }
     283
     284        if (addr >= rom_wr_beg && addr <= rom_wr_end - 4) {
     285                // ROM has its BSS section in RAM.
     286                ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 24);
     287                ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 16);
     288                ram_data[addr - RAM_START + 2] = (uint8_t)(val >>  8);
     289                ram_data[addr - RAM_START + 3] = (uint8_t)(val >>  0);
     290                return;
     291        }
     292
     293        hw_t *hw = hw_by_addr(addr);
     294
     295        if (hw != NULL) {
     296                hw->write(hw_off(hw, addr), 4, val);
     297                return;
     298        }
     299
     300        fail("invalid write 0x%08x:32 0x%08x", addr, val);
    88301}
    89302
    90303void cpu_loop(void)
    91304{
    92         ver("entering CPU loop");
    93 
     305        ver("initializing hardware");
     306        hw_init();
     307
     308        ver("starting CPU");
    94309        m68k_init();
    95310        m68k_set_cpu_type(M68K_CPU_TYPE_68000);
    96311        m68k_pulse_reset();
    97312
    98         for (int32_t i = 0; i < 5; ++i) {
     313        for (int32_t c = 0; c < 5; ++c) {
    99314                m68k_execute(CYCLES);
    100         }
    101 }
     315                hw_exec();
     316        }
     317}
  • emu/main.c

    rf996387 ra06aa8b  
     1/*
     2 *  Copyright (C) 2017 The Contributors
     3 *
     4 *  This program is free software: you can redistribute it and/or modify
     5 *  it under the terms of the GNU General Public License as published by
     6 *  the Free Software Foundation, either version 3 of the License, or (at
     7 *  your option) any later version.
     8 *
     9 *  This program is distributed in the hope that it will be useful, but
     10 *  WITHOUT ANY WARRANTY; without even the implied warranty of
     11 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
     12 *  General Public License for more details.
     13 *
     14 *  A copy of the GNU General Public License can be found in the file
     15 *  "gpl-v3.txt" in the top directory of this repository.
     16 */
     17
    118#include <all.h>
    219
  • emu/sdl.c

    rf996387 ra06aa8b  
     1/*
     2 *  Copyright (C) 2017 The Contributors
     3 *
     4 *  This program is free software: you can redistribute it and/or modify
     5 *  it under the terms of the GNU General Public License as published by
     6 *  the Free Software Foundation, either version 3 of the License, or (at
     7 *  your option) any later version.
     8 *
     9 *  This program is distributed in the hope that it will be useful, but
     10 *  WITHOUT ANY WARRANTY; without even the implied warranty of
     11 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
     12 *  General Public License for more details.
     13 *
     14 *  A copy of the GNU General Public License can be found in the file
     15 *  "gpl-v3.txt" in the top directory of this repository.
     16 */
     17
    118#include <all.h>
    219
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