source: buchla-emu/emu/cpu.c@ a06aa8b

Last change on this file since a06aa8b was a06aa8b, checked in by Thomas Lopatic <thomas@…>, 6 years ago

Added skeleton device files.

  • Property mode set to 100644
File size: 7.4 KB
Line 
1/*
2 * Copyright (C) 2017 The Contributors
3 *
4 * This program is free software: you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation, either version 3 of the License, or (at
7 * your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
13 *
14 * A copy of the GNU General Public License can be found in the file
15 * "gpl-v3.txt" in the top directory of this repository.
16 */
17
18#include <all.h>
19
20#define ver(...) { \
21 if (cpu_verbose) { \
22 SDL_LogVerbose(SDL_LOG_CATEGORY_APPLICATION, __VA_ARGS__); \
23 } \
24}
25
26bool cpu_verbose = false;
27
28#define CYCLES 10
29
30#define RAM_START 0x0
31#define RAM_SIZE 0x100000
32
33#define ROM_START 0x100000
34#define ROM_SIZE 0x10000
35
36#define RESET_SP ROM_START
37#define RESET_PC ROM_START
38
39typedef void (*hw_init_t)(void);
40typedef void (*hw_quit_t)(void);
41typedef void (*hw_exec_t)(void);
42typedef uint32_t (*hw_read_t)(uint32_t off, int32_t sz);
43typedef void (*hw_write_t)(uint32_t off, int32_t sz, uint32_t val);
44
45typedef struct {
46 uint32_t addr_beg;
47 uint32_t addr_end;
48 hw_init_t init;
49 hw_quit_t quit;
50 hw_exec_t exec;
51 hw_read_t read;
52 hw_write_t write;
53} hw_t;
54
55static bool reset = true;
56
57static uint8_t ram_data[RAM_SIZE];
58static uint8_t rom_data[ROM_SIZE];
59
60static uint32_t ram_rd_beg;
61static uint32_t ram_rd_end;
62static uint32_t ram_wr_beg;
63static uint32_t ram_wr_end;
64
65static uint32_t rom_rd_beg;
66static uint32_t rom_rd_end;
67static uint32_t rom_wr_beg;
68static uint32_t rom_wr_end;
69
70static hw_t hw_map[] = {
71 { 0x180000, 0x200000, fpu_init, fpu_quit, fpu_exec, fpu_read, fpu_write },
72 { 0x200000, 0x280000, vid_init, vid_quit, vid_exec, vid_read, vid_write },
73 { 0x3a0001, 0x3a4001, tim_init, tim_quit, tim_exec, tim_read, tim_write },
74 { 0x3a4001, 0x3a8001, lcd_init, lcd_quit, lcd_exec, lcd_read, lcd_write },
75 { 0x3a8001, 0x3ac001, ser_init, ser_quit, ser_exec, ser_read, ser_write },
76 { 0x3ac001, 0x3b0001, mid_init, mid_quit, mid_exec, mid_read, mid_write },
77 { 0x3b0001, 0x3b4001, fdd_init, fdd_quit, fdd_exec, fdd_read, fdd_write },
78 { 0x3b4001, 0x3b8001, snd_init, snd_quit, snd_exec, snd_read, snd_write },
79 { 0x3b8001, 0x3bc001, led_init, led_quit, led_exec, led_read, led_write },
80 { 0x3bc001, 0x3c0001, kbd_init, kbd_quit, kbd_exec, kbd_read, kbd_write }
81};
82
83static hw_t *hw_by_addr(uint32_t addr)
84{
85 for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
86 if (addr >= hw_map[i].addr_beg && addr < hw_map[i].addr_end) {
87 return hw_map + i;
88 }
89 }
90
91 return NULL;
92}
93
94static void hw_init(void)
95{
96 for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
97 hw_map[i].init();
98 }
99}
100
101static void hw_exec(void)
102{
103 for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
104 hw_map[i].exec();
105 }
106}
107
108static uint32_t hw_off(hw_t *hw, uint32_t addr)
109{
110 if ((hw->addr_beg & 0x1) == 0) {
111 return addr - hw->addr_beg;
112 }
113
114 return (addr - hw->addr_beg) / 2;
115}
116
117uint32_t m68k_read_disassembler_8(uint32_t addr)
118{
119 return m68k_read_memory_8(addr);
120}
121
122uint32_t m68k_read_disassembler_16(uint32_t addr)
123{
124 return m68k_read_memory_16(addr);
125}
126
127uint32_t m68k_read_disassembler_32(uint32_t addr)
128{
129 return m68k_read_memory_32(addr);
130}
131
132uint32_t m68k_read_memory_8(uint32_t addr)
133{
134 ver("mem rd 0x%08x:8", addr);
135
136 if (addr >= ram_rd_beg && addr <= ram_rd_end - 1) {
137 return ram_data[addr - RAM_START];
138 }
139
140 if (addr >= rom_rd_beg && addr <= rom_rd_end - 1) {
141 return rom_data[addr - ROM_START];
142 }
143
144 hw_t *hw = hw_by_addr(addr);
145
146 if (hw != NULL) {
147 return hw->read(hw_off(hw, addr), 1);
148 }
149
150 fail("invalid read 0x%08x:8", addr);
151}
152
153uint32_t m68k_read_memory_16(uint32_t addr)
154{
155 ver("mem rd 0x%08x:16", addr);
156
157 if (addr >= ram_rd_beg && addr <= ram_rd_end - 2) {
158 return
159 ((uint32_t)ram_data[addr - RAM_START + 0] << 8) |
160 ((uint32_t)ram_data[addr - RAM_START + 1] << 0);
161 }
162
163 if (addr >= rom_rd_beg && addr <= rom_rd_end - 2) {
164 return
165 ((uint32_t)rom_data[addr - ROM_START + 0] << 8) |
166 ((uint32_t)rom_data[addr - ROM_START + 1] << 0);
167 }
168
169 hw_t *hw = hw_by_addr(addr);
170
171 if (hw != NULL) {
172 return hw->read(hw_off(hw, addr), 2);
173 }
174
175 fail("invalid read 0x%08x:16", addr);
176}
177
178uint32_t m68k_read_memory_32(uint32_t addr)
179{
180 ver("mem rd 0x%08x:32", addr);
181
182 if (reset) {
183 if (addr == 0) {
184 return RESET_SP;
185 }
186
187 if (addr == 4) {
188 reset = false;
189 return RESET_PC;
190 }
191
192 fail("invalid reset sequence");
193 }
194
195 if (addr >= ram_rd_beg && addr <= ram_rd_end - 4) {
196 return
197 ((uint32_t)ram_data[addr - RAM_START + 0] << 24) |
198 ((uint32_t)ram_data[addr - RAM_START + 1] << 16) |
199 ((uint32_t)ram_data[addr - RAM_START + 2] << 8) |
200 ((uint32_t)ram_data[addr - RAM_START + 3] << 0);
201 }
202
203 if (addr >= rom_rd_beg && addr <= rom_rd_end - 4) {
204 return
205 ((uint32_t)rom_data[addr - ROM_START + 0] << 24) |
206 ((uint32_t)rom_data[addr - ROM_START + 1] << 16) |
207 ((uint32_t)rom_data[addr - ROM_START + 2] << 8) |
208 ((uint32_t)rom_data[addr - ROM_START + 3] << 0);
209 }
210
211 hw_t *hw = hw_by_addr(addr);
212
213 if (hw != NULL) {
214 return hw->read(hw_off(hw, addr), 4);
215 }
216
217 fail("invalid read 0x%08x:32", addr);
218}
219
220void m68k_write_memory_8(uint32_t addr, uint32_t val)
221{
222 ver("mem wr 0x%08x:8 0x%02x", addr, val);
223
224 if (addr >= ram_wr_beg && addr <= ram_wr_end - 1) {
225 ram_data[addr - RAM_START] = (uint8_t)val;
226 return;
227 }
228
229 if (addr >= rom_wr_beg && addr <= rom_wr_end - 1) {
230 // ROM has its BSS section in RAM.
231 ram_data[addr - RAM_START] = (uint8_t)val;
232 return;
233 }
234
235 hw_t *hw = hw_by_addr(addr);
236
237 if (hw != NULL) {
238 hw->write(hw_off(hw, addr), 1, val);
239 return;
240 }
241
242 fail("invalid write 0x%08x:8 0x%02x", addr, val);
243}
244
245void m68k_write_memory_16(uint32_t addr, uint32_t val)
246{
247 ver("mem wr 0x%08x:16 0x%04x", addr, val);
248
249 if (addr >= ram_wr_beg && addr <= ram_wr_end - 2) {
250 ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 8);
251 ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 0);
252 return;
253 }
254
255 if (addr >= rom_wr_beg && addr <= rom_wr_end - 2) {
256 // ROM has its BSS section in RAM.
257 ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 8);
258 ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 0);
259 return;
260 }
261
262 hw_t *hw = hw_by_addr(addr);
263
264 if (hw != NULL) {
265 hw->write(hw_off(hw, addr), 2, val);
266 return;
267 }
268
269 fail("invalid write 0x%08x:16 0x%04x", addr, val);
270}
271
272void m68k_write_memory_32(uint32_t addr, uint32_t val)
273{
274 ver("mem wr 0x%08x:32 0x%08x", addr, val);
275
276 if (addr >= ram_wr_beg && addr <= ram_wr_end - 4) {
277 ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 24);
278 ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 16);
279 ram_data[addr - RAM_START + 2] = (uint8_t)(val >> 8);
280 ram_data[addr - RAM_START + 3] = (uint8_t)(val >> 0);
281 return;
282 }
283
284 if (addr >= rom_wr_beg && addr <= rom_wr_end - 4) {
285 // ROM has its BSS section in RAM.
286 ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 24);
287 ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 16);
288 ram_data[addr - RAM_START + 2] = (uint8_t)(val >> 8);
289 ram_data[addr - RAM_START + 3] = (uint8_t)(val >> 0);
290 return;
291 }
292
293 hw_t *hw = hw_by_addr(addr);
294
295 if (hw != NULL) {
296 hw->write(hw_off(hw, addr), 4, val);
297 return;
298 }
299
300 fail("invalid write 0x%08x:32 0x%08x", addr, val);
301}
302
303void cpu_loop(void)
304{
305 ver("initializing hardware");
306 hw_init();
307
308 ver("starting CPU");
309 m68k_init();
310 m68k_set_cpu_type(M68K_CPU_TYPE_68000);
311 m68k_pulse_reset();
312
313 for (int32_t c = 0; c < 5; ++c) {
314 m68k_execute(CYCLES);
315 hw_exec();
316 }
317}
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