Changeset b28a12e in buchla-68k for ram/scinit.c


Ignore:
Timestamp:
07/10/2017 02:17:49 PM (7 years ago)
Author:
Thomas Lopatic <thomas@…>
Branches:
master
Children:
06f6615
Parents:
39a696b
Message:

Zero redundant declarations.

File:
1 edited

Legend:

Unmodified
Added
Removed

  • ram/scinit.c

    r39a696b rb28a12e  
    8080*/
    8181
    82 #include "all.h"
    83 
    84 extern void clkset(int16_t st);
    85 extern void dsclk(void);
    86 
    87 /*
    88 
    89 */
    90 
    91 extern  int16_t sd;             /* Scroll direction */
    92 extern  int16_t curasg;         /* Current assgnment table */
    93 extern  int16_t tmpoval;        /* Current tempo */
    94 extern  int16_t curtun;         /* Current tuning table */
    95 
    96 extern  struct  s_time  stimes[N_SCORES][N_SECTS];      /* section times */
    97 
    98 /*
    99 
    100 */
     82#include "ram.h"
    10183
    10284/*
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