- Timestamp:
- 07/31/2017 05:01:38 PM (7 years ago)
- Branches:
- master
- Children:
- 1489228
- Parents:
- 1efc42c
- git-author:
- Thomas Lopatic <thomas@…> (07/31/2017 05:01:32 PM)
- git-committer:
- Thomas Lopatic <thomas@…> (07/31/2017 05:01:38 PM)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
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-
emu/mid.c
r1efc42c rc5b6c90 23 23 24 24 int32_t mid_verbose = 0; 25 26 #define REG_IER_ISR 0 27 #define REG_CFR_SR 1 28 #define REG_CDR_TBR 2 29 #define REG_TDR_RDR 3 25 30 26 31 void mid_init(void) … … 49 54 { 50 55 ver2("mid wr %u:%d 0x%0*x", off, sz * 8, sz * 2, val); 56 57 if (sz != 1 || off > 7) { 58 fail("invalid mid wr %u:%d", off, sz * 8); 59 } 60 61 int32_t rg = (int32_t)(off % 4); 62 int32_t un = (int32_t)(off / 4); 63 64 switch (rg) { 65 case REG_CFR_SR: 66 ver2("CFR[%d] 0x%02x", un, val); 67 68 if (un == 1) { 69 fdd_set_side((int32_t)val & 0x01); 70 } 71 else { 72 fdd_set_sel((int32_t)val & 0x01); 73 } 74 75 break; 76 77 default: 78 break; 79 } 51 80 }
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