[a06aa8b] | 1 | /*
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| 2 | * Copyright (C) 2017 The Contributors
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| 3 | *
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| 4 | * This program is free software: you can redistribute it and/or modify
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| 5 | * it under the terms of the GNU General Public License as published by
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| 6 | * the Free Software Foundation, either version 3 of the License, or (at
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| 7 | * your option) any later version.
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| 8 | *
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| 9 | * This program is distributed in the hope that it will be useful, but
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| 10 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 12 | * General Public License for more details.
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| 13 | *
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| 14 | * A copy of the GNU General Public License can be found in the file
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[2147e53] | 15 | * "gpl.txt" in the top directory of this repository.
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[a06aa8b] | 16 | */
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| 17 |
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[ff8d800] | 18 | #include <all.h>
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| 19 |
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| 20 | #define ver(...) { \
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| 21 | if (cpu_verbose) { \
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| 22 | SDL_LogVerbose(SDL_LOG_CATEGORY_APPLICATION, __VA_ARGS__); \
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| 23 | } \
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| 24 | }
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| 25 |
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[a06aa8b] | 26 | bool cpu_verbose = false;
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| 27 |
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[ebc8f69] | 28 | #define CPU_FREQ 7000000
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| 29 | #define PER_SEC 100000
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[ff8d800] | 30 |
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[555b171] | 31 | #define APP_START 0x10000
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[ba36b71] | 32 |
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[a06aa8b] | 33 | #define RAM_START 0x0
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| 34 | #define RAM_SIZE 0x100000
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| 35 |
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| 36 | #define ROM_START 0x100000
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| 37 | #define ROM_SIZE 0x10000
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| 38 |
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| 39 | typedef void (*hw_init_t)(void);
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| 40 | typedef void (*hw_quit_t)(void);
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| 41 | typedef void (*hw_exec_t)(void);
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| 42 | typedef uint32_t (*hw_read_t)(uint32_t off, int32_t sz);
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| 43 | typedef void (*hw_write_t)(uint32_t off, int32_t sz, uint32_t val);
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| 44 |
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| 45 | typedef struct {
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| 46 | uint32_t addr_beg;
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| 47 | uint32_t addr_end;
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| 48 | hw_init_t init;
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| 49 | hw_quit_t quit;
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| 50 | hw_exec_t exec;
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| 51 | hw_read_t read;
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| 52 | hw_write_t write;
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| 53 | } hw_t;
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[ff8d800] | 54 |
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| 55 | static bool reset = true;
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| 56 |
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[a06aa8b] | 57 | static uint8_t ram_data[RAM_SIZE];
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| 58 | static uint8_t rom_data[ROM_SIZE];
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| 59 |
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[ba36b71] | 60 | static uint32_t ram_ro_beg = 0x1234;
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| 61 | static uint32_t ram_ro_end = 0x1234;
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| 62 | static uint32_t ram_rw_beg = 0x1234;
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| 63 | static uint32_t ram_rw_end = 0x1234;
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[a06aa8b] | 64 |
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[ba36b71] | 65 | static uint32_t rom_ro_beg;
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| 66 | static uint32_t rom_ro_end;
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| 67 | static uint32_t rom_rw_beg;
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| 68 | static uint32_t rom_rw_end;
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[a06aa8b] | 69 |
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| 70 | static hw_t hw_map[] = {
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| 71 | { 0x180000, 0x200000, fpu_init, fpu_quit, fpu_exec, fpu_read, fpu_write },
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| 72 | { 0x200000, 0x280000, vid_init, vid_quit, vid_exec, vid_read, vid_write },
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| 73 | { 0x3a0001, 0x3a4001, tim_init, tim_quit, tim_exec, tim_read, tim_write },
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| 74 | { 0x3a4001, 0x3a8001, lcd_init, lcd_quit, lcd_exec, lcd_read, lcd_write },
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| 75 | { 0x3a8001, 0x3ac001, ser_init, ser_quit, ser_exec, ser_read, ser_write },
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| 76 | { 0x3ac001, 0x3b0001, mid_init, mid_quit, mid_exec, mid_read, mid_write },
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| 77 | { 0x3b0001, 0x3b4001, fdd_init, fdd_quit, fdd_exec, fdd_read, fdd_write },
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| 78 | { 0x3b4001, 0x3b8001, snd_init, snd_quit, snd_exec, snd_read, snd_write },
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| 79 | { 0x3b8001, 0x3bc001, led_init, led_quit, led_exec, led_read, led_write },
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| 80 | { 0x3bc001, 0x3c0001, kbd_init, kbd_quit, kbd_exec, kbd_read, kbd_write }
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| 81 | };
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| 82 |
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| 83 | static hw_t *hw_by_addr(uint32_t addr)
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| 84 | {
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| 85 | for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
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| 86 | if (addr >= hw_map[i].addr_beg && addr < hw_map[i].addr_end) {
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| 87 | return hw_map + i;
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| 88 | }
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| 89 | }
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| 90 |
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| 91 | return NULL;
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| 92 | }
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| 93 |
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| 94 | static void hw_init(void)
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| 95 | {
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[ba36b71] | 96 | inf("initializing hardware");
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[b909777] | 97 |
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[a06aa8b] | 98 | for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
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| 99 | hw_map[i].init();
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| 100 | }
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| 101 | }
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| 102 |
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| 103 | static void hw_exec(void)
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| 104 | {
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| 105 | for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
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| 106 | hw_map[i].exec();
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| 107 | }
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| 108 | }
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| 109 |
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| 110 | static uint32_t hw_off(hw_t *hw, uint32_t addr)
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| 111 | {
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| 112 | if ((hw->addr_beg & 0x1) == 0) {
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| 113 | return addr - hw->addr_beg;
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| 114 | }
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| 115 |
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| 116 | return (addr - hw->addr_beg) / 2;
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| 117 | }
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| 118 |
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[b909777] | 119 | static void bios_init(const char *bios)
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| 120 | {
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[ba36b71] | 121 | inf("loading BIOS file %s", bios);
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[b909777] | 122 |
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| 123 | SDL_RWops *ops = SDL_RWFromFile(bios, "rb");
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| 124 |
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| 125 | if (ops == NULL) {
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| 126 | fail("error while opening BIOS file %s", bios);
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| 127 | }
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| 128 |
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| 129 | if (SDL_ReadBE16(ops) != 0x601b) {
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| 130 | fail("invalid BIOS file %s", bios);
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| 131 | }
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| 132 |
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| 133 | uint32_t text_len = SDL_ReadBE32(ops);
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| 134 | uint32_t data_len = SDL_ReadBE32(ops);
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| 135 | uint32_t bss_len = SDL_ReadBE32(ops);
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| 136 |
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| 137 | SDL_ReadBE32(ops);
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| 138 | SDL_ReadBE32(ops);
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| 139 |
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| 140 | uint32_t text_loc = SDL_ReadBE32(ops);
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| 141 |
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| 142 | SDL_ReadBE16(ops);
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| 143 |
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| 144 | uint32_t data_loc = SDL_ReadBE32(ops);
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| 145 | uint32_t bss_loc = SDL_ReadBE32(ops);
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| 146 |
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[ba36b71] | 147 | inf("BIOS text 0x%x:0x%x data 0x%x:0x%x bss 0x%x:0x%x",
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| 148 | text_loc, text_len, data_loc, data_len, bss_loc, bss_len);
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[b909777] | 149 |
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| 150 | size_t load_len = (size_t)SDL_RWsize(ops) - 36;
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| 151 |
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[ba36b71] | 152 | if (text_loc != ROM_START || text_loc + text_len != data_loc ||
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| 153 | load_len != text_len + data_len || load_len > ROM_SIZE) {
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| 154 | fail("invalid BIOS file %s", bios);
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[b909777] | 155 | }
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| 156 |
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| 157 | size_t loaded = 0;
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| 158 |
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| 159 | while (loaded < load_len) {
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| 160 | size_t n_rd = SDL_RWread(ops, rom_data + loaded, 1, load_len - loaded);
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| 161 |
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| 162 | if (n_rd == 0) {
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| 163 | fail("error while reading BIOS file %s", bios);
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| 164 | }
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| 165 |
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| 166 | loaded += n_rd;
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| 167 | }
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| 168 |
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| 169 | SDL_RWclose(ops);
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[ba36b71] | 170 |
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| 171 | rom_ro_beg = text_loc;
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| 172 | rom_ro_end = text_loc + text_len + data_len;
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| 173 | rom_rw_beg = bss_loc;
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| 174 | rom_rw_end = bss_loc + bss_len;
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| 175 |
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| 176 | ver("rom_ro_beg 0x%08x rom_ro_end 0x%08x", rom_ro_beg, rom_ro_end);
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| 177 | ver("rom_rw_beg 0x%08x rom_rw_end 0x%08x", rom_rw_beg, rom_rw_end);
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[b909777] | 178 | }
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| 179 |
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[ff8d800] | 180 | uint32_t m68k_read_disassembler_8(uint32_t addr)
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| 181 | {
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[a06aa8b] | 182 | return m68k_read_memory_8(addr);
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[ff8d800] | 183 | }
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| 184 |
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| 185 | uint32_t m68k_read_disassembler_16(uint32_t addr)
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| 186 | {
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[a06aa8b] | 187 | return m68k_read_memory_16(addr);
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[ff8d800] | 188 | }
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| 189 |
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| 190 | uint32_t m68k_read_disassembler_32(uint32_t addr)
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| 191 | {
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[a06aa8b] | 192 | return m68k_read_memory_32(addr);
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[ff8d800] | 193 | }
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| 194 |
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| 195 | uint32_t m68k_read_memory_8(uint32_t addr)
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| 196 | {
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| 197 | ver("mem rd 0x%08x:8", addr);
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[a06aa8b] | 198 |
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[ba36b71] | 199 | if (addr >= ram_ro_beg && addr <= ram_ro_end - 1) {
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| 200 | return ram_data[addr - RAM_START];
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| 201 | }
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| 202 |
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| 203 | if (addr >= ram_rw_beg && addr <= ram_rw_end - 1) {
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[a06aa8b] | 204 | return ram_data[addr - RAM_START];
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| 205 | }
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| 206 |
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[ba36b71] | 207 | if (addr >= rom_ro_beg && addr <= rom_ro_end - 1) {
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[a06aa8b] | 208 | return rom_data[addr - ROM_START];
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| 209 | }
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| 210 |
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[ba36b71] | 211 | if (addr >= rom_rw_beg && addr <= rom_rw_end - 1) {
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| 212 | // ROM has its BSS section in RAM.
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| 213 | return ram_data[addr - RAM_START];
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| 214 | }
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| 215 |
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[a06aa8b] | 216 | hw_t *hw = hw_by_addr(addr);
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| 217 |
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| 218 | if (hw != NULL) {
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| 219 | return hw->read(hw_off(hw, addr), 1);
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| 220 | }
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| 221 |
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[555b171] | 222 | if (addr <= APP_START - 1) {
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[ba36b71] | 223 | return ram_data[addr];
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| 224 | }
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| 225 |
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[a06aa8b] | 226 | fail("invalid read 0x%08x:8", addr);
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[ff8d800] | 227 | }
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| 228 |
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| 229 | uint32_t m68k_read_memory_16(uint32_t addr)
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| 230 | {
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| 231 | ver("mem rd 0x%08x:16", addr);
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| 232 |
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[ba36b71] | 233 | if (addr >= ram_ro_beg && addr <= ram_ro_end - 2) {
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| 234 | return
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| 235 | ((uint32_t)ram_data[addr - RAM_START + 0] << 8) |
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| 236 | ((uint32_t)ram_data[addr - RAM_START + 1] << 0);
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| 237 | }
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| 238 |
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| 239 | if (addr >= ram_rw_beg && addr <= ram_rw_end - 2) {
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[a06aa8b] | 240 | return
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| 241 | ((uint32_t)ram_data[addr - RAM_START + 0] << 8) |
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| 242 | ((uint32_t)ram_data[addr - RAM_START + 1] << 0);
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| 243 | }
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| 244 |
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[ba36b71] | 245 | if (addr >= rom_ro_beg && addr <= rom_ro_end - 2) {
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[a06aa8b] | 246 | return
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| 247 | ((uint32_t)rom_data[addr - ROM_START + 0] << 8) |
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| 248 | ((uint32_t)rom_data[addr - ROM_START + 1] << 0);
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[ff8d800] | 249 | }
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| 250 |
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[ba36b71] | 251 | if (addr >= rom_rw_beg && addr <= rom_rw_end - 2) {
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| 252 | // ROM has its BSS section in RAM.
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| 253 | return
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| 254 | ((uint32_t)ram_data[addr - RAM_START + 0] << 8) |
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| 255 | ((uint32_t)ram_data[addr - RAM_START + 1] << 0);
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| 256 | }
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| 257 |
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[a06aa8b] | 258 | hw_t *hw = hw_by_addr(addr);
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| 259 |
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| 260 | if (hw != NULL) {
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| 261 | return hw->read(hw_off(hw, addr), 2);
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[ff8d800] | 262 | }
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| 263 |
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[555b171] | 264 | if (addr <= APP_START - 2) {
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[ba36b71] | 265 | return
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| 266 | ((uint32_t)ram_data[addr - 0] << 8) |
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| 267 | ((uint32_t)ram_data[addr - 1] << 0);
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| 268 | }
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| 269 |
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[a06aa8b] | 270 | fail("invalid read 0x%08x:16", addr);
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[ff8d800] | 271 | }
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| 272 |
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| 273 | uint32_t m68k_read_memory_32(uint32_t addr)
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| 274 | {
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| 275 | ver("mem rd 0x%08x:32", addr);
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| 276 |
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| 277 | if (reset) {
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| 278 | if (addr == 0) {
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[b909777] | 279 | addr += ROM_START;
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[ff8d800] | 280 | }
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| 281 |
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[b909777] | 282 | else if (addr == 4) {
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| 283 | addr += ROM_START;
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[ff8d800] | 284 | reset = false;
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| 285 | }
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[b909777] | 286 | else {
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| 287 | fail("invalid reset sequence");
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| 288 | }
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[ff8d800] | 289 | }
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| 290 |
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[ba36b71] | 291 | if (addr >= ram_ro_beg && addr <= ram_ro_end - 4) {
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[a06aa8b] | 292 | return
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| 293 | ((uint32_t)ram_data[addr - RAM_START + 0] << 24) |
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| 294 | ((uint32_t)ram_data[addr - RAM_START + 1] << 16) |
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| 295 | ((uint32_t)ram_data[addr - RAM_START + 2] << 8) |
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| 296 | ((uint32_t)ram_data[addr - RAM_START + 3] << 0);
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| 297 | }
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| 298 |
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[ba36b71] | 299 | if (addr >= ram_rw_beg && addr <= ram_rw_end - 4) {
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| 300 | return
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| 301 | ((uint32_t)ram_data[addr - RAM_START + 0] << 24) |
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| 302 | ((uint32_t)ram_data[addr - RAM_START + 1] << 16) |
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| 303 | ((uint32_t)ram_data[addr - RAM_START + 2] << 8) |
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| 304 | ((uint32_t)ram_data[addr - RAM_START + 3] << 0);
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| 305 | }
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| 306 |
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| 307 | if (addr >= rom_ro_beg && addr <= rom_ro_end - 4) {
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[a06aa8b] | 308 | return
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| 309 | ((uint32_t)rom_data[addr - ROM_START + 0] << 24) |
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| 310 | ((uint32_t)rom_data[addr - ROM_START + 1] << 16) |
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| 311 | ((uint32_t)rom_data[addr - ROM_START + 2] << 8) |
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| 312 | ((uint32_t)rom_data[addr - ROM_START + 3] << 0);
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| 313 | }
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| 314 |
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[ba36b71] | 315 | if (addr >= rom_rw_beg && addr <= rom_rw_end - 4) {
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| 316 | // ROM has its BSS section in RAM.
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| 317 | return
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| 318 | ((uint32_t)ram_data[addr - RAM_START + 0] << 24) |
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| 319 | ((uint32_t)ram_data[addr - RAM_START + 1] << 16) |
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| 320 | ((uint32_t)ram_data[addr - RAM_START + 2] << 8) |
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| 321 | ((uint32_t)ram_data[addr - RAM_START + 3] << 0);
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| 322 | }
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| 323 |
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[a06aa8b] | 324 | hw_t *hw = hw_by_addr(addr);
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| 325 |
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| 326 | if (hw != NULL) {
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| 327 | return hw->read(hw_off(hw, addr), 4);
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| 328 | }
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| 329 |
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[555b171] | 330 | if (addr <= APP_START - 4) {
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[ba36b71] | 331 | return
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| 332 | ((uint32_t)ram_data[addr + 0] << 24) |
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| 333 | ((uint32_t)ram_data[addr + 1] << 16) |
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| 334 | ((uint32_t)ram_data[addr + 2] << 8) |
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| 335 | ((uint32_t)ram_data[addr + 3] << 0);
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| 336 | }
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| 337 |
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[a06aa8b] | 338 | fail("invalid read 0x%08x:32", addr);
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[ff8d800] | 339 | }
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| 340 |
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| 341 | void m68k_write_memory_8(uint32_t addr, uint32_t val)
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| 342 | {
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| 343 | ver("mem wr 0x%08x:8 0x%02x", addr, val);
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[a06aa8b] | 344 |
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[ba36b71] | 345 | if (addr >= ram_rw_beg && addr <= ram_rw_end - 1) {
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[a06aa8b] | 346 | ram_data[addr - RAM_START] = (uint8_t)val;
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| 347 | return;
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| 348 | }
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| 349 |
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[ba36b71] | 350 | if (addr >= rom_rw_beg && addr <= rom_rw_end - 1) {
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[a06aa8b] | 351 | // ROM has its BSS section in RAM.
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| 352 | ram_data[addr - RAM_START] = (uint8_t)val;
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| 353 | return;
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| 354 | }
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| 355 |
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| 356 | hw_t *hw = hw_by_addr(addr);
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| 357 |
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| 358 | if (hw != NULL) {
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| 359 | hw->write(hw_off(hw, addr), 1, val);
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| 360 | return;
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| 361 | }
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| 362 |
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[555b171] | 363 | if (addr <= APP_START - 1) {
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[ba36b71] | 364 | ram_data[addr] = (uint8_t)val;
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| 365 | return;
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| 366 | }
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| 367 |
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[a06aa8b] | 368 | fail("invalid write 0x%08x:8 0x%02x", addr, val);
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[ff8d800] | 369 | }
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| 370 |
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| 371 | void m68k_write_memory_16(uint32_t addr, uint32_t val)
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| 372 | {
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| 373 | ver("mem wr 0x%08x:16 0x%04x", addr, val);
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[a06aa8b] | 374 |
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[ba36b71] | 375 | if (addr >= ram_rw_beg && addr <= ram_rw_end - 2) {
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[a06aa8b] | 376 | ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 8);
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| 377 | ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 0);
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| 378 | return;
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| 379 | }
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| 380 |
|
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[ba36b71] | 381 | if (addr >= rom_rw_beg && addr <= rom_rw_end - 2) {
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[a06aa8b] | 382 | // ROM has its BSS section in RAM.
|
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| 383 | ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 8);
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| 384 | ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 0);
|
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| 385 | return;
|
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| 386 | }
|
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| 387 |
|
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| 388 | hw_t *hw = hw_by_addr(addr);
|
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| 389 |
|
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| 390 | if (hw != NULL) {
|
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| 391 | hw->write(hw_off(hw, addr), 2, val);
|
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| 392 | return;
|
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| 393 | }
|
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| 394 |
|
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[555b171] | 395 | if (addr <= APP_START - 2) {
|
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[ba36b71] | 396 | ram_data[addr + 0] = (uint8_t)(val >> 8);
|
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| 397 | ram_data[addr + 1] = (uint8_t)(val >> 0);
|
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| 398 | return;
|
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| 399 | }
|
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| 400 |
|
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[a06aa8b] | 401 | fail("invalid write 0x%08x:16 0x%04x", addr, val);
|
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[ff8d800] | 402 | }
|
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| 403 |
|
---|
| 404 | void m68k_write_memory_32(uint32_t addr, uint32_t val)
|
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| 405 | {
|
---|
| 406 | ver("mem wr 0x%08x:32 0x%08x", addr, val);
|
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[a06aa8b] | 407 |
|
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[ba36b71] | 408 | if (addr >= ram_rw_beg && addr <= ram_rw_end - 4) {
|
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[a06aa8b] | 409 | ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 24);
|
---|
| 410 | ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 16);
|
---|
| 411 | ram_data[addr - RAM_START + 2] = (uint8_t)(val >> 8);
|
---|
| 412 | ram_data[addr - RAM_START + 3] = (uint8_t)(val >> 0);
|
---|
| 413 | return;
|
---|
| 414 | }
|
---|
| 415 |
|
---|
[ba36b71] | 416 | if (addr >= rom_rw_beg && addr <= rom_rw_end - 4) {
|
---|
[a06aa8b] | 417 | // ROM has its BSS section in RAM.
|
---|
| 418 | ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 24);
|
---|
| 419 | ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 16);
|
---|
| 420 | ram_data[addr - RAM_START + 2] = (uint8_t)(val >> 8);
|
---|
| 421 | ram_data[addr - RAM_START + 3] = (uint8_t)(val >> 0);
|
---|
| 422 | return;
|
---|
| 423 | }
|
---|
| 424 |
|
---|
| 425 | hw_t *hw = hw_by_addr(addr);
|
---|
| 426 |
|
---|
| 427 | if (hw != NULL) {
|
---|
| 428 | hw->write(hw_off(hw, addr), 4, val);
|
---|
| 429 | return;
|
---|
| 430 | }
|
---|
| 431 |
|
---|
[555b171] | 432 | if (addr <= APP_START - 4) {
|
---|
[ba36b71] | 433 | ram_data[addr + 0] = (uint8_t)(val >> 24);
|
---|
| 434 | ram_data[addr + 1] = (uint8_t)(val >> 16);
|
---|
| 435 | ram_data[addr + 2] = (uint8_t)(val >> 8);
|
---|
| 436 | ram_data[addr + 3] = (uint8_t)(val >> 0);
|
---|
| 437 | return;
|
---|
| 438 | }
|
---|
| 439 |
|
---|
[a06aa8b] | 440 | fail("invalid write 0x%08x:32 0x%08x", addr, val);
|
---|
[ff8d800] | 441 | }
|
---|
| 442 |
|
---|
[b909777] | 443 | void cpu_loop(const char *bios)
|
---|
[ff8d800] | 444 | {
|
---|
[a06aa8b] | 445 | hw_init();
|
---|
[b909777] | 446 | bios_init(bios);
|
---|
[ff8d800] | 447 |
|
---|
[ba36b71] | 448 | inf("entering CPU loop");
|
---|
[ff8d800] | 449 | m68k_init();
|
---|
| 450 | m68k_set_cpu_type(M68K_CPU_TYPE_68000);
|
---|
| 451 | m68k_pulse_reset();
|
---|
| 452 |
|
---|
[ebc8f69] | 453 | uint64_t freq = SDL_GetPerformanceFrequency();
|
---|
| 454 | uint64_t quan = freq / PER_SEC;
|
---|
| 455 | inf("freq %" PRIu64 " quan %" PRIu64, freq, quan);
|
---|
| 456 |
|
---|
[e41c6b6] | 457 | bool run = true;
|
---|
| 458 |
|
---|
| 459 | while (run) {
|
---|
[ebc8f69] | 460 | uint64_t until = SDL_GetPerformanceCounter() + quan;
|
---|
| 461 |
|
---|
| 462 | m68k_execute(CPU_FREQ / PER_SEC);
|
---|
[a06aa8b] | 463 | hw_exec();
|
---|
[e41c6b6] | 464 |
|
---|
| 465 | SDL_Event ev;
|
---|
| 466 |
|
---|
| 467 | while (SDL_PollEvent(&ev) > 0) {
|
---|
| 468 | if (ev.type == SDL_QUIT) {
|
---|
| 469 | run = false;
|
---|
| 470 | }
|
---|
| 471 | }
|
---|
[ebc8f69] | 472 |
|
---|
| 473 | while (SDL_GetPerformanceCounter() < until) {
|
---|
| 474 | _mm_pause();
|
---|
| 475 | }
|
---|
[ff8d800] | 476 | }
|
---|
[e41c6b6] | 477 |
|
---|
| 478 | inf("leaving CPU loop");
|
---|
[ff8d800] | 479 | }
|
---|