source: buchla-emu/emu/cpu.c@ 51b6cfd

Last change on this file since 51b6cfd was 51b6cfd, checked in by Thomas Lopatic <thomas@…>, 7 years ago

Removed unnecessary definitions.
  • Property mode set to 100644
File size: 8.5 KB
Line 
1/*
2 * Copyright (C) 2017 The Contributors
3 *
4 * This program is free software: you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation, either version 3 of the License, or (at
7 * your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
13 *
14 * A copy of the GNU General Public License can be found in the file
15 * "gpl-v3.txt" in the top directory of this repository.
16 */
17
18#include <all.h>
19
20#define ver(...) { \
21 if (cpu_verbose) { \
22 SDL_LogVerbose(SDL_LOG_CATEGORY_APPLICATION, __VA_ARGS__); \
23 } \
24}
25
26bool cpu_verbose = false;
27
28#define CYCLES 10
29
30#define RAM_START 0x0
31#define RAM_SIZE 0x100000
32
33#define ROM_START 0x100000
34#define ROM_SIZE 0x10000
35
36typedef void (*hw_init_t)(void);
37typedef void (*hw_quit_t)(void);
38typedef void (*hw_exec_t)(void);
39typedef uint32_t (*hw_read_t)(uint32_t off, int32_t sz);
40typedef void (*hw_write_t)(uint32_t off, int32_t sz, uint32_t val);
41
42typedef struct {
43 uint32_t addr_beg;
44 uint32_t addr_end;
45 hw_init_t init;
46 hw_quit_t quit;
47 hw_exec_t exec;
48 hw_read_t read;
49 hw_write_t write;
50} hw_t;
51
52static bool reset = true;
53
54static uint8_t ram_data[RAM_SIZE];
55static uint8_t rom_data[ROM_SIZE];
56
57static uint32_t ram_rd_beg = 0x10000000;
58static uint32_t ram_rd_end = 0x10000000;
59static uint32_t ram_wr_beg = 0x10000000;
60static uint32_t ram_wr_end = 0x10000000;
61
62static uint32_t rom_rd_beg;
63static uint32_t rom_rd_end;
64static uint32_t rom_wr_beg;
65static uint32_t rom_wr_end;
66
67static hw_t hw_map[] = {
68 { 0x180000, 0x200000, fpu_init, fpu_quit, fpu_exec, fpu_read, fpu_write },
69 { 0x200000, 0x280000, vid_init, vid_quit, vid_exec, vid_read, vid_write },
70 { 0x3a0001, 0x3a4001, tim_init, tim_quit, tim_exec, tim_read, tim_write },
71 { 0x3a4001, 0x3a8001, lcd_init, lcd_quit, lcd_exec, lcd_read, lcd_write },
72 { 0x3a8001, 0x3ac001, ser_init, ser_quit, ser_exec, ser_read, ser_write },
73 { 0x3ac001, 0x3b0001, mid_init, mid_quit, mid_exec, mid_read, mid_write },
74 { 0x3b0001, 0x3b4001, fdd_init, fdd_quit, fdd_exec, fdd_read, fdd_write },
75 { 0x3b4001, 0x3b8001, snd_init, snd_quit, snd_exec, snd_read, snd_write },
76 { 0x3b8001, 0x3bc001, led_init, led_quit, led_exec, led_read, led_write },
77 { 0x3bc001, 0x3c0001, kbd_init, kbd_quit, kbd_exec, kbd_read, kbd_write }
78};
79
80static hw_t *hw_by_addr(uint32_t addr)
81{
82 for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
83 if (addr >= hw_map[i].addr_beg && addr < hw_map[i].addr_end) {
84 return hw_map + i;
85 }
86 }
87
88 return NULL;
89}
90
91static void hw_init(void)
92{
93 ver("initializing hardware");
94
95 for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
96 hw_map[i].init();
97 }
98}
99
100static void hw_exec(void)
101{
102 for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
103 hw_map[i].exec();
104 }
105}
106
107static uint32_t hw_off(hw_t *hw, uint32_t addr)
108{
109 if ((hw->addr_beg & 0x1) == 0) {
110 return addr - hw->addr_beg;
111 }
112
113 return (addr - hw->addr_beg) / 2;
114}
115
116static void bios_init(const char *bios)
117{
118 ver("loading BIOS file %s", bios);
119
120 SDL_RWops *ops = SDL_RWFromFile(bios, "rb");
121
122 if (ops == NULL) {
123 fail("error while opening BIOS file %s", bios);
124 }
125
126 if (SDL_ReadBE16(ops) != 0x601b) {
127 fail("invalid BIOS file %s", bios);
128 }
129
130 uint32_t text_len = SDL_ReadBE32(ops);
131 uint32_t data_len = SDL_ReadBE32(ops);
132 uint32_t bss_len = SDL_ReadBE32(ops);
133
134 SDL_ReadBE32(ops);
135 SDL_ReadBE32(ops);
136
137 uint32_t text_loc = SDL_ReadBE32(ops);
138
139 SDL_ReadBE16(ops);
140
141 uint32_t data_loc = SDL_ReadBE32(ops);
142 uint32_t bss_loc = SDL_ReadBE32(ops);
143
144 ver("text 0x%x@0x%x data 0x%x@0x%x bss 0x%x@0x%x",
145 text_len, text_loc, data_len, data_loc, bss_len, bss_loc);
146
147 size_t load_len = (size_t)SDL_RWsize(ops) - 36;
148
149 if (load_len != text_len + data_len) {
150 fail("corrupted BIOS file %s", bios);
151 }
152
153 size_t loaded = 0;
154
155 while (loaded < load_len) {
156 size_t n_rd = SDL_RWread(ops, rom_data + loaded, 1, load_len - loaded);
157
158 if (n_rd == 0) {
159 fail("error while reading BIOS file %s", bios);
160 }
161
162 loaded += n_rd;
163 }
164
165 SDL_RWclose(ops);
166}
167
168uint32_t m68k_read_disassembler_8(uint32_t addr)
169{
170 return m68k_read_memory_8(addr);
171}
172
173uint32_t m68k_read_disassembler_16(uint32_t addr)
174{
175 return m68k_read_memory_16(addr);
176}
177
178uint32_t m68k_read_disassembler_32(uint32_t addr)
179{
180 return m68k_read_memory_32(addr);
181}
182
183uint32_t m68k_read_memory_8(uint32_t addr)
184{
185 ver("mem rd 0x%08x:8", addr);
186
187 if (addr >= ram_rd_beg && addr <= ram_rd_end - 1) {
188 return ram_data[addr - RAM_START];
189 }
190
191 if (addr >= rom_rd_beg && addr <= rom_rd_end - 1) {
192 return rom_data[addr - ROM_START];
193 }
194
195 hw_t *hw = hw_by_addr(addr);
196
197 if (hw != NULL) {
198 return hw->read(hw_off(hw, addr), 1);
199 }
200
201 fail("invalid read 0x%08x:8", addr);
202}
203
204uint32_t m68k_read_memory_16(uint32_t addr)
205{
206 ver("mem rd 0x%08x:16", addr);
207
208 if (addr >= ram_rd_beg && addr <= ram_rd_end - 2) {
209 return
210 ((uint32_t)ram_data[addr - RAM_START + 0] << 8) |
211 ((uint32_t)ram_data[addr - RAM_START + 1] << 0);
212 }
213
214 if (addr >= rom_rd_beg && addr <= rom_rd_end - 2) {
215 return
216 ((uint32_t)rom_data[addr - ROM_START + 0] << 8) |
217 ((uint32_t)rom_data[addr - ROM_START + 1] << 0);
218 }
219
220 hw_t *hw = hw_by_addr(addr);
221
222 if (hw != NULL) {
223 return hw->read(hw_off(hw, addr), 2);
224 }
225
226 fail("invalid read 0x%08x:16", addr);
227}
228
229uint32_t m68k_read_memory_32(uint32_t addr)
230{
231 ver("mem rd 0x%08x:32", addr);
232
233 if (reset) {
234 if (addr == 0) {
235 addr += ROM_START;
236 }
237
238 else if (addr == 4) {
239 addr += ROM_START;
240 reset = false;
241 }
242 else {
243 fail("invalid reset sequence");
244 }
245 }
246
247 if (addr >= ram_rd_beg && addr <= ram_rd_end - 4) {
248 return
249 ((uint32_t)ram_data[addr - RAM_START + 0] << 24) |
250 ((uint32_t)ram_data[addr - RAM_START + 1] << 16) |
251 ((uint32_t)ram_data[addr - RAM_START + 2] << 8) |
252 ((uint32_t)ram_data[addr - RAM_START + 3] << 0);
253 }
254
255 if (addr >= rom_rd_beg && addr <= rom_rd_end - 4) {
256 return
257 ((uint32_t)rom_data[addr - ROM_START + 0] << 24) |
258 ((uint32_t)rom_data[addr - ROM_START + 1] << 16) |
259 ((uint32_t)rom_data[addr - ROM_START + 2] << 8) |
260 ((uint32_t)rom_data[addr - ROM_START + 3] << 0);
261 }
262
263 hw_t *hw = hw_by_addr(addr);
264
265 if (hw != NULL) {
266 return hw->read(hw_off(hw, addr), 4);
267 }
268
269 fail("invalid read 0x%08x:32", addr);
270}
271
272void m68k_write_memory_8(uint32_t addr, uint32_t val)
273{
274 ver("mem wr 0x%08x:8 0x%02x", addr, val);
275
276 if (addr >= ram_wr_beg && addr <= ram_wr_end - 1) {
277 ram_data[addr - RAM_START] = (uint8_t)val;
278 return;
279 }
280
281 if (addr >= rom_wr_beg && addr <= rom_wr_end - 1) {
282 // ROM has its BSS section in RAM.
283 ram_data[addr - RAM_START] = (uint8_t)val;
284 return;
285 }
286
287 hw_t *hw = hw_by_addr(addr);
288
289 if (hw != NULL) {
290 hw->write(hw_off(hw, addr), 1, val);
291 return;
292 }
293
294 fail("invalid write 0x%08x:8 0x%02x", addr, val);
295}
296
297void m68k_write_memory_16(uint32_t addr, uint32_t val)
298{
299 ver("mem wr 0x%08x:16 0x%04x", addr, val);
300
301 if (addr >= ram_wr_beg && addr <= ram_wr_end - 2) {
302 ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 8);
303 ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 0);
304 return;
305 }
306
307 if (addr >= rom_wr_beg && addr <= rom_wr_end - 2) {
308 // ROM has its BSS section in RAM.
309 ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 8);
310 ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 0);
311 return;
312 }
313
314 hw_t *hw = hw_by_addr(addr);
315
316 if (hw != NULL) {
317 hw->write(hw_off(hw, addr), 2, val);
318 return;
319 }
320
321 fail("invalid write 0x%08x:16 0x%04x", addr, val);
322}
323
324void m68k_write_memory_32(uint32_t addr, uint32_t val)
325{
326 ver("mem wr 0x%08x:32 0x%08x", addr, val);
327
328 if (addr >= ram_wr_beg && addr <= ram_wr_end - 4) {
329 ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 24);
330 ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 16);
331 ram_data[addr - RAM_START + 2] = (uint8_t)(val >> 8);
332 ram_data[addr - RAM_START + 3] = (uint8_t)(val >> 0);
333 return;
334 }
335
336 if (addr >= rom_wr_beg && addr <= rom_wr_end - 4) {
337 // ROM has its BSS section in RAM.
338 ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 24);
339 ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 16);
340 ram_data[addr - RAM_START + 2] = (uint8_t)(val >> 8);
341 ram_data[addr - RAM_START + 3] = (uint8_t)(val >> 0);
342 return;
343 }
344
345 hw_t *hw = hw_by_addr(addr);
346
347 if (hw != NULL) {
348 hw->write(hw_off(hw, addr), 4, val);
349 return;
350 }
351
352 fail("invalid write 0x%08x:32 0x%08x", addr, val);
353}
354
355void cpu_loop(const char *bios)
356{
357 ver("entering CPU loop");
358
359 hw_init();
360 bios_init(bios);
361
362 ver("starting CPU");
363 m68k_init();
364 m68k_set_cpu_type(M68K_CPU_TYPE_68000);
365 m68k_pulse_reset();
366
367 for (int32_t c = 0; c < 5; ++c) {
368 m68k_execute(CYCLES);
369 hw_exec();
370 }
371}
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