source: buchla-emu/emu/cpu.c@ b909777

Last change on this file since b909777 was b909777, checked in by Thomas Lopatic <thomas@…>, 7 years ago

Parse command line options. Load BIOS file.
  • Property mode set to 100644
File size: 8.6 KB
Line 
1/*
2 * Copyright (C) 2017 The Contributors
3 *
4 * This program is free software: you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation, either version 3 of the License, or (at
7 * your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
13 *
14 * A copy of the GNU General Public License can be found in the file
15 * "gpl-v3.txt" in the top directory of this repository.
16 */
17
18#include <all.h>
19
20#define ver(...) { \
21 if (cpu_verbose) { \
22 SDL_LogVerbose(SDL_LOG_CATEGORY_APPLICATION, __VA_ARGS__); \
23 } \
24}
25
26bool cpu_verbose = false;
27
28#define CYCLES 10
29
30#define RAM_START 0x0
31#define RAM_SIZE 0x100000
32
33#define ROM_START 0x100000
34#define ROM_SIZE 0x10000
35
36#define RESET_SP ROM_START
37#define RESET_PC ROM_START
38
39typedef void (*hw_init_t)(void);
40typedef void (*hw_quit_t)(void);
41typedef void (*hw_exec_t)(void);
42typedef uint32_t (*hw_read_t)(uint32_t off, int32_t sz);
43typedef void (*hw_write_t)(uint32_t off, int32_t sz, uint32_t val);
44
45typedef struct {
46 uint32_t addr_beg;
47 uint32_t addr_end;
48 hw_init_t init;
49 hw_quit_t quit;
50 hw_exec_t exec;
51 hw_read_t read;
52 hw_write_t write;
53} hw_t;
54
55static bool reset = true;
56
57static uint8_t ram_data[RAM_SIZE];
58static uint8_t rom_data[ROM_SIZE];
59
60static uint32_t ram_rd_beg = 0x10000000;
61static uint32_t ram_rd_end = 0x10000000;
62static uint32_t ram_wr_beg = 0x10000000;
63static uint32_t ram_wr_end = 0x10000000;
64
65static uint32_t rom_rd_beg;
66static uint32_t rom_rd_end;
67static uint32_t rom_wr_beg;
68static uint32_t rom_wr_end;
69
70static hw_t hw_map[] = {
71 { 0x180000, 0x200000, fpu_init, fpu_quit, fpu_exec, fpu_read, fpu_write },
72 { 0x200000, 0x280000, vid_init, vid_quit, vid_exec, vid_read, vid_write },
73 { 0x3a0001, 0x3a4001, tim_init, tim_quit, tim_exec, tim_read, tim_write },
74 { 0x3a4001, 0x3a8001, lcd_init, lcd_quit, lcd_exec, lcd_read, lcd_write },
75 { 0x3a8001, 0x3ac001, ser_init, ser_quit, ser_exec, ser_read, ser_write },
76 { 0x3ac001, 0x3b0001, mid_init, mid_quit, mid_exec, mid_read, mid_write },
77 { 0x3b0001, 0x3b4001, fdd_init, fdd_quit, fdd_exec, fdd_read, fdd_write },
78 { 0x3b4001, 0x3b8001, snd_init, snd_quit, snd_exec, snd_read, snd_write },
79 { 0x3b8001, 0x3bc001, led_init, led_quit, led_exec, led_read, led_write },
80 { 0x3bc001, 0x3c0001, kbd_init, kbd_quit, kbd_exec, kbd_read, kbd_write }
81};
82
83static hw_t *hw_by_addr(uint32_t addr)
84{
85 for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
86 if (addr >= hw_map[i].addr_beg && addr < hw_map[i].addr_end) {
87 return hw_map + i;
88 }
89 }
90
91 return NULL;
92}
93
94static void hw_init(void)
95{
96 ver("initializing hardware");
97
98 for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
99 hw_map[i].init();
100 }
101}
102
103static void hw_exec(void)
104{
105 for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
106 hw_map[i].exec();
107 }
108}
109
110static uint32_t hw_off(hw_t *hw, uint32_t addr)
111{
112 if ((hw->addr_beg & 0x1) == 0) {
113 return addr - hw->addr_beg;
114 }
115
116 return (addr - hw->addr_beg) / 2;
117}
118
119static void bios_init(const char *bios)
120{
121 ver("loading BIOS file %s", bios);
122
123 SDL_RWops *ops = SDL_RWFromFile(bios, "rb");
124
125 if (ops == NULL) {
126 fail("error while opening BIOS file %s", bios);
127 }
128
129 if (SDL_ReadBE16(ops) != 0x601b) {
130 fail("invalid BIOS file %s", bios);
131 }
132
133 uint32_t text_len = SDL_ReadBE32(ops);
134 uint32_t data_len = SDL_ReadBE32(ops);
135 uint32_t bss_len = SDL_ReadBE32(ops);
136
137 SDL_ReadBE32(ops);
138 SDL_ReadBE32(ops);
139
140 uint32_t text_loc = SDL_ReadBE32(ops);
141
142 SDL_ReadBE16(ops);
143
144 uint32_t data_loc = SDL_ReadBE32(ops);
145 uint32_t bss_loc = SDL_ReadBE32(ops);
146
147 ver("text 0x%x@0x%x data 0x%x@0x%x bss 0x%x@0x%x",
148 text_len, text_loc, data_len, data_loc, bss_len, bss_loc);
149
150 size_t load_len = (size_t)SDL_RWsize(ops) - 36;
151
152 if (load_len != text_len + data_len) {
153 fail("corrupted BIOS file %s", bios);
154 }
155
156 size_t loaded = 0;
157
158 while (loaded < load_len) {
159 size_t n_rd = SDL_RWread(ops, rom_data + loaded, 1, load_len - loaded);
160
161 if (n_rd == 0) {
162 fail("error while reading BIOS file %s", bios);
163 }
164
165 loaded += n_rd;
166 }
167
168 SDL_RWclose(ops);
169}
170
171uint32_t m68k_read_disassembler_8(uint32_t addr)
172{
173 return m68k_read_memory_8(addr);
174}
175
176uint32_t m68k_read_disassembler_16(uint32_t addr)
177{
178 return m68k_read_memory_16(addr);
179}
180
181uint32_t m68k_read_disassembler_32(uint32_t addr)
182{
183 return m68k_read_memory_32(addr);
184}
185
186uint32_t m68k_read_memory_8(uint32_t addr)
187{
188 ver("mem rd 0x%08x:8", addr);
189
190 if (addr >= ram_rd_beg && addr <= ram_rd_end - 1) {
191 return ram_data[addr - RAM_START];
192 }
193
194 if (addr >= rom_rd_beg && addr <= rom_rd_end - 1) {
195 return rom_data[addr - ROM_START];
196 }
197
198 hw_t *hw = hw_by_addr(addr);
199
200 if (hw != NULL) {
201 return hw->read(hw_off(hw, addr), 1);
202 }
203
204 fail("invalid read 0x%08x:8", addr);
205}
206
207uint32_t m68k_read_memory_16(uint32_t addr)
208{
209 ver("mem rd 0x%08x:16", addr);
210
211 if (addr >= ram_rd_beg && addr <= ram_rd_end - 2) {
212 return
213 ((uint32_t)ram_data[addr - RAM_START + 0] << 8) |
214 ((uint32_t)ram_data[addr - RAM_START + 1] << 0);
215 }
216
217 if (addr >= rom_rd_beg && addr <= rom_rd_end - 2) {
218 return
219 ((uint32_t)rom_data[addr - ROM_START + 0] << 8) |
220 ((uint32_t)rom_data[addr - ROM_START + 1] << 0);
221 }
222
223 hw_t *hw = hw_by_addr(addr);
224
225 if (hw != NULL) {
226 return hw->read(hw_off(hw, addr), 2);
227 }
228
229 fail("invalid read 0x%08x:16", addr);
230}
231
232uint32_t m68k_read_memory_32(uint32_t addr)
233{
234 ver("mem rd 0x%08x:32", addr);
235
236 if (reset) {
237 if (addr == 0) {
238 addr += ROM_START;
239 }
240
241 else if (addr == 4) {
242 addr += ROM_START;
243 reset = false;
244 }
245 else {
246 fail("invalid reset sequence");
247 }
248 }
249
250 if (addr >= ram_rd_beg && addr <= ram_rd_end - 4) {
251 return
252 ((uint32_t)ram_data[addr - RAM_START + 0] << 24) |
253 ((uint32_t)ram_data[addr - RAM_START + 1] << 16) |
254 ((uint32_t)ram_data[addr - RAM_START + 2] << 8) |
255 ((uint32_t)ram_data[addr - RAM_START + 3] << 0);
256 }
257
258 if (addr >= rom_rd_beg && addr <= rom_rd_end - 4) {
259 return
260 ((uint32_t)rom_data[addr - ROM_START + 0] << 24) |
261 ((uint32_t)rom_data[addr - ROM_START + 1] << 16) |
262 ((uint32_t)rom_data[addr - ROM_START + 2] << 8) |
263 ((uint32_t)rom_data[addr - ROM_START + 3] << 0);
264 }
265
266 hw_t *hw = hw_by_addr(addr);
267
268 if (hw != NULL) {
269 return hw->read(hw_off(hw, addr), 4);
270 }
271
272 fail("invalid read 0x%08x:32", addr);
273}
274
275void m68k_write_memory_8(uint32_t addr, uint32_t val)
276{
277 ver("mem wr 0x%08x:8 0x%02x", addr, val);
278
279 if (addr >= ram_wr_beg && addr <= ram_wr_end - 1) {
280 ram_data[addr - RAM_START] = (uint8_t)val;
281 return;
282 }
283
284 if (addr >= rom_wr_beg && addr <= rom_wr_end - 1) {
285 // ROM has its BSS section in RAM.
286 ram_data[addr - RAM_START] = (uint8_t)val;
287 return;
288 }
289
290 hw_t *hw = hw_by_addr(addr);
291
292 if (hw != NULL) {
293 hw->write(hw_off(hw, addr), 1, val);
294 return;
295 }
296
297 fail("invalid write 0x%08x:8 0x%02x", addr, val);
298}
299
300void m68k_write_memory_16(uint32_t addr, uint32_t val)
301{
302 ver("mem wr 0x%08x:16 0x%04x", addr, val);
303
304 if (addr >= ram_wr_beg && addr <= ram_wr_end - 2) {
305 ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 8);
306 ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 0);
307 return;
308 }
309
310 if (addr >= rom_wr_beg && addr <= rom_wr_end - 2) {
311 // ROM has its BSS section in RAM.
312 ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 8);
313 ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 0);
314 return;
315 }
316
317 hw_t *hw = hw_by_addr(addr);
318
319 if (hw != NULL) {
320 hw->write(hw_off(hw, addr), 2, val);
321 return;
322 }
323
324 fail("invalid write 0x%08x:16 0x%04x", addr, val);
325}
326
327void m68k_write_memory_32(uint32_t addr, uint32_t val)
328{
329 ver("mem wr 0x%08x:32 0x%08x", addr, val);
330
331 if (addr >= ram_wr_beg && addr <= ram_wr_end - 4) {
332 ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 24);
333 ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 16);
334 ram_data[addr - RAM_START + 2] = (uint8_t)(val >> 8);
335 ram_data[addr - RAM_START + 3] = (uint8_t)(val >> 0);
336 return;
337 }
338
339 if (addr >= rom_wr_beg && addr <= rom_wr_end - 4) {
340 // ROM has its BSS section in RAM.
341 ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 24);
342 ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 16);
343 ram_data[addr - RAM_START + 2] = (uint8_t)(val >> 8);
344 ram_data[addr - RAM_START + 3] = (uint8_t)(val >> 0);
345 return;
346 }
347
348 hw_t *hw = hw_by_addr(addr);
349
350 if (hw != NULL) {
351 hw->write(hw_off(hw, addr), 4, val);
352 return;
353 }
354
355 fail("invalid write 0x%08x:32 0x%08x", addr, val);
356}
357
358void cpu_loop(const char *bios)
359{
360 ver("entering CPU loop");
361
362 hw_init();
363 bios_init(bios);
364
365 ver("starting CPU");
366 m68k_init();
367 m68k_set_cpu_type(M68K_CPU_TYPE_68000);
368 m68k_pulse_reset();
369
370 for (int32_t c = 0; c < 5; ++c) {
371 m68k_execute(CYCLES);
372 hw_exec();
373 }
374}
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