source: buchla-emu/emu/cpu.c@ ba36b71

Last change on this file since ba36b71 was ba36b71, checked in by Thomas Lopatic <thomas@…>, 5 years ago

Fixed memory access control.

  • Property mode set to 100644
File size: 10.8 KB
Line 
1/*
2 * Copyright (C) 2017 The Contributors
3 *
4 * This program is free software: you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation, either version 3 of the License, or (at
7 * your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
13 *
14 * A copy of the GNU General Public License can be found in the file
15 * "gpl-v3.txt" in the top directory of this repository.
16 */
17
18#include <all.h>
19
20#define ver(...) { \
21 if (cpu_verbose) { \
22 SDL_LogVerbose(SDL_LOG_CATEGORY_APPLICATION, __VA_ARGS__); \
23 } \
24}
25
26bool cpu_verbose = false;
27
28#define CYCLES 10
29
30#define VEC_SIZE 0x400
31
32#define RAM_START 0x0
33#define RAM_SIZE 0x100000
34
35#define ROM_START 0x100000
36#define ROM_SIZE 0x10000
37
38typedef void (*hw_init_t)(void);
39typedef void (*hw_quit_t)(void);
40typedef void (*hw_exec_t)(void);
41typedef uint32_t (*hw_read_t)(uint32_t off, int32_t sz);
42typedef void (*hw_write_t)(uint32_t off, int32_t sz, uint32_t val);
43
44typedef struct {
45 uint32_t addr_beg;
46 uint32_t addr_end;
47 hw_init_t init;
48 hw_quit_t quit;
49 hw_exec_t exec;
50 hw_read_t read;
51 hw_write_t write;
52} hw_t;
53
54static bool reset = true;
55
56static uint8_t ram_data[RAM_SIZE];
57static uint8_t rom_data[ROM_SIZE];
58
59static uint32_t ram_ro_beg = 0x1234;
60static uint32_t ram_ro_end = 0x1234;
61static uint32_t ram_rw_beg = 0x1234;
62static uint32_t ram_rw_end = 0x1234;
63
64static uint32_t rom_ro_beg;
65static uint32_t rom_ro_end;
66static uint32_t rom_rw_beg;
67static uint32_t rom_rw_end;
68
69static hw_t hw_map[] = {
70 { 0x180000, 0x200000, fpu_init, fpu_quit, fpu_exec, fpu_read, fpu_write },
71 { 0x200000, 0x280000, vid_init, vid_quit, vid_exec, vid_read, vid_write },
72 { 0x3a0001, 0x3a4001, tim_init, tim_quit, tim_exec, tim_read, tim_write },
73 { 0x3a4001, 0x3a8001, lcd_init, lcd_quit, lcd_exec, lcd_read, lcd_write },
74 { 0x3a8001, 0x3ac001, ser_init, ser_quit, ser_exec, ser_read, ser_write },
75 { 0x3ac001, 0x3b0001, mid_init, mid_quit, mid_exec, mid_read, mid_write },
76 { 0x3b0001, 0x3b4001, fdd_init, fdd_quit, fdd_exec, fdd_read, fdd_write },
77 { 0x3b4001, 0x3b8001, snd_init, snd_quit, snd_exec, snd_read, snd_write },
78 { 0x3b8001, 0x3bc001, led_init, led_quit, led_exec, led_read, led_write },
79 { 0x3bc001, 0x3c0001, kbd_init, kbd_quit, kbd_exec, kbd_read, kbd_write }
80};
81
82static hw_t *hw_by_addr(uint32_t addr)
83{
84 for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
85 if (addr >= hw_map[i].addr_beg && addr < hw_map[i].addr_end) {
86 return hw_map + i;
87 }
88 }
89
90 return NULL;
91}
92
93static void hw_init(void)
94{
95 inf("initializing hardware");
96
97 for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
98 hw_map[i].init();
99 }
100}
101
102static void hw_exec(void)
103{
104 for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
105 hw_map[i].exec();
106 }
107}
108
109static uint32_t hw_off(hw_t *hw, uint32_t addr)
110{
111 if ((hw->addr_beg & 0x1) == 0) {
112 return addr - hw->addr_beg;
113 }
114
115 return (addr - hw->addr_beg) / 2;
116}
117
118static void bios_init(const char *bios)
119{
120 inf("loading BIOS file %s", bios);
121
122 SDL_RWops *ops = SDL_RWFromFile(bios, "rb");
123
124 if (ops == NULL) {
125 fail("error while opening BIOS file %s", bios);
126 }
127
128 if (SDL_ReadBE16(ops) != 0x601b) {
129 fail("invalid BIOS file %s", bios);
130 }
131
132 uint32_t text_len = SDL_ReadBE32(ops);
133 uint32_t data_len = SDL_ReadBE32(ops);
134 uint32_t bss_len = SDL_ReadBE32(ops);
135
136 SDL_ReadBE32(ops);
137 SDL_ReadBE32(ops);
138
139 uint32_t text_loc = SDL_ReadBE32(ops);
140
141 SDL_ReadBE16(ops);
142
143 uint32_t data_loc = SDL_ReadBE32(ops);
144 uint32_t bss_loc = SDL_ReadBE32(ops);
145
146 inf("BIOS text 0x%x:0x%x data 0x%x:0x%x bss 0x%x:0x%x",
147 text_loc, text_len, data_loc, data_len, bss_loc, bss_len);
148
149 size_t load_len = (size_t)SDL_RWsize(ops) - 36;
150
151 if (text_loc != ROM_START || text_loc + text_len != data_loc ||
152 load_len != text_len + data_len || load_len > ROM_SIZE) {
153 fail("invalid BIOS file %s", bios);
154 }
155
156 size_t loaded = 0;
157
158 while (loaded < load_len) {
159 size_t n_rd = SDL_RWread(ops, rom_data + loaded, 1, load_len - loaded);
160
161 if (n_rd == 0) {
162 fail("error while reading BIOS file %s", bios);
163 }
164
165 loaded += n_rd;
166 }
167
168 SDL_RWclose(ops);
169
170 rom_ro_beg = text_loc;
171 rom_ro_end = text_loc + text_len + data_len;
172 rom_rw_beg = bss_loc;
173 rom_rw_end = bss_loc + bss_len;
174
175 ver("rom_ro_beg 0x%08x rom_ro_end 0x%08x", rom_ro_beg, rom_ro_end);
176 ver("rom_rw_beg 0x%08x rom_rw_end 0x%08x", rom_rw_beg, rom_rw_end);
177}
178
179uint32_t m68k_read_disassembler_8(uint32_t addr)
180{
181 return m68k_read_memory_8(addr);
182}
183
184uint32_t m68k_read_disassembler_16(uint32_t addr)
185{
186 return m68k_read_memory_16(addr);
187}
188
189uint32_t m68k_read_disassembler_32(uint32_t addr)
190{
191 return m68k_read_memory_32(addr);
192}
193
194uint32_t m68k_read_memory_8(uint32_t addr)
195{
196 ver("mem rd 0x%08x:8", addr);
197
198 if (addr >= ram_ro_beg && addr <= ram_ro_end - 1) {
199 return ram_data[addr - RAM_START];
200 }
201
202 if (addr >= ram_rw_beg && addr <= ram_rw_end - 1) {
203 return ram_data[addr - RAM_START];
204 }
205
206 if (addr >= rom_ro_beg && addr <= rom_ro_end - 1) {
207 return rom_data[addr - ROM_START];
208 }
209
210 if (addr >= rom_rw_beg && addr <= rom_rw_end - 1) {
211 // ROM has its BSS section in RAM.
212 return ram_data[addr - RAM_START];
213 }
214
215 hw_t *hw = hw_by_addr(addr);
216
217 if (hw != NULL) {
218 return hw->read(hw_off(hw, addr), 1);
219 }
220
221 if (addr <= VEC_SIZE - 1) {
222 return ram_data[addr];
223 }
224
225 fail("invalid read 0x%08x:8", addr);
226}
227
228uint32_t m68k_read_memory_16(uint32_t addr)
229{
230 ver("mem rd 0x%08x:16", addr);
231
232 if (addr >= ram_ro_beg && addr <= ram_ro_end - 2) {
233 return
234 ((uint32_t)ram_data[addr - RAM_START + 0] << 8) |
235 ((uint32_t)ram_data[addr - RAM_START + 1] << 0);
236 }
237
238 if (addr >= ram_rw_beg && addr <= ram_rw_end - 2) {
239 return
240 ((uint32_t)ram_data[addr - RAM_START + 0] << 8) |
241 ((uint32_t)ram_data[addr - RAM_START + 1] << 0);
242 }
243
244 if (addr >= rom_ro_beg && addr <= rom_ro_end - 2) {
245 return
246 ((uint32_t)rom_data[addr - ROM_START + 0] << 8) |
247 ((uint32_t)rom_data[addr - ROM_START + 1] << 0);
248 }
249
250 if (addr >= rom_rw_beg && addr <= rom_rw_end - 2) {
251 // ROM has its BSS section in RAM.
252 return
253 ((uint32_t)ram_data[addr - RAM_START + 0] << 8) |
254 ((uint32_t)ram_data[addr - RAM_START + 1] << 0);
255 }
256
257 hw_t *hw = hw_by_addr(addr);
258
259 if (hw != NULL) {
260 return hw->read(hw_off(hw, addr), 2);
261 }
262
263 if (addr <= VEC_SIZE - 2) {
264 return
265 ((uint32_t)ram_data[addr - 0] << 8) |
266 ((uint32_t)ram_data[addr - 1] << 0);
267 }
268
269 fail("invalid read 0x%08x:16", addr);
270}
271
272uint32_t m68k_read_memory_32(uint32_t addr)
273{
274 ver("mem rd 0x%08x:32", addr);
275
276 if (reset) {
277 if (addr == 0) {
278 addr += ROM_START;
279 }
280
281 else if (addr == 4) {
282 addr += ROM_START;
283 reset = false;
284 }
285 else {
286 fail("invalid reset sequence");
287 }
288 }
289
290 if (addr >= ram_ro_beg && addr <= ram_ro_end - 4) {
291 return
292 ((uint32_t)ram_data[addr - RAM_START + 0] << 24) |
293 ((uint32_t)ram_data[addr - RAM_START + 1] << 16) |
294 ((uint32_t)ram_data[addr - RAM_START + 2] << 8) |
295 ((uint32_t)ram_data[addr - RAM_START + 3] << 0);
296 }
297
298 if (addr >= ram_rw_beg && addr <= ram_rw_end - 4) {
299 return
300 ((uint32_t)ram_data[addr - RAM_START + 0] << 24) |
301 ((uint32_t)ram_data[addr - RAM_START + 1] << 16) |
302 ((uint32_t)ram_data[addr - RAM_START + 2] << 8) |
303 ((uint32_t)ram_data[addr - RAM_START + 3] << 0);
304 }
305
306 if (addr >= rom_ro_beg && addr <= rom_ro_end - 4) {
307 return
308 ((uint32_t)rom_data[addr - ROM_START + 0] << 24) |
309 ((uint32_t)rom_data[addr - ROM_START + 1] << 16) |
310 ((uint32_t)rom_data[addr - ROM_START + 2] << 8) |
311 ((uint32_t)rom_data[addr - ROM_START + 3] << 0);
312 }
313
314 if (addr >= rom_rw_beg && addr <= rom_rw_end - 4) {
315 // ROM has its BSS section in RAM.
316 return
317 ((uint32_t)ram_data[addr - RAM_START + 0] << 24) |
318 ((uint32_t)ram_data[addr - RAM_START + 1] << 16) |
319 ((uint32_t)ram_data[addr - RAM_START + 2] << 8) |
320 ((uint32_t)ram_data[addr - RAM_START + 3] << 0);
321 }
322
323 hw_t *hw = hw_by_addr(addr);
324
325 if (hw != NULL) {
326 return hw->read(hw_off(hw, addr), 4);
327 }
328
329 if (addr <= VEC_SIZE - 4) {
330 return
331 ((uint32_t)ram_data[addr + 0] << 24) |
332 ((uint32_t)ram_data[addr + 1] << 16) |
333 ((uint32_t)ram_data[addr + 2] << 8) |
334 ((uint32_t)ram_data[addr + 3] << 0);
335 }
336
337 fail("invalid read 0x%08x:32", addr);
338}
339
340void m68k_write_memory_8(uint32_t addr, uint32_t val)
341{
342 ver("mem wr 0x%08x:8 0x%02x", addr, val);
343
344 if (addr >= ram_rw_beg && addr <= ram_rw_end - 1) {
345 ram_data[addr - RAM_START] = (uint8_t)val;
346 return;
347 }
348
349 if (addr >= rom_rw_beg && addr <= rom_rw_end - 1) {
350 // ROM has its BSS section in RAM.
351 ram_data[addr - RAM_START] = (uint8_t)val;
352 return;
353 }
354
355 hw_t *hw = hw_by_addr(addr);
356
357 if (hw != NULL) {
358 hw->write(hw_off(hw, addr), 1, val);
359 return;
360 }
361
362 if (addr <= VEC_SIZE - 1) {
363 ram_data[addr] = (uint8_t)val;
364 return;
365 }
366
367 fail("invalid write 0x%08x:8 0x%02x", addr, val);
368}
369
370void m68k_write_memory_16(uint32_t addr, uint32_t val)
371{
372 ver("mem wr 0x%08x:16 0x%04x", addr, val);
373
374 if (addr >= ram_rw_beg && addr <= ram_rw_end - 2) {
375 ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 8);
376 ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 0);
377 return;
378 }
379
380 if (addr >= rom_rw_beg && addr <= rom_rw_end - 2) {
381 // ROM has its BSS section in RAM.
382 ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 8);
383 ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 0);
384 return;
385 }
386
387 hw_t *hw = hw_by_addr(addr);
388
389 if (hw != NULL) {
390 hw->write(hw_off(hw, addr), 2, val);
391 return;
392 }
393
394 if (addr <= VEC_SIZE - 2) {
395 ram_data[addr + 0] = (uint8_t)(val >> 8);
396 ram_data[addr + 1] = (uint8_t)(val >> 0);
397 return;
398 }
399
400 fail("invalid write 0x%08x:16 0x%04x", addr, val);
401}
402
403void m68k_write_memory_32(uint32_t addr, uint32_t val)
404{
405 ver("mem wr 0x%08x:32 0x%08x", addr, val);
406
407 if (addr >= ram_rw_beg && addr <= ram_rw_end - 4) {
408 ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 24);
409 ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 16);
410 ram_data[addr - RAM_START + 2] = (uint8_t)(val >> 8);
411 ram_data[addr - RAM_START + 3] = (uint8_t)(val >> 0);
412 return;
413 }
414
415 if (addr >= rom_rw_beg && addr <= rom_rw_end - 4) {
416 // ROM has its BSS section in RAM.
417 ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 24);
418 ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 16);
419 ram_data[addr - RAM_START + 2] = (uint8_t)(val >> 8);
420 ram_data[addr - RAM_START + 3] = (uint8_t)(val >> 0);
421 return;
422 }
423
424 hw_t *hw = hw_by_addr(addr);
425
426 if (hw != NULL) {
427 hw->write(hw_off(hw, addr), 4, val);
428 return;
429 }
430
431 if (addr <= VEC_SIZE - 4) {
432 ram_data[addr + 0] = (uint8_t)(val >> 24);
433 ram_data[addr + 1] = (uint8_t)(val >> 16);
434 ram_data[addr + 2] = (uint8_t)(val >> 8);
435 ram_data[addr + 3] = (uint8_t)(val >> 0);
436 return;
437 }
438
439 fail("invalid write 0x%08x:32 0x%08x", addr, val);
440}
441
442void cpu_loop(const char *bios)
443{
444 hw_init();
445 bios_init(bios);
446
447 inf("entering CPU loop");
448 m68k_init();
449 m68k_set_cpu_type(M68K_CPU_TYPE_68000);
450 m68k_pulse_reset();
451
452 for (int32_t c = 0; c < 5; ++c) {
453 m68k_execute(CYCLES);
454 hw_exec();
455 }
456}
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