1 | /*
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2 | * Copyright (C) 2017 The Contributors
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3 | *
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4 | * This program is free software: you can redistribute it and/or modify
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5 | * it under the terms of the GNU General Public License as published by
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6 | * the Free Software Foundation, either version 3 of the License, or (at
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7 | * your option) any later version.
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8 | *
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9 | * This program is distributed in the hope that it will be useful, but
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10 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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12 | * General Public License for more details.
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13 | *
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14 | * A copy of the GNU General Public License can be found in the file
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15 | * "gpl-v3.txt" in the top directory of this repository.
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16 | */
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17 |
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18 | #include <all.h>
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19 |
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20 | #define ver(...) { \
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21 | if (cpu_verbose) { \
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22 | SDL_LogVerbose(SDL_LOG_CATEGORY_APPLICATION, __VA_ARGS__); \
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23 | } \
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24 | }
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25 |
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26 | bool cpu_verbose = false;
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27 |
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28 | #define CYCLES 10
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29 |
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30 | #define RAM_START 0x0
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31 | #define RAM_SIZE 0x100000
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32 |
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33 | #define ROM_START 0x100000
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34 | #define ROM_SIZE 0x10000
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35 |
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36 | #define RESET_SP ROM_START
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37 | #define RESET_PC ROM_START
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38 |
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39 | typedef void (*hw_init_t)(void);
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40 | typedef void (*hw_quit_t)(void);
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41 | typedef void (*hw_exec_t)(void);
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42 | typedef uint32_t (*hw_read_t)(uint32_t off, int32_t sz);
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43 | typedef void (*hw_write_t)(uint32_t off, int32_t sz, uint32_t val);
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44 |
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45 | typedef struct {
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46 | uint32_t addr_beg;
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47 | uint32_t addr_end;
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48 | hw_init_t init;
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49 | hw_quit_t quit;
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50 | hw_exec_t exec;
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51 | hw_read_t read;
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52 | hw_write_t write;
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53 | } hw_t;
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54 |
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55 | static bool reset = true;
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56 |
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57 | static uint8_t ram_data[RAM_SIZE];
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58 | static uint8_t rom_data[ROM_SIZE];
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59 |
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60 | static uint32_t ram_rd_beg;
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61 | static uint32_t ram_rd_end;
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62 | static uint32_t ram_wr_beg;
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63 | static uint32_t ram_wr_end;
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64 |
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65 | static uint32_t rom_rd_beg;
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66 | static uint32_t rom_rd_end;
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67 | static uint32_t rom_wr_beg;
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68 | static uint32_t rom_wr_end;
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69 |
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70 | static hw_t hw_map[] = {
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71 | { 0x180000, 0x200000, fpu_init, fpu_quit, fpu_exec, fpu_read, fpu_write },
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72 | { 0x200000, 0x280000, vid_init, vid_quit, vid_exec, vid_read, vid_write },
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73 | { 0x3a0001, 0x3a4001, tim_init, tim_quit, tim_exec, tim_read, tim_write },
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74 | { 0x3a4001, 0x3a8001, lcd_init, lcd_quit, lcd_exec, lcd_read, lcd_write },
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75 | { 0x3a8001, 0x3ac001, ser_init, ser_quit, ser_exec, ser_read, ser_write },
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76 | { 0x3ac001, 0x3b0001, mid_init, mid_quit, mid_exec, mid_read, mid_write },
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77 | { 0x3b0001, 0x3b4001, fdd_init, fdd_quit, fdd_exec, fdd_read, fdd_write },
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78 | { 0x3b4001, 0x3b8001, snd_init, snd_quit, snd_exec, snd_read, snd_write },
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79 | { 0x3b8001, 0x3bc001, led_init, led_quit, led_exec, led_read, led_write },
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80 | { 0x3bc001, 0x3c0001, kbd_init, kbd_quit, kbd_exec, kbd_read, kbd_write }
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81 | };
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82 |
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83 | static hw_t *hw_by_addr(uint32_t addr)
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84 | {
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85 | for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
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86 | if (addr >= hw_map[i].addr_beg && addr < hw_map[i].addr_end) {
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87 | return hw_map + i;
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88 | }
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89 | }
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90 |
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91 | return NULL;
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92 | }
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93 |
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94 | static void hw_init(void)
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95 | {
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96 | for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
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97 | hw_map[i].init();
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98 | }
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99 | }
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100 |
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101 | static void hw_exec(void)
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102 | {
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103 | for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
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104 | hw_map[i].exec();
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105 | }
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106 | }
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107 |
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108 | static uint32_t hw_off(hw_t *hw, uint32_t addr)
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109 | {
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110 | if ((hw->addr_beg & 0x1) == 0) {
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111 | return addr - hw->addr_beg;
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112 | }
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113 |
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114 | return (addr - hw->addr_beg) / 2;
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115 | }
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116 |
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117 | uint32_t m68k_read_disassembler_8(uint32_t addr)
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118 | {
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119 | return m68k_read_memory_8(addr);
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120 | }
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121 |
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122 | uint32_t m68k_read_disassembler_16(uint32_t addr)
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123 | {
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124 | return m68k_read_memory_16(addr);
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125 | }
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126 |
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127 | uint32_t m68k_read_disassembler_32(uint32_t addr)
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128 | {
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129 | return m68k_read_memory_32(addr);
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130 | }
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131 |
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132 | uint32_t m68k_read_memory_8(uint32_t addr)
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133 | {
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134 | ver("mem rd 0x%08x:8", addr);
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135 |
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136 | if (addr >= ram_rd_beg && addr <= ram_rd_end - 1) {
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137 | return ram_data[addr - RAM_START];
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138 | }
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139 |
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140 | if (addr >= rom_rd_beg && addr <= rom_rd_end - 1) {
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141 | return rom_data[addr - ROM_START];
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142 | }
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143 |
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144 | hw_t *hw = hw_by_addr(addr);
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145 |
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146 | if (hw != NULL) {
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147 | return hw->read(hw_off(hw, addr), 1);
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148 | }
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149 |
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150 | fail("invalid read 0x%08x:8", addr);
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151 | }
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152 |
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153 | uint32_t m68k_read_memory_16(uint32_t addr)
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154 | {
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155 | ver("mem rd 0x%08x:16", addr);
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156 |
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157 | if (addr >= ram_rd_beg && addr <= ram_rd_end - 2) {
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158 | return
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159 | ((uint32_t)ram_data[addr - RAM_START + 0] << 8) |
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160 | ((uint32_t)ram_data[addr - RAM_START + 1] << 0);
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161 | }
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162 |
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163 | if (addr >= rom_rd_beg && addr <= rom_rd_end - 2) {
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164 | return
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165 | ((uint32_t)rom_data[addr - ROM_START + 0] << 8) |
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166 | ((uint32_t)rom_data[addr - ROM_START + 1] << 0);
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167 | }
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168 |
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169 | hw_t *hw = hw_by_addr(addr);
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170 |
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171 | if (hw != NULL) {
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172 | return hw->read(hw_off(hw, addr), 2);
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173 | }
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174 |
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175 | fail("invalid read 0x%08x:16", addr);
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176 | }
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177 |
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178 | uint32_t m68k_read_memory_32(uint32_t addr)
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179 | {
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180 | ver("mem rd 0x%08x:32", addr);
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181 |
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182 | if (reset) {
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183 | if (addr == 0) {
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184 | return RESET_SP;
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185 | }
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186 |
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187 | if (addr == 4) {
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188 | reset = false;
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189 | return RESET_PC;
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190 | }
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191 |
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192 | fail("invalid reset sequence");
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193 | }
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194 |
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195 | if (addr >= ram_rd_beg && addr <= ram_rd_end - 4) {
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196 | return
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197 | ((uint32_t)ram_data[addr - RAM_START + 0] << 24) |
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198 | ((uint32_t)ram_data[addr - RAM_START + 1] << 16) |
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199 | ((uint32_t)ram_data[addr - RAM_START + 2] << 8) |
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200 | ((uint32_t)ram_data[addr - RAM_START + 3] << 0);
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201 | }
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202 |
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203 | if (addr >= rom_rd_beg && addr <= rom_rd_end - 4) {
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204 | return
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205 | ((uint32_t)rom_data[addr - ROM_START + 0] << 24) |
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206 | ((uint32_t)rom_data[addr - ROM_START + 1] << 16) |
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207 | ((uint32_t)rom_data[addr - ROM_START + 2] << 8) |
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208 | ((uint32_t)rom_data[addr - ROM_START + 3] << 0);
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209 | }
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210 |
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211 | hw_t *hw = hw_by_addr(addr);
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212 |
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213 | if (hw != NULL) {
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214 | return hw->read(hw_off(hw, addr), 4);
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215 | }
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216 |
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217 | fail("invalid read 0x%08x:32", addr);
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218 | }
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219 |
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220 | void m68k_write_memory_8(uint32_t addr, uint32_t val)
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221 | {
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222 | ver("mem wr 0x%08x:8 0x%02x", addr, val);
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223 |
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224 | if (addr >= ram_wr_beg && addr <= ram_wr_end - 1) {
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225 | ram_data[addr - RAM_START] = (uint8_t)val;
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226 | return;
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227 | }
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228 |
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229 | if (addr >= rom_wr_beg && addr <= rom_wr_end - 1) {
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230 | // ROM has its BSS section in RAM.
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231 | ram_data[addr - RAM_START] = (uint8_t)val;
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232 | return;
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233 | }
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234 |
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235 | hw_t *hw = hw_by_addr(addr);
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236 |
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237 | if (hw != NULL) {
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238 | hw->write(hw_off(hw, addr), 1, val);
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239 | return;
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240 | }
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241 |
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242 | fail("invalid write 0x%08x:8 0x%02x", addr, val);
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243 | }
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244 |
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245 | void m68k_write_memory_16(uint32_t addr, uint32_t val)
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246 | {
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247 | ver("mem wr 0x%08x:16 0x%04x", addr, val);
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248 |
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249 | if (addr >= ram_wr_beg && addr <= ram_wr_end - 2) {
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250 | ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 8);
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251 | ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 0);
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252 | return;
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253 | }
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254 |
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255 | if (addr >= rom_wr_beg && addr <= rom_wr_end - 2) {
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256 | // ROM has its BSS section in RAM.
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257 | ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 8);
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258 | ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 0);
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259 | return;
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260 | }
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261 |
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262 | hw_t *hw = hw_by_addr(addr);
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263 |
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264 | if (hw != NULL) {
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265 | hw->write(hw_off(hw, addr), 2, val);
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266 | return;
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267 | }
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268 |
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269 | fail("invalid write 0x%08x:16 0x%04x", addr, val);
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270 | }
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271 |
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272 | void m68k_write_memory_32(uint32_t addr, uint32_t val)
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273 | {
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274 | ver("mem wr 0x%08x:32 0x%08x", addr, val);
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275 |
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276 | if (addr >= ram_wr_beg && addr <= ram_wr_end - 4) {
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277 | ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 24);
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278 | ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 16);
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279 | ram_data[addr - RAM_START + 2] = (uint8_t)(val >> 8);
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280 | ram_data[addr - RAM_START + 3] = (uint8_t)(val >> 0);
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281 | return;
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282 | }
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283 |
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284 | if (addr >= rom_wr_beg && addr <= rom_wr_end - 4) {
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285 | // ROM has its BSS section in RAM.
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286 | ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 24);
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287 | ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 16);
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288 | ram_data[addr - RAM_START + 2] = (uint8_t)(val >> 8);
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289 | ram_data[addr - RAM_START + 3] = (uint8_t)(val >> 0);
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290 | return;
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291 | }
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292 |
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293 | hw_t *hw = hw_by_addr(addr);
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294 |
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295 | if (hw != NULL) {
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296 | hw->write(hw_off(hw, addr), 4, val);
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297 | return;
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298 | }
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299 |
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300 | fail("invalid write 0x%08x:32 0x%08x", addr, val);
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301 | }
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302 |
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303 | void cpu_loop(void)
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304 | {
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305 | ver("initializing hardware");
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306 | hw_init();
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307 |
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308 | ver("starting CPU");
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309 | m68k_init();
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310 | m68k_set_cpu_type(M68K_CPU_TYPE_68000);
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311 | m68k_pulse_reset();
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312 |
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313 | for (int32_t c = 0; c < 5; ++c) {
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314 | m68k_execute(CYCLES);
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315 | hw_exec();
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316 | }
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317 | }
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