Changeset ba36b71 in buchla-emu
- Timestamp:
- 07/20/2017 07:09:33 PM (7 years ago)
- Branches:
- master
- Children:
- 555b171
- Parents:
- 51b6cfd
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
emu/cpu.c
r51b6cfd rba36b71 28 28 #define CYCLES 10 29 29 30 #define VEC_SIZE 0x400 31 30 32 #define RAM_START 0x0 31 33 #define RAM_SIZE 0x100000 … … 55 57 static uint8_t rom_data[ROM_SIZE]; 56 58 57 static uint32_t ram_r d_beg = 0x10000000;58 static uint32_t ram_r d_end = 0x10000000;59 static uint32_t ram_ wr_beg = 0x10000000;60 static uint32_t ram_ wr_end = 0x10000000;61 62 static uint32_t rom_r d_beg;63 static uint32_t rom_r d_end;64 static uint32_t rom_ wr_beg;65 static uint32_t rom_ wr_end;59 static uint32_t ram_ro_beg = 0x1234; 60 static uint32_t ram_ro_end = 0x1234; 61 static uint32_t ram_rw_beg = 0x1234; 62 static uint32_t ram_rw_end = 0x1234; 63 64 static uint32_t rom_ro_beg; 65 static uint32_t rom_ro_end; 66 static uint32_t rom_rw_beg; 67 static uint32_t rom_rw_end; 66 68 67 69 static hw_t hw_map[] = { … … 91 93 static void hw_init(void) 92 94 { 93 ver("initializing hardware");95 inf("initializing hardware"); 94 96 95 97 for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) { … … 116 118 static void bios_init(const char *bios) 117 119 { 118 ver("loading BIOS file %s", bios);120 inf("loading BIOS file %s", bios); 119 121 120 122 SDL_RWops *ops = SDL_RWFromFile(bios, "rb"); … … 142 144 uint32_t bss_loc = SDL_ReadBE32(ops); 143 145 144 ver("text 0x%x@0x%x data 0x%x@0x%x bss 0x%x@0x%x",145 text_l en, text_loc, data_len, data_loc, bss_len, bss_loc);146 inf("BIOS text 0x%x:0x%x data 0x%x:0x%x bss 0x%x:0x%x", 147 text_loc, text_len, data_loc, data_len, bss_loc, bss_len); 146 148 147 149 size_t load_len = (size_t)SDL_RWsize(ops) - 36; 148 150 149 if (load_len != text_len + data_len) { 150 fail("corrupted BIOS file %s", bios); 151 if (text_loc != ROM_START || text_loc + text_len != data_loc || 152 load_len != text_len + data_len || load_len > ROM_SIZE) { 153 fail("invalid BIOS file %s", bios); 151 154 } 152 155 … … 164 167 165 168 SDL_RWclose(ops); 169 170 rom_ro_beg = text_loc; 171 rom_ro_end = text_loc + text_len + data_len; 172 rom_rw_beg = bss_loc; 173 rom_rw_end = bss_loc + bss_len; 174 175 ver("rom_ro_beg 0x%08x rom_ro_end 0x%08x", rom_ro_beg, rom_ro_end); 176 ver("rom_rw_beg 0x%08x rom_rw_end 0x%08x", rom_rw_beg, rom_rw_end); 166 177 } 167 178 … … 185 196 ver("mem rd 0x%08x:8", addr); 186 197 187 if (addr >= ram_r d_beg && addr <= ram_rd_end - 1) {198 if (addr >= ram_ro_beg && addr <= ram_ro_end - 1) { 188 199 return ram_data[addr - RAM_START]; 189 200 } 190 201 191 if (addr >= rom_rd_beg && addr <= rom_rd_end - 1) { 202 if (addr >= ram_rw_beg && addr <= ram_rw_end - 1) { 203 return ram_data[addr - RAM_START]; 204 } 205 206 if (addr >= rom_ro_beg && addr <= rom_ro_end - 1) { 192 207 return rom_data[addr - ROM_START]; 193 208 } 194 209 210 if (addr >= rom_rw_beg && addr <= rom_rw_end - 1) { 211 // ROM has its BSS section in RAM. 212 return ram_data[addr - RAM_START]; 213 } 214 195 215 hw_t *hw = hw_by_addr(addr); 196 216 … … 199 219 } 200 220 221 if (addr <= VEC_SIZE - 1) { 222 return ram_data[addr]; 223 } 224 201 225 fail("invalid read 0x%08x:8", addr); 202 226 } … … 206 230 ver("mem rd 0x%08x:16", addr); 207 231 208 if (addr >= ram_r d_beg && addr <= ram_rd_end - 2) {232 if (addr >= ram_ro_beg && addr <= ram_ro_end - 2) { 209 233 return 210 234 ((uint32_t)ram_data[addr - RAM_START + 0] << 8) | … … 212 236 } 213 237 214 if (addr >= rom_rd_beg && addr <= rom_rd_end - 2) { 238 if (addr >= ram_rw_beg && addr <= ram_rw_end - 2) { 239 return 240 ((uint32_t)ram_data[addr - RAM_START + 0] << 8) | 241 ((uint32_t)ram_data[addr - RAM_START + 1] << 0); 242 } 243 244 if (addr >= rom_ro_beg && addr <= rom_ro_end - 2) { 215 245 return 216 246 ((uint32_t)rom_data[addr - ROM_START + 0] << 8) | … … 218 248 } 219 249 250 if (addr >= rom_rw_beg && addr <= rom_rw_end - 2) { 251 // ROM has its BSS section in RAM. 252 return 253 ((uint32_t)ram_data[addr - RAM_START + 0] << 8) | 254 ((uint32_t)ram_data[addr - RAM_START + 1] << 0); 255 } 256 220 257 hw_t *hw = hw_by_addr(addr); 221 258 222 259 if (hw != NULL) { 223 260 return hw->read(hw_off(hw, addr), 2); 261 } 262 263 if (addr <= VEC_SIZE - 2) { 264 return 265 ((uint32_t)ram_data[addr - 0] << 8) | 266 ((uint32_t)ram_data[addr - 1] << 0); 224 267 } 225 268 … … 245 288 } 246 289 247 if (addr >= ram_r d_beg && addr <= ram_rd_end - 4) {290 if (addr >= ram_ro_beg && addr <= ram_ro_end - 4) { 248 291 return 249 292 ((uint32_t)ram_data[addr - RAM_START + 0] << 24) | … … 253 296 } 254 297 255 if (addr >= rom_rd_beg && addr <= rom_rd_end - 4) { 298 if (addr >= ram_rw_beg && addr <= ram_rw_end - 4) { 299 return 300 ((uint32_t)ram_data[addr - RAM_START + 0] << 24) | 301 ((uint32_t)ram_data[addr - RAM_START + 1] << 16) | 302 ((uint32_t)ram_data[addr - RAM_START + 2] << 8) | 303 ((uint32_t)ram_data[addr - RAM_START + 3] << 0); 304 } 305 306 if (addr >= rom_ro_beg && addr <= rom_ro_end - 4) { 256 307 return 257 308 ((uint32_t)rom_data[addr - ROM_START + 0] << 24) | … … 261 312 } 262 313 314 if (addr >= rom_rw_beg && addr <= rom_rw_end - 4) { 315 // ROM has its BSS section in RAM. 316 return 317 ((uint32_t)ram_data[addr - RAM_START + 0] << 24) | 318 ((uint32_t)ram_data[addr - RAM_START + 1] << 16) | 319 ((uint32_t)ram_data[addr - RAM_START + 2] << 8) | 320 ((uint32_t)ram_data[addr - RAM_START + 3] << 0); 321 } 322 263 323 hw_t *hw = hw_by_addr(addr); 264 324 … … 267 327 } 268 328 329 if (addr <= VEC_SIZE - 4) { 330 return 331 ((uint32_t)ram_data[addr + 0] << 24) | 332 ((uint32_t)ram_data[addr + 1] << 16) | 333 ((uint32_t)ram_data[addr + 2] << 8) | 334 ((uint32_t)ram_data[addr + 3] << 0); 335 } 336 269 337 fail("invalid read 0x%08x:32", addr); 270 338 } … … 274 342 ver("mem wr 0x%08x:8 0x%02x", addr, val); 275 343 276 if (addr >= ram_ wr_beg && addr <= ram_wr_end - 1) {344 if (addr >= ram_rw_beg && addr <= ram_rw_end - 1) { 277 345 ram_data[addr - RAM_START] = (uint8_t)val; 278 346 return; 279 347 } 280 348 281 if (addr >= rom_ wr_beg && addr <= rom_wr_end - 1) {349 if (addr >= rom_rw_beg && addr <= rom_rw_end - 1) { 282 350 // ROM has its BSS section in RAM. 283 351 ram_data[addr - RAM_START] = (uint8_t)val; … … 292 360 } 293 361 362 if (addr <= VEC_SIZE - 1) { 363 ram_data[addr] = (uint8_t)val; 364 return; 365 } 366 294 367 fail("invalid write 0x%08x:8 0x%02x", addr, val); 295 368 } … … 299 372 ver("mem wr 0x%08x:16 0x%04x", addr, val); 300 373 301 if (addr >= ram_ wr_beg && addr <= ram_wr_end - 2) {374 if (addr >= ram_rw_beg && addr <= ram_rw_end - 2) { 302 375 ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 8); 303 376 ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 0); … … 305 378 } 306 379 307 if (addr >= rom_ wr_beg && addr <= rom_wr_end - 2) {380 if (addr >= rom_rw_beg && addr <= rom_rw_end - 2) { 308 381 // ROM has its BSS section in RAM. 309 382 ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 8); … … 319 392 } 320 393 394 if (addr <= VEC_SIZE - 2) { 395 ram_data[addr + 0] = (uint8_t)(val >> 8); 396 ram_data[addr + 1] = (uint8_t)(val >> 0); 397 return; 398 } 399 321 400 fail("invalid write 0x%08x:16 0x%04x", addr, val); 322 401 } … … 326 405 ver("mem wr 0x%08x:32 0x%08x", addr, val); 327 406 328 if (addr >= ram_ wr_beg && addr <= ram_wr_end - 4) {407 if (addr >= ram_rw_beg && addr <= ram_rw_end - 4) { 329 408 ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 24); 330 409 ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 16); … … 334 413 } 335 414 336 if (addr >= rom_ wr_beg && addr <= rom_wr_end - 4) {415 if (addr >= rom_rw_beg && addr <= rom_rw_end - 4) { 337 416 // ROM has its BSS section in RAM. 338 417 ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 24); … … 350 429 } 351 430 431 if (addr <= VEC_SIZE - 4) { 432 ram_data[addr + 0] = (uint8_t)(val >> 24); 433 ram_data[addr + 1] = (uint8_t)(val >> 16); 434 ram_data[addr + 2] = (uint8_t)(val >> 8); 435 ram_data[addr + 3] = (uint8_t)(val >> 0); 436 return; 437 } 438 352 439 fail("invalid write 0x%08x:32 0x%08x", addr, val); 353 440 } … … 355 442 void cpu_loop(const char *bios) 356 443 { 357 ver("entering CPU loop");358 359 444 hw_init(); 360 445 bios_init(bios); 361 446 362 ver("starting CPU");447 inf("entering CPU loop"); 363 448 m68k_init(); 364 449 m68k_set_cpu_type(M68K_CPU_TYPE_68000);
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