[a06aa8b] | 1 | /*
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| 2 | * Copyright (C) 2017 The Contributors
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| 3 | *
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| 4 | * This program is free software: you can redistribute it and/or modify
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| 5 | * it under the terms of the GNU General Public License as published by
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| 6 | * the Free Software Foundation, either version 3 of the License, or (at
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| 7 | * your option) any later version.
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| 8 | *
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| 9 | * This program is distributed in the hope that it will be useful, but
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| 10 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 12 | * General Public License for more details.
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| 13 | *
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| 14 | * A copy of the GNU General Public License can be found in the file
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[2147e53] | 15 | * "gpl.txt" in the top directory of this repository.
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[a06aa8b] | 16 | */
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| 17 |
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| 18 | #include <all.h>
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| 19 |
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[4c71d39] | 20 | #define ver(...) _ver(mid_verbose, 0, __VA_ARGS__)
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| 21 | #define ver2(...) _ver(mid_verbose, 1, __VA_ARGS__)
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| 22 | #define ver3(...) _ver(mid_verbose, 2, __VA_ARGS__)
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[a06aa8b] | 23 |
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[4c71d39] | 24 | int32_t mid_verbose = 0;
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[a06aa8b] | 25 |
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[c5b6c90] | 26 | #define REG_IER_ISR 0
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| 27 | #define REG_CFR_SR 1
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| 28 | #define REG_CDR_TBR 2
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| 29 | #define REG_TDR_RDR 3
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| 30 |
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[a06aa8b] | 31 | void mid_init(void)
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| 32 | {
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| 33 | ver("mid init");
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| 34 | }
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| 35 |
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| 36 | void mid_quit(void)
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| 37 | {
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| 38 | ver("mid quit");
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| 39 | }
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| 40 |
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[3c30832] | 41 | bool mid_exec(void)
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[a06aa8b] | 42 | {
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[4c71d39] | 43 | ver3("mid exec");
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[3c30832] | 44 | return false;
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[a06aa8b] | 45 | }
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| 46 |
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| 47 | uint32_t mid_read(uint32_t off, int32_t sz)
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| 48 | {
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[4c71d39] | 49 | ver2("mid rd %u:%d", off, sz * 8);
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[a06aa8b] | 50 | return 0;
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| 51 | }
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| 52 |
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| 53 | void mid_write(uint32_t off, int32_t sz, uint32_t val)
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| 54 | {
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[4c71d39] | 55 | ver2("mid wr %u:%d 0x%0*x", off, sz * 8, sz * 2, val);
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[c5b6c90] | 56 |
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| 57 | if (sz != 1 || off > 7) {
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| 58 | fail("invalid mid wr %u:%d", off, sz * 8);
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| 59 | }
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| 60 |
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| 61 | int32_t rg = (int32_t)(off % 4);
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| 62 | int32_t un = (int32_t)(off / 4);
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| 63 |
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| 64 | switch (rg) {
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| 65 | case REG_CFR_SR:
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| 66 | ver2("CFR[%d] 0x%02x", un, val);
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| 67 |
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| 68 | if (un == 1) {
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| 69 | fdd_set_side((int32_t)val & 0x01);
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| 70 | }
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| 71 | else {
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| 72 | fdd_set_sel((int32_t)val & 0x01);
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| 73 | }
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| 74 |
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| 75 | break;
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| 76 |
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| 77 | default:
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| 78 | break;
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| 79 | }
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[a06aa8b] | 80 | }
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