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Changeset 4f508e6 in buchla-68k for ram/execins.s
- Timestamp:
- 07/01/2017 02:34:46 PM (7 years ago)
- Branches:
- master
- Children:
- 08e1da1
- Parents:
- f40a309
- File:
-
- 1 edited
-
ram/execins.s (modified) (2 diffs)
Legend:
- Unmodified
- Added
- Removed
-
ram/execins.s
rf40a309 r4f508e6 1 *------------------------------------------------------------------------------2 *execins.s -- execute an instrument selection3 *Version 9 -- 1988-09-09 -- D.N. Lynx Crowe4 * 5 *Hand optimized C object code from: execins.c -- ver 2 -- 1988-06-296 *------------------------------------------------------------------------------7 * 1 | ------------------------------------------------------------------------------ 2 | execins.s -- execute an instrument selection 3 | Version 9 -- 1988-09-09 -- D.N. Lynx Crowe 4 5 | Hand optimized C object code from: execins.c -- ver 2 -- 1988-06-29 6 | ------------------------------------------------------------------------------ 7 8 8 .text 9 * 10 DOUBLED .equ 1 *double output to WS table11 * 9 10 DOUBLED = 1 | double output to WS table 11 12 12 .xdef _execins 13 * 13 14 14 .xref _clrvce 15 15 .xref _execkey 16 * 16 17 17 .xref _io_fpu 18 18 .xref _instmod … … 20 20 .xref _idefs 21 21 .xref _vbufs 22 * 23 *register equates24 *----------------25 SYNC .equD426 OLDSR .equD527 VCE .equD728 * 29 IP .equA530 P1 .equA431 P2 .equA332 * 33 P3 .equA234 P4 .equA135 * 36 *parameter offsets37 *-----------------38 VOICE .equ839 INS .equ1040 TAG .equ1241 * 42 .page 43 * 44 _execins: link A6,#0 *link stack frames45 movem.l D3-VCE/P2-IP,-(sp) *preserve registers46 move.w VOICE(A6),VCE *get voice number47 move.w VCE,D0 *calculate IP48 add.w D0,D0 *...49 add.w D0,D0 *...50 lea vibtabl,A0 *...51 movea.l 0(A0,D0.W),IP *...52 add.l #_vbufs,IP *...53 move.w VCE,(sp) *clrvce(vce)54 jsr _clrvce *...55 tst.w TAG(A6) *if (tag) {56 beq L2 *...57 * 58 move.l IP,P1 *p1 = ip;59 move.w INS(A6),D0 *p2 = &idefs[ins]60 add.w D0,D0 *...61 add.w D0,D0 *...62 lea vibtabl,A0 *...63 movea.l 0(A0,D0.W),P2 *...64 add.l #_idefs,P2 *...65 move.w #1968,D0 *set move count66 * 67 L6: move.w (P2)+,(P1)+ *load voice buffer68 dbra D0,L6 *...69 * 70 .page 71 * 72 move.w VCE,D0 *calculate FPU offset for voice73 move.w #9,D1 *...74 asl.w D1,D0 *...75 asl.w #1,D0 *...76 ext.l D0 *...77 move.l D0,P1 *...78 move.l D0,P3 *...79 add.l #_io_fpu,P1 *point P1 at FPU WS A80 add.l # $202,P1 *...81 lea 1778(IP),P2 *point P2 at instdef WS A82 add.l #_io_fpu,P3 *point P3 at FPU WS B83 add.l #2,P3 *...84 lea 2858(IP),P4 *point P4 at instdef WS B85 move.w #253,D0 *setup move count86 * 22 23 | register equates 24 | ---------------- 25 SYNC = D4 26 OLDSR = D5 27 VCE = D7 28 29 IP = A5 30 P1 = A4 31 P2 = A3 32 33 P3 = A2 34 P4 = A1 35 36 | parameter offsets 37 | ----------------- 38 VOICE = 8 39 INS = 10 40 TAG = 12 41 42 .page 43 44 _execins: link A6,#0 | link stack frames 45 movem.l D3-VCE/P2-IP,-(sp) | preserve registers 46 move.w VOICE(A6),VCE | get voice number 47 move.w VCE,D0 | calculate IP 48 add.w D0,D0 | ... 49 add.w D0,D0 | ... 50 lea vibtabl,A0 | ... 51 movea.l 0(A0,D0.W),IP | ... 52 add.l #_vbufs,IP | ... 53 move.w VCE,(sp) | clrvce(vce) 54 jsr _clrvce | ... 55 tst.w TAG(A6) | if (tag) { 56 beq L2 | ... 57 58 move.l IP,P1 | p1 = ip; 59 move.w INS(A6),D0 | p2 = &idefs[ins] 60 add.w D0,D0 | ... 61 add.w D0,D0 | ... 62 lea vibtabl,A0 | ... 63 movea.l 0(A0,D0.W),P2 | ... 64 add.l #_idefs,P2 | ... 65 move.w #1968,D0 | set move count 66 67 L6: move.w (P2)+,(P1)+ | load voice buffer 68 dbra D0,L6 | ... 69 70 .page 71 72 move.w VCE,D0 | calculate FPU offset for voice 73 move.w #9,D1 | ... 74 asl.w D1,D0 | ... 75 asl.w #1,D0 | ... 76 ext.l D0 | ... 77 move.l D0,P1 | ... 78 move.l D0,P3 | ... 79 add.l #_io_fpu,P1 | point P1 at FPU WS A 80 add.l #0x202,P1 | ... 81 lea 1778(IP),P2 | point P2 at instdef WS A 82 add.l #_io_fpu,P3 | point P3 at FPU WS B 83 add.l #2,P3 | ... 84 lea 2858(IP),P4 | point P4 at instdef WS B 85 move.w #253,D0 | setup move count 86 87 87 .ifne DOUBLED 88 move.l P1,-(a7) *save P1 on stack89 move.l P2,-(a7) *save P2 on stack90 move.l P3,-(a7) *save P3 on stack91 move.l P4,-(a7) *save P4 on stack92 move.w D0,-(a7) *save D0 on stack88 move.l P1,-(a7) | save P1 on stack 89 move.l P2,-(a7) | save P2 on stack 90 move.l P3,-(a7) | save P3 on stack 91 move.l P4,-(a7) | save P4 on stack 92 move.w D0,-(a7) | save D0 on stack 93 93 .endc 94 * 95 move.w SR,OLDSR *turn off FPU interrupts96 move.w # $2200,SR *...97 * 98 L10: move.w (P2)+,(P1)+ *set FPU WS A from instdef99 nop *delay for FPU timing100 nop *...101 nop *...102 move.w (P4)+,(P3)+ *set FPU WS B from instdef103 nop *delay for FPU timing104 nop *...105 dbra D0,L10 *loop until done106 * 94 95 move.w SR,OLDSR | turn off FPU interrupts 96 move.w #0x2200,SR | ... 97 98 L10: move.w (P2)+,(P1)+ | set FPU WS A from instdef 99 nop | delay for FPU timing 100 nop | ... 101 nop | ... 102 move.w (P4)+,(P3)+ | set FPU WS B from instdef 103 nop | delay for FPU timing 104 nop | ... 105 dbra D0,L10 | loop until done 106 107 107 .ifne DOUBLED 108 move.w (a7)+,D0 *restore D0 from stack109 movea.l (a7)+,P4 *restore P4 from stack110 movea.l (a7)+,P3 *restore P3 from stack111 movea.l (a7)+,P2 *restore P2 from stack112 movea.l (a7)+,P1 *restore P1 from stack113 * 114 L10A: move.w (P2)+,(P1)+ *set FPU WS A from instdef115 nop *delay for FPU timing116 nop *...117 nop *...118 move.w (P4)+,(P3)+ *set FPU WS B from instdef119 nop *delay for FPU timing120 nop *...121 dbra D0,L10A *loop until done122 * 108 move.w (a7)+,D0 | restore D0 from stack 109 movea.l (a7)+,P4 | restore P4 from stack 110 movea.l (a7)+,P3 | restore P3 from stack 111 movea.l (a7)+,P2 | restore P2 from stack 112 movea.l (a7)+,P1 | restore P1 from stack 113 114 L10A: move.w (P2)+,(P1)+ | set FPU WS A from instdef 115 nop | delay for FPU timing 116 nop | ... 117 nop | ... 118 move.w (P4)+,(P3)+ | set FPU WS B from instdef 119 nop | delay for FPU timing 120 nop | ... 121 dbra D0,L10A | loop until done 122 123 123 .endc 124 * 125 move.w OLDSR,SR *enable FPU interrupts126 * 127 .page 128 * 129 move.w VCE,A0 *instmod[vce] = FALSE130 add.l A0,A0 *...131 add.l #_instmod,A0 *...132 clr.w (A0) *...133 move.w VCE,A0 *s_inst[vce] = ins134 add.l A0,A0 *...135 add.l #_s_inst,A0 *...136 move.w INS(A6),(A0) *...137 move.b 70(IP),SYNC *get config bits138 ext.w SYNC *...139 asl.w #8,SYNC *...140 btst #2,74(IP) *sync 2nd osc141 beq L15 *...142 * 143 ori.w # $2000,SYNC *...144 * 145 L15: btst #2,75(IP) *sync 3rd osc146 beq L16 *...147 * 148 ori.w # $4000,SYNC *...149 * 150 L16: btst #2,76(IP) *sync 4th osc151 beq L17 *...152 * 153 ori.w # $8000,SYNC *...154 * 155 L17: move.w VCE,A0 *send sync to FPU156 add.l A0,A0 *...157 add.l #_io_fpu,A0 *...158 add.l # $5FE0,A0 *...159 move.w SYNC,(A0) *...160 * 161 L2: move.w #1,(sp) *execkey(-1, 0, vce, 1)162 move.w VCE,-(sp) *...163 clr.w -(sp) *...164 move.w #-1,-(sp) *...165 jsr _execkey *...166 addq.l #6,sp *...167 tst.l (sp)+ *clean up stack168 movem.l (sp)+,SYNC-VCE/P2-IP *restore registers169 unlk A6 *unlink stack frames170 rts *return171 * 172 .page 173 * 124 125 move.w OLDSR,SR | enable FPU interrupts 126 127 .page 128 129 move.w VCE,A0 | instmod[vce] = FALSE 130 add.l A0,A0 | ... 131 add.l #_instmod,A0 | ... 132 clr.w (A0) | ... 133 move.w VCE,A0 | s_inst[vce] = ins 134 add.l A0,A0 | ... 135 add.l #_s_inst,A0 | ... 136 move.w INS(A6),(A0) | ... 137 move.b 70(IP),SYNC | get config bits 138 ext.w SYNC | ... 139 asl.w #8,SYNC | ... 140 btst #2,74(IP) | sync 2nd osc 141 beq L15 | ... 142 143 ori.w #0x2000,SYNC | ... 144 145 L15: btst #2,75(IP) | sync 3rd osc 146 beq L16 | ... 147 148 ori.w #0x4000,SYNC | ... 149 150 L16: btst #2,76(IP) | sync 4th osc 151 beq L17 | ... 152 153 ori.w #0x8000,SYNC | ... 154 155 L17: move.w VCE,A0 | send sync to FPU 156 add.l A0,A0 | ... 157 add.l #_io_fpu,A0 | ... 158 add.l #0x5FE0,A0 | ... 159 move.w SYNC,(A0) | ... 160 161 L2: move.w #1,(sp) | execkey(-1, 0, vce, 1) 162 move.w VCE,-(sp) | ... 163 clr.w -(sp) | ... 164 move.w #-1,-(sp) | ... 165 jsr _execkey | ... 166 addq.l #6,sp | ... 167 tst.l (sp)+ | clean up stack 168 movem.l (sp)+,SYNC-VCE/P2-IP | restore registers 169 unlk A6 | unlink stack frames 170 rts | return 171 172 .page 173 174 174 .data 175 * 176 *vibtabl -- voice and instrument buffer offset table177 *------- ----------------------------------------178 vibtabl: .dc.l 0 *0179 .dc.l 3938 *1180 .dc.l 7876 *2181 .dc.l 11814 *3182 .dc.l 15752 *4183 .dc.l 19690 *5184 .dc.l 23628 *6185 .dc.l 27566 *7186 .dc.l 31504 *8187 .dc.l 35442 *9188 .dc.l 39380 *10189 .dc.l 43318 *11190 .dc.l 47256 *12191 .dc.l 51194 *13192 .dc.l 55132 *14193 .dc.l 59070 *15194 .dc.l 63008 *16195 .dc.l 66946 *17196 .dc.l 70884 *18197 .dc.l 74822 *19198 .dc.l 78760 *20199 .dc.l 82698 *21200 .dc.l 86636 *22201 .dc.l 90574 *23202 .dc.l 94512 *24203 .dc.l 98450 *25204 .dc.l 102388 *26205 .dc.l 106326 *27206 .dc.l 110264 *28207 .dc.l 114202 *29208 .dc.l 118140 *30209 .dc.l 122078 *31210 .dc.l 126016 *32211 .dc.l 129954 *33212 .dc.l 133892 *34213 .dc.l 137830 *35214 .dc.l 141768 *36215 .dc.l 145706 *37216 .dc.l 149644 *38217 .dc.l 153582 *39218 .dc.l 157520 *40219 * 175 176 | vibtabl -- voice and instrument buffer offset table 177 | ------- ---------------------------------------- 178 vibtabl: .dc.l 0 | 0 179 .dc.l 3938 | 1 180 .dc.l 7876 | 2 181 .dc.l 11814 | 3 182 .dc.l 15752 | 4 183 .dc.l 19690 | 5 184 .dc.l 23628 | 6 185 .dc.l 27566 | 7 186 .dc.l 31504 | 8 187 .dc.l 35442 | 9 188 .dc.l 39380 | 10 189 .dc.l 43318 | 11 190 .dc.l 47256 | 12 191 .dc.l 51194 | 13 192 .dc.l 55132 | 14 193 .dc.l 59070 | 15 194 .dc.l 63008 | 16 195 .dc.l 66946 | 17 196 .dc.l 70884 | 18 197 .dc.l 74822 | 19 198 .dc.l 78760 | 20 199 .dc.l 82698 | 21 200 .dc.l 86636 | 22 201 .dc.l 90574 | 23 202 .dc.l 94512 | 24 203 .dc.l 98450 | 25 204 .dc.l 102388 | 26 205 .dc.l 106326 | 27 206 .dc.l 110264 | 28 207 .dc.l 114202 | 29 208 .dc.l 118140 | 30 209 .dc.l 122078 | 31 210 .dc.l 126016 | 32 211 .dc.l 129954 | 33 212 .dc.l 133892 | 34 213 .dc.l 137830 | 35 214 .dc.l 141768 | 36 215 .dc.l 145706 | 37 216 .dc.l 149644 | 38 217 .dc.l 153582 | 39 218 .dc.l 157520 | 40 219 220 220 .end
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