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Changeset 4f508e6 in buchla-68k for vlib/vbank.s
- Timestamp:
- 07/01/2017 02:34:46 PM (7 years ago)
- Branches:
- master
- Children:
- 08e1da1
- Parents:
- f40a309
- File:
-
- 1 edited
-
vlib/vbank.s (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
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vlib/vbank.s
rf40a309 r4f508e6 1 *------------------------------------------------------------------------------2 *vbank.s -- VSDD bank switching control functions3 *Version 3 -- 1989-12-19 -- D.N. Lynx Crowe4 * 5 *unsigned6 *vbank(b)7 *unsigned b;8 * 9 *Set VSDD Data Segment bank to b.10 *Return old bank select value.11 * 12 * 13 *vfwait()14 * 15 *Wait for a FRAMESTOP update to transpire.16 *------------------------------------------------------------------------------1 | ------------------------------------------------------------------------------ 2 | vbank.s -- VSDD bank switching control functions 3 | Version 3 -- 1989-12-19 -- D.N. Lynx Crowe 4 5 | unsigned 6 | vbank(b) 7 | unsigned b; 8 9 | Set VSDD Data Segment bank to b. 10 | Return old bank select value. 11 12 13 | vfwait() 14 15 | Wait for a FRAMESTOP update to transpire. 16 | ------------------------------------------------------------------------------ 17 17 .xdef _vbank 18 18 .xdef _vfwait 19 * 19 20 20 .xref _v_regs 21 * 21 22 22 .text 23 * 24 B .equ825 * 26 OLDB .equd627 NEWB .equd728 * 29 VSDD_R5 .equ1030 VSDD_R11 .equ2231 * 32 VT_BASE .equ 128 *word offset of VSDD Access Table33 * 34 VT_1 .equ VT_BASE+300 *high time35 VT_2 .equ VT_BASE+2 *low time36 * 23 24 B = 8 25 26 OLDB = d6 27 NEWB = d7 28 29 VSDD_R5 = 10 30 VSDD_R11 = 22 31 32 VT_BASE = 128 | word offset of VSDD Access Table 33 34 VT_1 = VT_BASE+300 | high time 35 VT_2 = VT_BASE+2 | low time 36 37 37 .page 38 * ------------------------------------------------------------------------------ 39 * vbank(b) -- change VSDD Data Segment bank to b. Return old bank. 40 * Assumes a 128K byte window, sets S15..S11 to zero. 41 * ------------------------------------------------------------------------------ 42 * 38 | ------------------------------------------------------------------------------ 39 | vbank(b) -- change VSDD Data Segment bank to b. Return old bank. 40 | Assumes a 128K byte window, sets S15..S11 to zero. 41 | ------------------------------------------------------------------------------ 43 42 44 _vbank: link a6,#0 * link stack frames 45 movem.l d5-d7,-(sp) * preserve registers 46 move.w _v_regs+VSDD_R5,OLDB * get v_regs[5] 47 lsr.w #6,OLDB * extract BS bits 48 move.w OLDB,d0 * ... 49 andi.w #2,d0 * ... 50 move.w OLDB,d1 * ... 51 lsr.w #2,d1 * ... 52 andi.w #1,d1 * ... 53 or.w d1,d0 * ... 54 move.w d0,OLDB * ... 55 cmp.w B(a6),OLDB * see if they're what we want 56 bne L2 * jump if not 57 * 58 move.w B(a6),d0 * setup to return b 43 44 _vbank: link a6,#0 | link stack frames 45 movem.l d5-d7,-(sp) | preserve registers 46 move.w _v_regs+VSDD_R5,OLDB | get v_regs[5] 47 lsr.w #6,OLDB | extract BS bits 48 move.w OLDB,d0 | ... 49 andi.w #2,d0 | ... 50 move.w OLDB,d1 | ... 51 lsr.w #2,d1 | ... 52 andi.w #1,d1 | ... 53 or.w d1,d0 | ... 54 move.w d0,OLDB | ... 55 cmp.w B(a6),OLDB | see if they're what we want 56 bne L2 | jump if not 57 58 move.w B(a6),d0 | setup to return b 59 59 bra L1 60 * 61 L2: move.w B(a6),NEWB *get bank bits from b62 lsl.w #6,NEWB *shift bits from b into BS bits63 move.w NEWB,d0 *...64 andi.w #128,d0 *...65 lsl.w #2,NEWB *...66 andi.w #256,NEWB *...67 or.w NEWB,d0 *...68 move.w d0,_v_regs+VSDD_R5 *set v_regs[5] with new BS bits69 * 70 vw1b: cmp.w #VT_1,_v_regs+VSDD_R11 *wait for FRAMESTOP71 bcc vw1b *...72 * 73 vw2b: cmp.w #VT_1,_v_regs+VSDD_R11 *...74 bcs vw2b *...75 * 76 vw3b: cmp.w #VT_1,_v_regs+VSDD_R11 *...77 bcc vw3b *...78 * 79 vw4b: cmp.w #VT_2,_v_regs+VSDD_R11 *...80 bcs vw4b *...81 * 82 move.w OLDB,d0 *setup to return OLDB83 * 84 L1: tst.l (sp)+ *fixup stack85 movem.l (sp)+,OLDB-NEWB *restore registers86 unlk a6 *unlink stack frames87 rts *return to caller88 * 60 61 L2: move.w B(a6),NEWB | get bank bits from b 62 lsl.w #6,NEWB | shift bits from b into BS bits 63 move.w NEWB,d0 | ... 64 andi.w #128,d0 | ... 65 lsl.w #2,NEWB | ... 66 andi.w #256,NEWB | ... 67 or.w NEWB,d0 | ... 68 move.w d0,_v_regs+VSDD_R5 | set v_regs[5] with new BS bits 69 70 vw1b: cmp.w #VT_1,_v_regs+VSDD_R11 | wait for FRAMESTOP 71 bcc vw1b | ... 72 73 vw2b: cmp.w #VT_1,_v_regs+VSDD_R11 | ... 74 bcs vw2b | ... 75 76 vw3b: cmp.w #VT_1,_v_regs+VSDD_R11 | ... 77 bcc vw3b | ... 78 79 vw4b: cmp.w #VT_2,_v_regs+VSDD_R11 | ... 80 bcs vw4b | ... 81 82 move.w OLDB,d0 | setup to return OLDB 83 84 L1: tst.l (sp)+ | fixup stack 85 movem.l (sp)+,OLDB-NEWB | restore registers 86 unlk a6 | unlink stack frames 87 rts | return to caller 88 89 89 .page 90 * 91 *------------------------------------------------------------------------------92 *vfwait() -- Wait for a FRAMESTOP update to transpire.93 *------------------------------------------------------------------------------94 * 95 _vfwait: link a6,#0 *link stack frames96 * 97 vw1a: cmp.w #VT_1,_v_regs+VSDD_R11 *wait for FRAMESTOP98 bcc vw1a *...99 * 100 vw2a: cmp.w #VT_1,_v_regs+VSDD_R11 *...101 bcs vw2a *...102 * 103 vw3a: cmp.w #VT_1,_v_regs+VSDD_R11 *...104 bcc vw3a *...105 * 106 vw4a: cmp.w #VT_2,_v_regs+VSDD_R11 *...107 bcs vw4a *...108 * 109 unlk a6 *unlink stack frames110 rts *return to caller111 * 90 91 | ------------------------------------------------------------------------------ 92 | vfwait() -- Wait for a FRAMESTOP update to transpire. 93 | ------------------------------------------------------------------------------ 94 95 _vfwait: link a6,#0 | link stack frames 96 97 vw1a: cmp.w #VT_1,_v_regs+VSDD_R11 | wait for FRAMESTOP 98 bcc vw1a | ... 99 100 vw2a: cmp.w #VT_1,_v_regs+VSDD_R11 | ... 101 bcs vw2a | ... 102 103 vw3a: cmp.w #VT_1,_v_regs+VSDD_R11 | ... 104 bcc vw3a | ... 105 106 vw4a: cmp.w #VT_2,_v_regs+VSDD_R11 | ... 107 bcs vw4a | ... 108 109 unlk a6 | unlink stack frames 110 rts | return to caller 111 112 112 .end
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