[a06aa8b] | 1 | /*
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| 2 | * Copyright (C) 2017 The Contributors
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| 3 | *
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| 4 | * This program is free software: you can redistribute it and/or modify
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| 5 | * it under the terms of the GNU General Public License as published by
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| 6 | * the Free Software Foundation, either version 3 of the License, or (at
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| 7 | * your option) any later version.
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| 8 | *
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| 9 | * This program is distributed in the hope that it will be useful, but
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| 10 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 12 | * General Public License for more details.
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| 13 | *
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| 14 | * A copy of the GNU General Public License can be found in the file
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| 15 | * "gpl-v3.txt" in the top directory of this repository.
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| 16 | */
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| 17 |
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[ff8d800] | 18 | #include <all.h>
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| 19 |
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| 20 | #define ver(...) { \
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| 21 | if (cpu_verbose) { \
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| 22 | SDL_LogVerbose(SDL_LOG_CATEGORY_APPLICATION, __VA_ARGS__); \
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| 23 | } \
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| 24 | }
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| 25 |
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[a06aa8b] | 26 | bool cpu_verbose = false;
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| 27 |
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[ff8d800] | 28 | #define CYCLES 10
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| 29 |
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[a06aa8b] | 30 | #define RAM_START 0x0
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| 31 | #define RAM_SIZE 0x100000
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| 32 |
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| 33 | #define ROM_START 0x100000
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| 34 | #define ROM_SIZE 0x10000
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| 35 |
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| 36 | typedef void (*hw_init_t)(void);
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| 37 | typedef void (*hw_quit_t)(void);
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| 38 | typedef void (*hw_exec_t)(void);
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| 39 | typedef uint32_t (*hw_read_t)(uint32_t off, int32_t sz);
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| 40 | typedef void (*hw_write_t)(uint32_t off, int32_t sz, uint32_t val);
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| 41 |
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| 42 | typedef struct {
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| 43 | uint32_t addr_beg;
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| 44 | uint32_t addr_end;
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| 45 | hw_init_t init;
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| 46 | hw_quit_t quit;
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| 47 | hw_exec_t exec;
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| 48 | hw_read_t read;
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| 49 | hw_write_t write;
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| 50 | } hw_t;
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[ff8d800] | 51 |
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| 52 | static bool reset = true;
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| 53 |
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[a06aa8b] | 54 | static uint8_t ram_data[RAM_SIZE];
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| 55 | static uint8_t rom_data[ROM_SIZE];
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| 56 |
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[b909777] | 57 | static uint32_t ram_rd_beg = 0x10000000;
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| 58 | static uint32_t ram_rd_end = 0x10000000;
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| 59 | static uint32_t ram_wr_beg = 0x10000000;
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| 60 | static uint32_t ram_wr_end = 0x10000000;
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[a06aa8b] | 61 |
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| 62 | static uint32_t rom_rd_beg;
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| 63 | static uint32_t rom_rd_end;
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| 64 | static uint32_t rom_wr_beg;
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| 65 | static uint32_t rom_wr_end;
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| 66 |
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| 67 | static hw_t hw_map[] = {
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| 68 | { 0x180000, 0x200000, fpu_init, fpu_quit, fpu_exec, fpu_read, fpu_write },
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| 69 | { 0x200000, 0x280000, vid_init, vid_quit, vid_exec, vid_read, vid_write },
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| 70 | { 0x3a0001, 0x3a4001, tim_init, tim_quit, tim_exec, tim_read, tim_write },
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| 71 | { 0x3a4001, 0x3a8001, lcd_init, lcd_quit, lcd_exec, lcd_read, lcd_write },
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| 72 | { 0x3a8001, 0x3ac001, ser_init, ser_quit, ser_exec, ser_read, ser_write },
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| 73 | { 0x3ac001, 0x3b0001, mid_init, mid_quit, mid_exec, mid_read, mid_write },
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| 74 | { 0x3b0001, 0x3b4001, fdd_init, fdd_quit, fdd_exec, fdd_read, fdd_write },
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| 75 | { 0x3b4001, 0x3b8001, snd_init, snd_quit, snd_exec, snd_read, snd_write },
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| 76 | { 0x3b8001, 0x3bc001, led_init, led_quit, led_exec, led_read, led_write },
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| 77 | { 0x3bc001, 0x3c0001, kbd_init, kbd_quit, kbd_exec, kbd_read, kbd_write }
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| 78 | };
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| 79 |
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| 80 | static hw_t *hw_by_addr(uint32_t addr)
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| 81 | {
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| 82 | for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
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| 83 | if (addr >= hw_map[i].addr_beg && addr < hw_map[i].addr_end) {
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| 84 | return hw_map + i;
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| 85 | }
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| 86 | }
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| 87 |
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| 88 | return NULL;
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| 89 | }
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| 90 |
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| 91 | static void hw_init(void)
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| 92 | {
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[b909777] | 93 | ver("initializing hardware");
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| 94 |
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[a06aa8b] | 95 | for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
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| 96 | hw_map[i].init();
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| 97 | }
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| 98 | }
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| 99 |
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| 100 | static void hw_exec(void)
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| 101 | {
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| 102 | for (int32_t i = 0; i < ARRAY_COUNT(hw_map); ++i) {
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| 103 | hw_map[i].exec();
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| 104 | }
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| 105 | }
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| 106 |
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| 107 | static uint32_t hw_off(hw_t *hw, uint32_t addr)
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| 108 | {
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| 109 | if ((hw->addr_beg & 0x1) == 0) {
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| 110 | return addr - hw->addr_beg;
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| 111 | }
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| 112 |
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| 113 | return (addr - hw->addr_beg) / 2;
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| 114 | }
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| 115 |
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[b909777] | 116 | static void bios_init(const char *bios)
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| 117 | {
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| 118 | ver("loading BIOS file %s", bios);
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| 119 |
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| 120 | SDL_RWops *ops = SDL_RWFromFile(bios, "rb");
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| 121 |
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| 122 | if (ops == NULL) {
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| 123 | fail("error while opening BIOS file %s", bios);
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| 124 | }
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| 125 |
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| 126 | if (SDL_ReadBE16(ops) != 0x601b) {
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| 127 | fail("invalid BIOS file %s", bios);
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| 128 | }
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| 129 |
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| 130 | uint32_t text_len = SDL_ReadBE32(ops);
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| 131 | uint32_t data_len = SDL_ReadBE32(ops);
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| 132 | uint32_t bss_len = SDL_ReadBE32(ops);
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| 133 |
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| 134 | SDL_ReadBE32(ops);
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| 135 | SDL_ReadBE32(ops);
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| 136 |
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| 137 | uint32_t text_loc = SDL_ReadBE32(ops);
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| 138 |
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| 139 | SDL_ReadBE16(ops);
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| 140 |
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| 141 | uint32_t data_loc = SDL_ReadBE32(ops);
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| 142 | uint32_t bss_loc = SDL_ReadBE32(ops);
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| 143 |
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| 144 | ver("text 0x%x@0x%x data 0x%x@0x%x bss 0x%x@0x%x",
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| 145 | text_len, text_loc, data_len, data_loc, bss_len, bss_loc);
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| 146 |
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| 147 | size_t load_len = (size_t)SDL_RWsize(ops) - 36;
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| 148 |
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| 149 | if (load_len != text_len + data_len) {
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| 150 | fail("corrupted BIOS file %s", bios);
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| 151 | }
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| 152 |
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| 153 | size_t loaded = 0;
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| 154 |
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| 155 | while (loaded < load_len) {
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| 156 | size_t n_rd = SDL_RWread(ops, rom_data + loaded, 1, load_len - loaded);
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| 157 |
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| 158 | if (n_rd == 0) {
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| 159 | fail("error while reading BIOS file %s", bios);
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| 160 | }
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| 161 |
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| 162 | loaded += n_rd;
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| 163 | }
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| 164 |
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| 165 | SDL_RWclose(ops);
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| 166 | }
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| 167 |
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[ff8d800] | 168 | uint32_t m68k_read_disassembler_8(uint32_t addr)
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| 169 | {
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[a06aa8b] | 170 | return m68k_read_memory_8(addr);
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[ff8d800] | 171 | }
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| 172 |
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| 173 | uint32_t m68k_read_disassembler_16(uint32_t addr)
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| 174 | {
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[a06aa8b] | 175 | return m68k_read_memory_16(addr);
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[ff8d800] | 176 | }
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| 177 |
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| 178 | uint32_t m68k_read_disassembler_32(uint32_t addr)
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| 179 | {
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[a06aa8b] | 180 | return m68k_read_memory_32(addr);
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[ff8d800] | 181 | }
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| 182 |
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| 183 | uint32_t m68k_read_memory_8(uint32_t addr)
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| 184 | {
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| 185 | ver("mem rd 0x%08x:8", addr);
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[a06aa8b] | 186 |
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| 187 | if (addr >= ram_rd_beg && addr <= ram_rd_end - 1) {
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| 188 | return ram_data[addr - RAM_START];
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| 189 | }
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| 190 |
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| 191 | if (addr >= rom_rd_beg && addr <= rom_rd_end - 1) {
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| 192 | return rom_data[addr - ROM_START];
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| 193 | }
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| 194 |
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| 195 | hw_t *hw = hw_by_addr(addr);
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| 196 |
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| 197 | if (hw != NULL) {
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| 198 | return hw->read(hw_off(hw, addr), 1);
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| 199 | }
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| 200 |
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| 201 | fail("invalid read 0x%08x:8", addr);
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[ff8d800] | 202 | }
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| 203 |
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| 204 | uint32_t m68k_read_memory_16(uint32_t addr)
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| 205 | {
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| 206 | ver("mem rd 0x%08x:16", addr);
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| 207 |
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[a06aa8b] | 208 | if (addr >= ram_rd_beg && addr <= ram_rd_end - 2) {
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| 209 | return
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| 210 | ((uint32_t)ram_data[addr - RAM_START + 0] << 8) |
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| 211 | ((uint32_t)ram_data[addr - RAM_START + 1] << 0);
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| 212 | }
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| 213 |
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| 214 | if (addr >= rom_rd_beg && addr <= rom_rd_end - 2) {
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| 215 | return
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| 216 | ((uint32_t)rom_data[addr - ROM_START + 0] << 8) |
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| 217 | ((uint32_t)rom_data[addr - ROM_START + 1] << 0);
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[ff8d800] | 218 | }
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| 219 |
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[a06aa8b] | 220 | hw_t *hw = hw_by_addr(addr);
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| 221 |
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| 222 | if (hw != NULL) {
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| 223 | return hw->read(hw_off(hw, addr), 2);
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[ff8d800] | 224 | }
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| 225 |
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[a06aa8b] | 226 | fail("invalid read 0x%08x:16", addr);
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[ff8d800] | 227 | }
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| 228 |
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| 229 | uint32_t m68k_read_memory_32(uint32_t addr)
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| 230 | {
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| 231 | ver("mem rd 0x%08x:32", addr);
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| 232 |
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| 233 | if (reset) {
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| 234 | if (addr == 0) {
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[b909777] | 235 | addr += ROM_START;
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[ff8d800] | 236 | }
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| 237 |
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[b909777] | 238 | else if (addr == 4) {
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| 239 | addr += ROM_START;
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[ff8d800] | 240 | reset = false;
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| 241 | }
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[b909777] | 242 | else {
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| 243 | fail("invalid reset sequence");
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| 244 | }
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[ff8d800] | 245 | }
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| 246 |
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[a06aa8b] | 247 | if (addr >= ram_rd_beg && addr <= ram_rd_end - 4) {
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| 248 | return
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| 249 | ((uint32_t)ram_data[addr - RAM_START + 0] << 24) |
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| 250 | ((uint32_t)ram_data[addr - RAM_START + 1] << 16) |
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| 251 | ((uint32_t)ram_data[addr - RAM_START + 2] << 8) |
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| 252 | ((uint32_t)ram_data[addr - RAM_START + 3] << 0);
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| 253 | }
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| 254 |
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| 255 | if (addr >= rom_rd_beg && addr <= rom_rd_end - 4) {
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| 256 | return
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| 257 | ((uint32_t)rom_data[addr - ROM_START + 0] << 24) |
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| 258 | ((uint32_t)rom_data[addr - ROM_START + 1] << 16) |
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| 259 | ((uint32_t)rom_data[addr - ROM_START + 2] << 8) |
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| 260 | ((uint32_t)rom_data[addr - ROM_START + 3] << 0);
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| 261 | }
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| 262 |
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| 263 | hw_t *hw = hw_by_addr(addr);
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| 264 |
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| 265 | if (hw != NULL) {
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| 266 | return hw->read(hw_off(hw, addr), 4);
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| 267 | }
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| 268 |
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| 269 | fail("invalid read 0x%08x:32", addr);
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[ff8d800] | 270 | }
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| 271 |
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| 272 | void m68k_write_memory_8(uint32_t addr, uint32_t val)
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| 273 | {
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| 274 | ver("mem wr 0x%08x:8 0x%02x", addr, val);
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[a06aa8b] | 275 |
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| 276 | if (addr >= ram_wr_beg && addr <= ram_wr_end - 1) {
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| 277 | ram_data[addr - RAM_START] = (uint8_t)val;
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| 278 | return;
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| 279 | }
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| 280 |
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| 281 | if (addr >= rom_wr_beg && addr <= rom_wr_end - 1) {
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| 282 | // ROM has its BSS section in RAM.
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| 283 | ram_data[addr - RAM_START] = (uint8_t)val;
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| 284 | return;
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| 285 | }
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| 286 |
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| 287 | hw_t *hw = hw_by_addr(addr);
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| 288 |
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| 289 | if (hw != NULL) {
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| 290 | hw->write(hw_off(hw, addr), 1, val);
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| 291 | return;
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| 292 | }
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| 293 |
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| 294 | fail("invalid write 0x%08x:8 0x%02x", addr, val);
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[ff8d800] | 295 | }
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| 296 |
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| 297 | void m68k_write_memory_16(uint32_t addr, uint32_t val)
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| 298 | {
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| 299 | ver("mem wr 0x%08x:16 0x%04x", addr, val);
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[a06aa8b] | 300 |
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| 301 | if (addr >= ram_wr_beg && addr <= ram_wr_end - 2) {
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| 302 | ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 8);
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| 303 | ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 0);
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| 304 | return;
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| 305 | }
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| 306 |
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| 307 | if (addr >= rom_wr_beg && addr <= rom_wr_end - 2) {
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| 308 | // ROM has its BSS section in RAM.
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| 309 | ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 8);
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| 310 | ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 0);
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| 311 | return;
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| 312 | }
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| 313 |
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| 314 | hw_t *hw = hw_by_addr(addr);
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| 315 |
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| 316 | if (hw != NULL) {
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| 317 | hw->write(hw_off(hw, addr), 2, val);
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| 318 | return;
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| 319 | }
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| 320 |
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| 321 | fail("invalid write 0x%08x:16 0x%04x", addr, val);
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[ff8d800] | 322 | }
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| 323 |
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| 324 | void m68k_write_memory_32(uint32_t addr, uint32_t val)
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| 325 | {
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| 326 | ver("mem wr 0x%08x:32 0x%08x", addr, val);
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[a06aa8b] | 327 |
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| 328 | if (addr >= ram_wr_beg && addr <= ram_wr_end - 4) {
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| 329 | ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 24);
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| 330 | ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 16);
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| 331 | ram_data[addr - RAM_START + 2] = (uint8_t)(val >> 8);
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| 332 | ram_data[addr - RAM_START + 3] = (uint8_t)(val >> 0);
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| 333 | return;
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| 334 | }
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| 335 |
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| 336 | if (addr >= rom_wr_beg && addr <= rom_wr_end - 4) {
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| 337 | // ROM has its BSS section in RAM.
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| 338 | ram_data[addr - RAM_START + 0] = (uint8_t)(val >> 24);
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| 339 | ram_data[addr - RAM_START + 1] = (uint8_t)(val >> 16);
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| 340 | ram_data[addr - RAM_START + 2] = (uint8_t)(val >> 8);
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| 341 | ram_data[addr - RAM_START + 3] = (uint8_t)(val >> 0);
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| 342 | return;
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| 343 | }
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| 344 |
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| 345 | hw_t *hw = hw_by_addr(addr);
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| 346 |
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| 347 | if (hw != NULL) {
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| 348 | hw->write(hw_off(hw, addr), 4, val);
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| 349 | return;
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| 350 | }
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| 351 |
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| 352 | fail("invalid write 0x%08x:32 0x%08x", addr, val);
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[ff8d800] | 353 | }
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| 354 |
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[b909777] | 355 | void cpu_loop(const char *bios)
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[ff8d800] | 356 | {
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[b909777] | 357 | ver("entering CPU loop");
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| 358 |
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[a06aa8b] | 359 | hw_init();
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[b909777] | 360 | bios_init(bios);
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[ff8d800] | 361 |
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[a06aa8b] | 362 | ver("starting CPU");
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[ff8d800] | 363 | m68k_init();
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| 364 | m68k_set_cpu_type(M68K_CPU_TYPE_68000);
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| 365 | m68k_pulse_reset();
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| 366 |
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[a06aa8b] | 367 | for (int32_t c = 0; c < 5; ++c) {
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[ff8d800] | 368 | m68k_execute(CYCLES);
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[a06aa8b] | 369 | hw_exec();
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[ff8d800] | 370 | }
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| 371 | }
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